From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
jani.nikula@intel.com
Subject: [PATCH v12 3/9] gpu/drm/i915: Update indentation for VRR registers and bits
Date: Wed, 5 Jun 2024 17:57:56 +0530 [thread overview]
Message-ID: <20240605122802.488124-4-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20240605122802.488124-1-mitulkumar.ajitkumar.golani@intel.com>
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0569a23b83b2..6b39211b5469 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1152,7 +1152,7 @@
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
#define _TRANS_VRR_CTL_D 0x63420
-#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
+#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
@@ -1160,7 +1160,8 @@
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
-#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \
+ (x))
#define _TRANS_VRR_VMAX_A 0x60424
#define _TRANS_VRR_VMAX_B 0x61424
@@ -1190,7 +1191,7 @@
#define _TRANS_VRR_STATUS_B 0x6142C
#define _TRANS_VRR_STATUS_C 0x6242C
#define _TRANS_VRR_STATUS_D 0x6342C
-#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
@@ -1241,7 +1242,7 @@
#define TRANS_PUSH_SEND REG_BIT(30)
#define _TRANS_VRR_VSYNC_A 0x60078
-#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
+#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
--
2.25.1
next prev parent reply other threads:[~2024-06-05 12:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-05 12:27 [PATCH v12 0/9] Implement CMRR Support Mitul Golani
2024-06-05 12:27 ` [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency Mitul Golani
2024-06-05 12:49 ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest Mitul Golani
2024-06-05 12:50 ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` Mitul Golani [this message]
2024-06-05 12:27 ` [PATCH v12 4/9] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-05 12:27 ` [PATCH v12 5/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-05 12:27 ` [PATCH v12 6/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-06-05 12:28 ` [PATCH v12 7/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-05 12:28 ` [PATCH v12 8/9] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-05 12:28 ` [PATCH v12 9/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-06-05 14:38 ` ✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev12) Patchwork
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