From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
jani.nikula@intel.com
Subject: [PATCH v12 6/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Date: Wed, 5 Jun 2024 17:57:59 +0530 [thread overview]
Message-ID: <20240605122802.488124-7-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20240605122802.488124-1-mitulkumar.ajitkumar.golani@intel.com>
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++--
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ } else {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 1aeb0cd45068..577b0abb66db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -123,4 +123,6 @@
#define _TRANS_CMRR_N_HI_A 0x604FC
#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
+
#endif /* __INTEL_VRR_REGS__ */
--
2.25.1
next prev parent reply other threads:[~2024-06-05 12:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-05 12:27 [PATCH v12 0/9] Implement CMRR Support Mitul Golani
2024-06-05 12:27 ` [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency Mitul Golani
2024-06-05 12:49 ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest Mitul Golani
2024-06-05 12:50 ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` [PATCH v12 3/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
2024-06-05 12:27 ` [PATCH v12 4/9] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-05 12:27 ` [PATCH v12 5/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-05 12:27 ` Mitul Golani [this message]
2024-06-05 12:28 ` [PATCH v12 7/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-05 12:28 ` [PATCH v12 8/9] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-05 12:28 ` [PATCH v12 9/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-06-05 14:38 ` ✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev12) Patchwork
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