From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: animesh.manna@intel.com, mika.kahola@intel.com,
"Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH 3/9] drm/i915/alpm: Fix port clock usage in AUX Less wake time calculation
Date: Tue, 18 Jun 2024 08:30:20 +0300 [thread overview]
Message-ID: <20240618053026.3268759-4-jouni.hogander@intel.com> (raw)
In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com>
Port clock is link rate in 10 kbit/s units. Take this into account when
calculating AUX Less wake time.
Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 90072f6e3a33..67848fc1e24d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -125,7 +125,8 @@ static int _lnl_compute_aux_less_wake_time(int port_clock)
int tsilence_max = 180;
int t1 = 50 * 1000;
int tps4 = 252;
- int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock;
+ /* port_clock is link rate in 10kbit/s units */
+ int tml_phy_lock = 1000 * 1000 * tps4 / port_clock;
int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
int t2 = num_ml_phy_lock * tml_phy_lock;
int tcds = 1 * t2;
--
2.34.1
next prev parent reply other threads:[~2024-06-18 5:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 5:30 [PATCH 0/9] Panel Replay eDP more prepare patches Jouni Högander
2024-06-18 5:30 ` [PATCH 1/9] drm/i915/psr: Set SU area width as pipe src width Jouni Högander
2024-06-18 10:23 ` Kahola, Mika
2024-06-18 5:30 ` [PATCH 2/9] drm/i915/display: Wa 16021440873 is writing wrong register Jouni Högander
2024-06-18 13:29 ` Kahola, Mika
2024-06-19 9:51 ` Jani Nikula
2024-06-19 12:11 ` Hogander, Jouni
2024-06-18 5:30 ` Jouni Högander [this message]
2024-06-18 5:30 ` [PATCH 4/9] drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter Jouni Högander
2024-06-18 12:00 ` Manna, Animesh
2024-06-18 5:30 ` [PATCH 5/9] drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set Jouni Högander
2024-06-18 12:03 ` Manna, Animesh
2024-06-18 5:30 ` [PATCH 6/9] drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only Jouni Högander
2024-06-18 5:30 ` [PATCH 7/9] drm/i915/psr: Add new debug bit to disable Panel Replay Jouni Högander
2024-06-18 5:30 ` [PATCH 8/9] Revert "drm/i915/psr: Disable early transport by default" Jouni Högander
2024-06-18 5:30 ` [PATCH 9/9] intel_alpm: Fix wrong offset for PORT_ALPM_* registers Jouni Högander
2024-06-18 11:58 ` Manna, Animesh
2024-06-18 6:06 ` ✗ Fi.CI.CHECKPATCH: warning for Panel Replay eDP more prepare patches Patchwork
2024-06-18 6:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-18 6:14 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-18 10:26 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-06-19 5:16 ` Hogander, Jouni
2024-06-19 5:24 ` [PATCH 0/9] " Hogander, Jouni
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