From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: animesh.manna@intel.com, mika.kahola@intel.com,
"Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH 5/9] drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set
Date: Tue, 18 Jun 2024 08:30:22 +0300 [thread overview]
Message-ID: <20240618053026.3268759-6-jouni.hogander@intel.com> (raw)
In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com>
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake
if panel supports it despite enable_psr module parameter value. This patch
makes it possible for user to limit used PSR mode and prevent SU Region
Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU
Region Early Transport is allowed.
v2: fix/improve commit desciption
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cfce0fe05d92..800cfeabc139 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp)
}
}
+static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (i915->display.params.enable_psr != -1)
+ return false;
+
+ return true;
+}
+
static bool panel_replay_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -683,7 +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
return panel_replay ?
intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
- intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
+ intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
+ psr2_su_region_et_global_enabled(intel_dp);
}
static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
--
2.34.1
next prev parent reply other threads:[~2024-06-18 5:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 5:30 [PATCH 0/9] Panel Replay eDP more prepare patches Jouni Högander
2024-06-18 5:30 ` [PATCH 1/9] drm/i915/psr: Set SU area width as pipe src width Jouni Högander
2024-06-18 10:23 ` Kahola, Mika
2024-06-18 5:30 ` [PATCH 2/9] drm/i915/display: Wa 16021440873 is writing wrong register Jouni Högander
2024-06-18 13:29 ` Kahola, Mika
2024-06-19 9:51 ` Jani Nikula
2024-06-19 12:11 ` Hogander, Jouni
2024-06-18 5:30 ` [PATCH 3/9] drm/i915/alpm: Fix port clock usage in AUX Less wake time calculation Jouni Högander
2024-06-18 5:30 ` [PATCH 4/9] drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter Jouni Högander
2024-06-18 12:00 ` Manna, Animesh
2024-06-18 5:30 ` Jouni Högander [this message]
2024-06-18 12:03 ` [PATCH 5/9] drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set Manna, Animesh
2024-06-18 5:30 ` [PATCH 6/9] drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only Jouni Högander
2024-06-18 5:30 ` [PATCH 7/9] drm/i915/psr: Add new debug bit to disable Panel Replay Jouni Högander
2024-06-18 5:30 ` [PATCH 8/9] Revert "drm/i915/psr: Disable early transport by default" Jouni Högander
2024-06-18 5:30 ` [PATCH 9/9] intel_alpm: Fix wrong offset for PORT_ALPM_* registers Jouni Högander
2024-06-18 11:58 ` Manna, Animesh
2024-06-18 6:06 ` ✗ Fi.CI.CHECKPATCH: warning for Panel Replay eDP more prepare patches Patchwork
2024-06-18 6:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-18 6:14 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-18 10:26 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-06-19 5:16 ` Hogander, Jouni
2024-06-19 5:24 ` [PATCH 0/9] " Hogander, Jouni
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