From: Raag Jadav <raag.jadav@intel.com>
To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com,
rodrigo.vivi@intel.com, matthew.d.roper@intel.com,
andi.shyti@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com,
badal.nilawar@intel.com, riana.tauro@intel.com,
Raag Jadav <raag.jadav@intel.com>
Subject: [PATCH v2 2/4] drm/i915/dg2: Introduce DG2_WA subplatform
Date: Fri, 11 Oct 2024 16:02:48 +0530 [thread overview]
Message-ID: <20241011103250.1035316-3-raag.jadav@intel.com> (raw)
In-Reply-To: <20241011103250.1035316-1-raag.jadav@intel.com>
Introduce DG2_WA subplatform for the devices that will be used in a
workaround and span across multiple DG2 subplatforms.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 34 +++++++++++++++++-------
drivers/gpu/drm/i915/intel_device_info.h | 5 +++-
3 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39f6614a0a99..0a68cd9379e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -548,6 +548,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+#define IS_DG2_WA(i915) \
+ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_WA)
#define IS_RAPTORLAKE_S(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_ALDERLAKE_P_N(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3c47c625993e..674ab2a4d75e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -200,6 +200,15 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(ID),
};
+static const u16 subplatform_dg2_wa_ids[] = {
+ INTEL_DG2_WA_IDS(ID),
+};
+
+static const u16 subplatform_dg2_ids[] = {
+ INTEL_DG2_IDS(ID),
+ INTEL_ATS_M_IDS(ID),
+};
+
static const u16 subplatform_arl_ids[] = {
INTEL_ARL_IDS(ID),
};
@@ -252,15 +261,22 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
if (find_devid(devid, subplatform_rplu_ids,
ARRAY_SIZE(subplatform_rplu_ids)))
mask |= BIT(INTEL_SUBPLATFORM_RPLU);
- } else if (find_devid(devid, subplatform_g10_ids,
- ARRAY_SIZE(subplatform_g10_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_G10);
- } else if (find_devid(devid, subplatform_g11_ids,
- ARRAY_SIZE(subplatform_g11_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_G11);
- } else if (find_devid(devid, subplatform_g12_ids,
- ARRAY_SIZE(subplatform_g12_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_G12);
+ } else if (find_devid(devid, subplatform_dg2_ids,
+ ARRAY_SIZE(subplatform_dg2_ids))) {
+ if (find_devid(devid, subplatform_g10_ids,
+ ARRAY_SIZE(subplatform_g10_ids)))
+ mask = BIT(INTEL_SUBPLATFORM_G10);
+ else if (find_devid(devid, subplatform_g11_ids,
+ ARRAY_SIZE(subplatform_g11_ids)))
+ mask = BIT(INTEL_SUBPLATFORM_G11);
+ else if (find_devid(devid, subplatform_g12_ids,
+ ARRAY_SIZE(subplatform_g12_ids)))
+ mask = BIT(INTEL_SUBPLATFORM_G12);
+
+ /* DG2 WA ids span across multiple subplatforms */
+ if (find_devid(devid, subplatform_dg2_wa_ids,
+ ARRAY_SIZE(subplatform_dg2_wa_ids)))
+ mask |= BIT(INTEL_SUBPLATFORM_WA);
} else if (find_devid(devid, subplatform_arl_ids,
ARRAY_SIZE(subplatform_arl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_ARL);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 643ff1bf74ee..c3623e859c78 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -95,9 +95,11 @@ enum intel_platform {
/*
* Subplatform bits share the same namespace per parent platform. In other words
* it is fine for the same bit to be used on multiple parent platforms.
+ * Devices can belong to multiple subplatforms if needed, so it's possible to set
+ * multiple bits for same device.
*/
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (4)
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
/* HSW/BDW/SKL/KBL/CFL */
@@ -114,6 +116,7 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_G10 0
#define INTEL_SUBPLATFORM_G11 1
#define INTEL_SUBPLATFORM_G12 2
+#define INTEL_SUBPLATFORM_WA 3
/* ADL */
#define INTEL_SUBPLATFORM_RPL 0
--
2.34.1
next prev parent reply other threads:[~2024-10-11 10:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-11 10:32 [PATCH v2 0/4] Implement Wa_14022698537 Raag Jadav
2024-10-11 10:32 ` [PATCH v2 1/4] drm/i915/pciids: Refactor DG2 PCI IDs into workaround ranges Raag Jadav
2024-10-11 10:40 ` Jani Nikula
2024-10-11 10:32 ` Raag Jadav [this message]
2024-10-11 10:44 ` [PATCH v2 2/4] drm/i915/dg2: Introduce DG2_WA subplatform Jani Nikula
2024-10-15 9:54 ` Raag Jadav
2024-10-11 10:32 ` [PATCH v2 3/4] drm/i915/wa: Introduce intel_wa_cpu.c for CPU specific workarounds Raag Jadav
2024-10-11 10:52 ` Jani Nikula
2024-10-15 10:26 ` Riana Tauro
2024-10-16 9:01 ` Raag Jadav
2024-10-22 9:53 ` Riana Tauro
2024-10-11 10:32 ` [PATCH v2 4/4] drm/i915/dg2: Implement Wa_14022698537 Raag Jadav
2024-10-15 10:02 ` Riana Tauro
2024-10-22 13:11 ` Nilawar, Badal
2024-10-23 7:09 ` Raag Jadav
2024-10-23 8:25 ` Gupta, Anshuman
2024-10-11 10:54 ` [PATCH v2 0/4] " Jani Nikula
2024-10-11 11:35 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-10-11 11:35 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-11 11:39 ` ✗ Fi.CI.BAT: failure " Patchwork
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