From: Raag Jadav <raag.jadav@intel.com>
To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com,
rodrigo.vivi@intel.com, matthew.d.roper@intel.com,
andi.shyti@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com,
badal.nilawar@intel.com, riana.tauro@intel.com,
Raag Jadav <raag.jadav@intel.com>
Subject: [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges
Date: Wed, 30 Oct 2024 20:04:15 +0530 [thread overview]
Message-ID: <20241030143418.410406-2-raag.jadav@intel.com> (raw)
In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com>
Refactor DG2 PCI IDs into D, E and M ranges which will be useful for
segment specific features.
v3: Rework subplatform naming (Jani)
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
include/drm/intel/pciids.h | 55 +++++++++++++++++++++++++++++---------
1 file changed, 42 insertions(+), 13 deletions(-)
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 7632507af166..83aac9f17372 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -717,37 +717,66 @@
MACRO__(0xA7AB, ## __VA_ARGS__)
/* DG2 */
-#define INTEL_DG2_G10_IDS(MACRO__, ...) \
- MACRO__(0x5690, ## __VA_ARGS__), \
- MACRO__(0x5691, ## __VA_ARGS__), \
- MACRO__(0x5692, ## __VA_ARGS__), \
+#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
MACRO__(0x56A0, ## __VA_ARGS__), \
MACRO__(0x56A1, ## __VA_ARGS__), \
- MACRO__(0x56A2, ## __VA_ARGS__), \
+ MACRO__(0x56A2, ## __VA_ARGS__)
+
+#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
MACRO__(0x56BE, ## __VA_ARGS__), \
MACRO__(0x56BF, ## __VA_ARGS__)
-#define INTEL_DG2_G11_IDS(MACRO__, ...) \
- MACRO__(0x5693, ## __VA_ARGS__), \
- MACRO__(0x5694, ## __VA_ARGS__), \
- MACRO__(0x5695, ## __VA_ARGS__), \
+#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
+ MACRO__(0x5690, ## __VA_ARGS__), \
+ MACRO__(0x5691, ## __VA_ARGS__), \
+ MACRO__(0x5692, ## __VA_ARGS__)
+
+#define INTEL_DG2_G10_IDS(MACRO__, ...) \
+ INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
+
+#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
MACRO__(0x56A5, ## __VA_ARGS__), \
MACRO__(0x56A6, ## __VA_ARGS__), \
MACRO__(0x56B0, ## __VA_ARGS__), \
- MACRO__(0x56B1, ## __VA_ARGS__), \
+ MACRO__(0x56B1, ## __VA_ARGS__)
+
+#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
MACRO__(0x56BA, ## __VA_ARGS__), \
MACRO__(0x56BB, ## __VA_ARGS__), \
MACRO__(0x56BC, ## __VA_ARGS__), \
MACRO__(0x56BD, ## __VA_ARGS__)
-#define INTEL_DG2_G12_IDS(MACRO__, ...) \
- MACRO__(0x5696, ## __VA_ARGS__), \
- MACRO__(0x5697, ## __VA_ARGS__), \
+#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
+ MACRO__(0x5693, ## __VA_ARGS__), \
+ MACRO__(0x5694, ## __VA_ARGS__), \
+ MACRO__(0x5695, ## __VA_ARGS__)
+
+#define INTEL_DG2_G11_IDS(MACRO__, ...) \
+ INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
+
+#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
MACRO__(0x56A3, ## __VA_ARGS__), \
MACRO__(0x56A4, ## __VA_ARGS__), \
MACRO__(0x56B2, ## __VA_ARGS__), \
MACRO__(0x56B3, ## __VA_ARGS__)
+#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
+ MACRO__(0x5696, ## __VA_ARGS__), \
+ MACRO__(0x5697, ## __VA_ARGS__)
+
+#define INTEL_DG2_G12_IDS(MACRO__, ...) \
+ INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
+
+#define INTEL_DG2_D_IDS(MACRO__, ...) \
+ INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
+
#define INTEL_DG2_IDS(MACRO__, ...) \
INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
--
2.34.1
next prev parent reply other threads:[~2024-10-30 14:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-30 14:34 [PATCH v3 0/4] Implement Wa_14022698537 Raag Jadav
2024-10-30 14:34 ` Raag Jadav [this message]
2024-11-20 7:21 ` [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges Riana Tauro
2024-12-10 11:45 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 2/4] drm/i915/dg2: Introduce DG2_D subplatform Raag Jadav
2024-10-30 14:34 ` [PATCH v3 3/4] drm/i915: Introduce intel_cpu_info.c for CPU IDs Raag Jadav
2024-12-10 7:38 ` Riana Tauro
2024-12-10 12:03 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537 Raag Jadav
2024-10-30 15:34 ` Andi Shyti
2024-10-30 16:35 ` Raag Jadav
2024-10-30 18:39 ` Jani Nikula
2024-10-31 8:51 ` Raag Jadav
2024-10-31 9:27 ` Jani Nikula
2024-10-31 11:02 ` Raag Jadav
2024-12-10 8:03 ` Riana Tauro
2024-12-10 11:33 ` Raag Jadav
2024-12-10 12:52 ` Andi Shyti
2024-12-11 5:21 ` Raag Jadav
2024-12-11 9:04 ` Andi Shyti
2024-10-30 15:03 ` ✗ Fi.CI.CHECKPATCH: warning for Implement Wa_14022698537 (rev2) Patchwork
2024-10-30 15:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-30 16:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-30 18:40 ` [PATCH v3 0/4] Implement Wa_14022698537 Jani Nikula
2024-10-31 8:59 ` Raag Jadav
2024-11-04 16:08 ` Jani Nikula
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