From: Raag Jadav <raag.jadav@intel.com>
To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com,
rodrigo.vivi@intel.com, matthew.d.roper@intel.com,
andi.shyti@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com,
badal.nilawar@intel.com, riana.tauro@intel.com,
Raag Jadav <raag.jadav@intel.com>
Subject: [PATCH v3 2/4] drm/i915/dg2: Introduce DG2_D subplatform
Date: Wed, 30 Oct 2024 20:04:16 +0530 [thread overview]
Message-ID: <20241030143418.410406-3-raag.jadav@intel.com> (raw)
In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com>
Introduce DG2_D subplatform for the devices that span across multiple
DG2 subplatforms but are within same segment and will be useful for
segment specific features.
v3: Rework subplatform naming (Jani)
Split subplatform check into separate case (Jani)
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 9 +++++++++
drivers/gpu/drm/i915/intel_device_info.h | 5 ++++-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f19cbd36829..fdb7158c7c1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -546,6 +546,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+#define IS_DG2_D(i915) \
+ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D)
#define IS_RAPTORLAKE_S(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_ALDERLAKE_P_N(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ff9500194d15..89d1549a83ae 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -200,6 +200,10 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(ID),
};
+static const u16 subplatform_dg2_d_ids[] = {
+ INTEL_DG2_D_IDS(ID),
+};
+
static const u16 subplatform_arl_ids[] = {
INTEL_ARL_IDS(ID),
};
@@ -266,6 +270,11 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
mask = BIT(INTEL_SUBPLATFORM_ARL);
}
+ /* DG2_D ids span across multiple DG2 subplatforms */
+ if (find_devid(devid, subplatform_dg2_d_ids,
+ ARRAY_SIZE(subplatform_dg2_d_ids)))
+ mask |= BIT(INTEL_SUBPLATFORM_D);
+
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4f4aa4ff9963..7f1f84b1d0e3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -95,9 +95,11 @@ enum intel_platform {
/*
* Subplatform bits share the same namespace per parent platform. In other words
* it is fine for the same bit to be used on multiple parent platforms.
+ * Devices can belong to multiple subplatforms if needed, so it's possible to set
+ * multiple bits for same device.
*/
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (4)
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
/* HSW/BDW/SKL/KBL/CFL */
@@ -114,6 +116,7 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_G10 0
#define INTEL_SUBPLATFORM_G11 1
#define INTEL_SUBPLATFORM_G12 2
+#define INTEL_SUBPLATFORM_D 3
/* ADL */
#define INTEL_SUBPLATFORM_RPL 0
--
2.34.1
next prev parent reply other threads:[~2024-10-30 14:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-30 14:34 [PATCH v3 0/4] Implement Wa_14022698537 Raag Jadav
2024-10-30 14:34 ` [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges Raag Jadav
2024-11-20 7:21 ` Riana Tauro
2024-12-10 11:45 ` Andi Shyti
2024-10-30 14:34 ` Raag Jadav [this message]
2024-10-30 14:34 ` [PATCH v3 3/4] drm/i915: Introduce intel_cpu_info.c for CPU IDs Raag Jadav
2024-12-10 7:38 ` Riana Tauro
2024-12-10 12:03 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537 Raag Jadav
2024-10-30 15:34 ` Andi Shyti
2024-10-30 16:35 ` Raag Jadav
2024-10-30 18:39 ` Jani Nikula
2024-10-31 8:51 ` Raag Jadav
2024-10-31 9:27 ` Jani Nikula
2024-10-31 11:02 ` Raag Jadav
2024-12-10 8:03 ` Riana Tauro
2024-12-10 11:33 ` Raag Jadav
2024-12-10 12:52 ` Andi Shyti
2024-12-11 5:21 ` Raag Jadav
2024-12-11 9:04 ` Andi Shyti
2024-10-30 15:03 ` ✗ Fi.CI.CHECKPATCH: warning for Implement Wa_14022698537 (rev2) Patchwork
2024-10-30 15:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-30 16:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-30 18:40 ` [PATCH v3 0/4] Implement Wa_14022698537 Jani Nikula
2024-10-31 8:59 ` Raag Jadav
2024-11-04 16:08 ` Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241030143418.410406-3-raag.jadav@intel.com \
--to=raag.jadav@intel.com \
--cc=andi.shyti@linux.intel.com \
--cc=anshuman.gupta@intel.com \
--cc=badal.nilawar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=joonas.lahtinen@linux.intel.com \
--cc=matthew.d.roper@intel.com \
--cc=riana.tauro@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox