From: Raag Jadav <raag.jadav@intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>
Cc: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com,
rodrigo.vivi@intel.com, matthew.d.roper@intel.com,
intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com,
badal.nilawar@intel.com, riana.tauro@intel.com
Subject: Re: [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537
Date: Wed, 11 Dec 2024 07:21:54 +0200 [thread overview]
Message-ID: <Z1khch4UxdICMGxT@black.fi.intel.com> (raw)
In-Reply-To: <Z1g5heTT1rwTcdt9@ashyti-mobl2.lan>
On Tue, Dec 10, 2024 at 01:52:21PM +0100, Andi Shyti wrote:
> Hi Raag,
>
> > +/* Wa_14022698537:dg2 */
> > +static void i915_enable_g8(struct drm_i915_private *i915)
> > +{
> > + if (IS_DG2(i915)) {
> > + if (IS_DG2_D(i915) && !intel_match_g8_cpu())
> > + return;
> > +
> > + snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
> > + POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);
> > + }
>
> In the workaround description there an "else if" which I am not
> understanding. I it suggesting to do nothing or is it suggesting
> to do the same thing?
We do the same thing (apply WA) except when the _D IDs are not paired
with whitelisted CPUs. What I did here is added a return call with
inverted CPU logic and got rid of the else part. I know it looks quirky
but does the job.
> > +}
> > +
> > static int i915_pcode_init(struct drm_i915_private *i915)
> > {
> > struct intel_gt *gt;
> > @@ -428,6 +442,7 @@ static int i915_pcode_init(struct drm_i915_private *i915)
> > }
> > }
> >
> > + i915_enable_g8(i915);
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 89e4381f8baa..d400c77423a5 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3617,6 +3617,7 @@
> > #define POWER_SETUP_I1_WATTS REG_BIT(31)
> > #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
> > #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
> > +#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
>
> for aesthetics 0x06 would look better, but this should be
> changed everywhere in the file because single digit hex values
> are used. It's better to keep uniformity in the style.
I agree about uniformity but perhaps a separate filewide patch would
be much cleaner IMHO. Let's keep it as it is for now.
> > #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
> > /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> > --
> > 2.34.1
next prev parent reply other threads:[~2024-12-11 5:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-30 14:34 [PATCH v3 0/4] Implement Wa_14022698537 Raag Jadav
2024-10-30 14:34 ` [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges Raag Jadav
2024-11-20 7:21 ` Riana Tauro
2024-12-10 11:45 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 2/4] drm/i915/dg2: Introduce DG2_D subplatform Raag Jadav
2024-10-30 14:34 ` [PATCH v3 3/4] drm/i915: Introduce intel_cpu_info.c for CPU IDs Raag Jadav
2024-12-10 7:38 ` Riana Tauro
2024-12-10 12:03 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537 Raag Jadav
2024-10-30 15:34 ` Andi Shyti
2024-10-30 16:35 ` Raag Jadav
2024-10-30 18:39 ` Jani Nikula
2024-10-31 8:51 ` Raag Jadav
2024-10-31 9:27 ` Jani Nikula
2024-10-31 11:02 ` Raag Jadav
2024-12-10 8:03 ` Riana Tauro
2024-12-10 11:33 ` Raag Jadav
2024-12-10 12:52 ` Andi Shyti
2024-12-11 5:21 ` Raag Jadav [this message]
2024-12-11 9:04 ` Andi Shyti
2024-10-30 15:03 ` ✗ Fi.CI.CHECKPATCH: warning for Implement Wa_14022698537 (rev2) Patchwork
2024-10-30 15:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-30 16:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-30 18:40 ` [PATCH v3 0/4] Implement Wa_14022698537 Jani Nikula
2024-10-31 8:59 ` Raag Jadav
2024-11-04 16:08 ` Jani Nikula
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