From: Jani Nikula <jani.nikula@linux.intel.com>
To: Raag Jadav <raag.jadav@intel.com>,
joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com,
matthew.d.roper@intel.com, andi.shyti@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com,
badal.nilawar@intel.com, riana.tauro@intel.com,
Raag Jadav <raag.jadav@intel.com>
Subject: Re: [PATCH v3 0/4] Implement Wa_14022698537
Date: Wed, 30 Oct 2024 20:40:50 +0200 [thread overview]
Message-ID: <874j4tl9hp.fsf@intel.com> (raw)
In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com>
On Wed, 30 Oct 2024, Raag Jadav <raag.jadav@intel.com> wrote:
> This series implements Wa_14022698537 for DG2 along with its prerequisites
> in i915. Now that we have a common pciids.h in place, this can be extended
> to xe as well. Detailed description in commit message.
Okay, so this bumps the requirements during development, but where's the
implementation for xe? What's it going to look like?
BR,
Jani.
>
> v1: https://patchwork.freedesktop.org/series/139628/
>
> v2: Introduce DG2_WA subplatform for workaround (Jani)
> Fix Wa_ID and include it in subject (Badal)
> Rephrase commit message (Jani)
> Move CPU whitelist to intel_wa_cpu.c
>
> v3: Rework subplatform naming (Jani)
> Move CPU file out of gt directory (Riana)
> Rephrase CPU file description (Jani)
> Add kernel doc, re-order macro (Riana)
> Move workaround to i915_pcode_init() (Badal, Anshuman)
>
> Raag Jadav (4):
> drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges
> drm/i915/dg2: Introduce DG2_D subplatform
> drm/i915: Introduce intel_cpu_info.c for CPU IDs
> drm/i915/dg2: Implement Wa_14022698537
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_driver.c | 15 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_cpu_info.c | 42 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_cpu_info.h | 13 ++++++
> drivers/gpu/drm/i915/intel_device_info.c | 9 ++++
> drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
> include/drm/intel/pciids.h | 55 ++++++++++++++++++------
> 9 files changed, 129 insertions(+), 14 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_cpu_info.c
> create mode 100644 drivers/gpu/drm/i915/intel_cpu_info.h
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-10-30 18:40 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-30 14:34 [PATCH v3 0/4] Implement Wa_14022698537 Raag Jadav
2024-10-30 14:34 ` [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges Raag Jadav
2024-11-20 7:21 ` Riana Tauro
2024-12-10 11:45 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 2/4] drm/i915/dg2: Introduce DG2_D subplatform Raag Jadav
2024-10-30 14:34 ` [PATCH v3 3/4] drm/i915: Introduce intel_cpu_info.c for CPU IDs Raag Jadav
2024-12-10 7:38 ` Riana Tauro
2024-12-10 12:03 ` Andi Shyti
2024-10-30 14:34 ` [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537 Raag Jadav
2024-10-30 15:34 ` Andi Shyti
2024-10-30 16:35 ` Raag Jadav
2024-10-30 18:39 ` Jani Nikula
2024-10-31 8:51 ` Raag Jadav
2024-10-31 9:27 ` Jani Nikula
2024-10-31 11:02 ` Raag Jadav
2024-12-10 8:03 ` Riana Tauro
2024-12-10 11:33 ` Raag Jadav
2024-12-10 12:52 ` Andi Shyti
2024-12-11 5:21 ` Raag Jadav
2024-12-11 9:04 ` Andi Shyti
2024-10-30 15:03 ` ✗ Fi.CI.CHECKPATCH: warning for Implement Wa_14022698537 (rev2) Patchwork
2024-10-30 15:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-30 16:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-30 18:40 ` Jani Nikula [this message]
2024-10-31 8:59 ` [PATCH v3 0/4] Implement Wa_14022698537 Raag Jadav
2024-11-04 16:08 ` Jani Nikula
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