[PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB

[Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (10):
  drm/i915/display: Add source param for dc balance
  drm/i915/display: Add VRR DC balance registers
  drm/i915/vrr: Add DC Balance params to crtc_state
  drm/i915/vrr: Add state dump for DC Balance params
  drm/i915/vrr: Add compute config for DC Balance params
  drm/i915/vrr: Write DC balance params to hw registers
  drm/i915/vrr: Add function to check if DC Balance Possible
  drm/i915/display: Add function to configure PIPEDMC_EVT_CTL
  drm/i915/vrr: Enable Adaptive sync counter bit
  drm/i915/vrr: Enable DC Balance

Ville Syrjälä (8):
  drm/i915/vrr: Refactor vmin/vmax stuff
  drm/i915/display: Add pipe dmc registers and bits for DC Balance
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Restructure VRR enablement bit
  drm/i915/vrr: Pause DC Balancing for DSB commits

 .../drm/i915/display/intel_crtc_state_dump.c  |   8 +
 drivers/gpu/drm/i915/display/intel_display.c  |  26 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  35 +++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   7 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  51 ++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 ++-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 240 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  45 ++++
 12 files changed, 449 insertions(+), 40 deletions(-)

-- 
2.48.1