From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, ankit.k.nautiyal@intel.com,
jani.nikula@linux.intel.com
Subject: [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing
Date: Tue, 24 Jun 2025 13:19:41 +0530 [thread overview]
Message-ID: <20250624074948.671761-12-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20250624074948.671761-1-mitulkumar.ajitkumar.golani@intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 53d8ae3a70e9..ec624dc1987e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -721,7 +721,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+ int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+ int vmin_vblank_start, vmax_vblank_start;
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+ if (vmin_vblank_start >= 0) {
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vmax_vblank_start >= 0) {
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ } else if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = intel_vrr_vblank_delay(crtc_state);
end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index d544e274bcfa..685768124852 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
{
- if (intel_vrr_is_push_sent(crtc_state))
- return intel_vrr_vmin_vblank_start(crtc_state);
+ bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+ int vblank_start;
+
+ if (!crtc_state->vrr.dc_balance.enable) {
+ if (is_push_sent)
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+ }
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
else
- return intel_vrr_vmax_vblank_start(crtc_state);
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vblank_start >= 0)
+ return vblank_start;
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ else
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+ return vblank_start;
}
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
--
2.48.1
next prev parent reply other threads:[~2025-06-24 7:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-06-24 7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-06-24 7:49 ` [PATCH v7 02/18] drm/i915/display: Add source param for dc balance Mitul Golani
2025-06-24 7:49 ` [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-06-24 7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
2025-06-24 8:13 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-06-24 7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-06-24 8:14 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-06-24 7:49 ` [PATCH v7 08/18] drm/i915/vrr: Add compute config " Mitul Golani
2025-06-24 7:49 ` [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-06-24 7:49 ` [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-06-24 7:49 ` Mitul Golani [this message]
2025-06-24 7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-06-24 8:25 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-06-24 7:49 ` [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-06-24 7:49 ` [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-06-24 7:49 ` [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
2025-06-24 7:49 ` [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-06-24 7:49 ` [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-06-24 8:54 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
2025-06-24 12:40 ` ✗ i915.CI.Full: failure " Patchwork
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