From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: mitulkumar.ajitkumar.golani@intel.com,
ankit.k.nautiyal@intel.com, ville.syrjala@linux.intel.com
Subject: [PATCH v1 1/8] drm/i915/display: Move CMRR crtc state into vrr state
Date: Tue, 19 May 2026 10:33:15 +0530 [thread overview]
Message-ID: <20260519050322.3677451-2-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20260519050322.3677451-1-mitulkumar.ajitkumar.golani@intel.com>
CMRR is part of the VRR fixed refresh rate case. Instead of a separate
top-level state entry, nest it within the vrr crtc state parameters.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++----
.../drm/i915/display/intel_display_types.h | 10 +++----
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 30 +++++++++----------
4 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5cf1476c7b9..1cdc6d8b9e5d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -927,8 +927,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
- old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+ return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
+ old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
}
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@@ -5459,9 +5459,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
- PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
- PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
- PIPE_CONF_CHECK_BOOL(cmrr.enable);
+ PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 26e59110e743..ce280349622b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1397,14 +1397,12 @@ struct intel_crtc_state {
u16 max_increase, max_decrease;
u16 vblank_target;
} dc_balance;
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
} vrr;
- /* Content Match Refresh Rate state */
- struct {
- bool enable;
- u64 cmrr_n, cmrr_m;
- } cmrr;
-
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2151766546e6..7c288e2e7593 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3206,7 +3206,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
as_sdp->duration_incr_ms = 0;
as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
- if (crtc_state->cmrr.enable) {
+ if (crtc_state->vrr.cmrr.enable) {
as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
as_sdp->target_rr_divider = true;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1b09992ce9fd..a5bd87c2912a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -220,12 +220,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
multiplier_n = 1000;
}
- crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
- multiplier_n);
+ crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
+ multiplier_n);
vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
- crtc_state->cmrr.cmrr_n);
+ crtc_state->vrr.cmrr.cmrr_n);
adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
- crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+ crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
return vtotal;
}
@@ -243,7 +243,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmin = crtc_state->vrr.vmax;
crtc_state->vrr.flipline = crtc_state->vrr.vmin;
- crtc_state->cmrr.enable = true;
+ crtc_state->vrr.cmrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
@@ -636,15 +636,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
- if (crtc_state->cmrr.enable) {
+ if (crtc_state->vrr.cmrr.enable) {
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
- upper_32_bits(crtc_state->cmrr.cmrr_m));
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
- lower_32_bits(crtc_state->cmrr.cmrr_m));
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
- upper_32_bits(crtc_state->cmrr.cmrr_n));
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
- lower_32_bits(crtc_state->cmrr.cmrr_n));
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
}
intel_vrr_set_fixed_rr_timings(crtc_state);
@@ -962,7 +962,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
- intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
+ intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1059,12 +1059,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_VRR_CTL(display, cpu_transcoder));
if (HAS_CMRR(display))
- crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+ crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
- if (crtc_state->cmrr.enable) {
- crtc_state->cmrr.cmrr_n =
+ if (crtc_state->vrr.cmrr.enable) {
+ crtc_state->vrr.cmrr.cmrr_n =
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
- crtc_state->cmrr.cmrr_m =
+ crtc_state->vrr.cmrr.cmrr_m =
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
}
--
2.48.1
next prev parent reply other threads:[~2026-05-19 5:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 5:03 [PATCH v1 0/8] Enable CMRR in fixed-RR VRR path Mitul Golani
2026-05-19 5:03 ` Mitul Golani [this message]
2026-05-19 5:03 ` [PATCH v1 2/8] drm/i915/vrr: Move CMRR register writes to fix refresh rate path Mitul Golani
2026-05-19 5:03 ` [PATCH v1 3/8] drm/i915/display: Introduce CMRR fraction level to vrr crtc state Mitul Golani
2026-06-02 13:10 ` Borah, Chaitanya Kumar
2026-05-19 5:03 ` [PATCH v1 4/8] drm/i915/display: Add state dump for CMRR params Mitul Golani
2026-05-19 5:03 ` [PATCH v1 5/8] i915/display/vrr: Compute CMRR params along with fixed refresh rate params Mitul Golani
2026-05-19 5:03 ` [PATCH v1 6/8] drm/i915/display: Add per-CRTC debugfs interface for CMRR fraction level Mitul Golani
2026-06-02 13:11 ` Borah, Chaitanya Kumar
2026-05-19 5:03 ` [PATCH v1 7/8] drm/i915/vrr: Compute CMRR vtotal based on configured scaling level Mitul Golani
2026-05-19 5:03 ` [PATCH v1 8/8] i915/display/vrr: Enable CMRR Mitul Golani
2026-06-02 13:16 ` Borah, Chaitanya Kumar
2026-05-19 6:25 ` ✓ i915.CI.BAT: success for Enable CMRR in fixed-RR VRR path Patchwork
2026-05-20 0:06 ` ✗ i915.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260519050322.3677451-2-mitulkumar.ajitkumar.golani@intel.com \
--to=mitulkumar.ajitkumar.golani@intel.com \
--cc=ankit.k.nautiyal@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox