[PATCH v1 2/8] drm/i915/vrr: Move CMRR register writes to fix refresh rate path

[Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>]

Write CMRR related M/N registers to fix rate path for its better
alignment as fix refresh rate use-case.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index a5bd87c2912a..87d52b206bdb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -328,6 +328,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	if (crtc_state->vrr.cmrr.enable) {
+		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	}
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
@@ -636,17 +647,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->vrr.cmrr.enable) {
-		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-	}
-
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-- 
2.48.1