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From: "Murthy, Arun R" <arun.r.murthy@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
	<intel-xe@lists.freedesktop.org>,
	 <intel-gfx@lists.freedesktop.org>
Cc: <ankit.k.nautiyal@intel.com>, <uma.shankar@intel.com>,
	<gustavo.sousa@intel.com>, <lucas.demarchi@intel.com>
Subject: Re: [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP
Date: Thu, 23 Oct 2025 13:12:17 +0530	[thread overview]
Message-ID: <27d0c847-df30-4409-a006-4e9c83755e27@intel.com> (raw)
In-Reply-To: <20251015040817.3431297-10-suraj.kandpal@intel.com>


On 15-10-2025 09:38, Suraj Kandpal wrote:
> When we get the eDP tables we reuse dp tables for some data rates.
> We need to modify the 3rd config value of this table to 1 instead
> of 0 since that is the only difference in the dp and edp table for
> that particular data rate.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 9380ba530901..8cd0009609d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1226,6 +1226,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   	for (i = 0; tables[i]; i++) {
>   		if (crtc_state->port_clock == tables[i]->clock) {
>   			crtc_state->dpll_hw_state.ltpll = *tables[i];
> +			if (intel_crtc_has_dp_encoder(crtc_state)) {
> +				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
> +			}
>   			return 0;
>   		}
>   	}

  reply	other threads:[~2025-10-23  7:42 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15  4:07 [PATCH 00/25] Enable LT PHY Suraj Kandpal
2025-10-15  4:07 ` [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-20 11:10   ` Jani Nikula
2025-10-22  4:05     ` Kandpal, Suraj
2025-10-22  7:57   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-22  8:01   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-22  8:41   ` Murthy, Arun R
2025-10-22  9:01     ` Kandpal, Suraj
2025-10-15  4:07 ` [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL " Suraj Kandpal
2025-10-22  8:49   ` Murthy, Arun R
2025-10-22  8:58     ` Kandpal, Suraj
2025-10-22  9:06       ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-22  9:13   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-23  7:29   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-23  7:36   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-23  7:40   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-23  7:42   ` Murthy, Arun R [this message]
2025-10-15  4:08 ` [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-23  7:49   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-15  4:08 ` [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-23  8:18   ` Murthy, Arun R
2025-10-23  9:24     ` Kandpal, Suraj
2025-10-23  9:32       ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-23  8:27   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-23  8:32   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-23  8:40   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-23  8:43   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-23  9:33   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24  6:39   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24  7:00   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24  7:03   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24  7:14   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24  7:26   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-24  7:32   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped Suraj Kandpal
2025-10-24  7:33   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-15  4:59 ` ✓ i915.CI.BAT: success for Enable LT PHY Patchwork
2025-10-15 11:32 ` ✓ i915.CI.Full: " Patchwork

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