From: "Murthy, Arun R" <arun.r.murthy@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
<intel-xe@lists.freedesktop.org>,
<intel-gfx@lists.freedesktop.org>
Cc: <ankit.k.nautiyal@intel.com>, <uma.shankar@intel.com>,
<gustavo.sousa@intel.com>, <lucas.demarchi@intel.com>
Subject: Re: [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function
Date: Fri, 24 Oct 2025 12:33:50 +0530 [thread overview]
Message-ID: <58a20cb9-cb0c-4f05-a543-c804748a9177@intel.com> (raw)
In-Reply-To: <20251015040817.3431297-21-suraj.kandpal@intel.com>
On 15-10-2025 09:38, Suraj Kandpal wrote:
> Define function to compare the state and if mismatch is detected
> dump both the states.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 30 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_lt_phy.h | 6 ++++
> 3 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5b2612d4ec2..b05f70582788 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
> #include "intel_hdmi.h"
> #include "intel_hotplug.h"
> #include "intel_link_bw.h"
> +#include "intel_lt_phy.h"
> #include "intel_lvds.h"
> #include "intel_lvds_regs.h"
> #include "intel_modeset_setup.h"
> @@ -4963,6 +4964,24 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
> !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> }
>
> +static void
> +pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
> + const struct intel_crtc *crtc,
> + const char *name,
> + const struct intel_lt_phy_pll_state *a,
> + const struct intel_lt_phy_pll_state *b)
> +{
> + struct intel_display *display = to_intel_display(crtc);
> + char *chipname = "LTPHY";
> +
> + pipe_config_mismatch(p, fastset, crtc, name, chipname);
> +
> + drm_printf(p, "expected:\n");
> + intel_lt_phy_dump_hw_state(display, a);
> + drm_printf(p, "found:\n");
> + intel_lt_phy_dump_hw_state(display, b);
> +}
> +
> bool
> intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> @@ -5087,6 +5106,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_PLL_LT(name) do { \
> + if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \
> + &pipe_config->name)) { \
> + pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
> + ¤t_config->name, \
> + &pipe_config->name); \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_CHECK_TIMINGS(name) do { \
> PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
> PIPE_CONF_CHECK_I(name.crtc_htotal); \
> @@ -5311,7 +5340,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_PLL(dpll_hw_state);
>
> /* FIXME convert MTL+ platforms over to dpll_mgr */
> - if (DISPLAY_VER(display) >= 14)
> + if (HAS_LT_PHY(display))
> + PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> + else if (DISPLAY_VER(display) >= 14)
> PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
>
> PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index f1e41f009bb5..0be4aad0efcc 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1843,6 +1843,36 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> intel_lt_phy_transaction_end(encoder, wakeref);
> }
>
> +void intel_lt_phy_dump_hw_state(struct intel_display *display,
> + const struct intel_lt_phy_pll_state *hw_state)
> +{
> + int i, j;
> +
> + drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
> + for (i = 0; i < 3; i++) {
> + drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
> + i, hw_state->config[i]);
> + }
> +
> + for (i = 0; i <= 12; i++)
> + for (j = 3; j >= 0; j--)
> + drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
> + i, j, hw_state->data[i][j]);
> +}
> +
> +bool
> +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
> + const struct intel_lt_phy_pll_state *b)
> +{
> + if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0)
> + return false;
> +
> + if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0)
> + return false;
> +
> + return true;
> +}
> +
> void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 6e67ae78801c..e93e5becc316 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -8,6 +8,7 @@
>
> #include <linux/types.h>
>
> +struct intel_display;
> struct intel_encoder;
> struct intel_crtc_state;
> struct intel_lt_phy_pll_state;
> @@ -22,6 +23,11 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> +void intel_lt_phy_dump_hw_state(struct intel_display *display,
> + const struct intel_lt_phy_pll_state *hw_state);
> +bool
> +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
> + const struct intel_lt_phy_pll_state *b);
> void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
next prev parent reply other threads:[~2025-10-24 7:04 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 4:07 [PATCH 00/25] Enable LT PHY Suraj Kandpal
2025-10-15 4:07 ` [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-20 11:10 ` Jani Nikula
2025-10-22 4:05 ` Kandpal, Suraj
2025-10-22 7:57 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-22 8:01 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-22 8:41 ` Murthy, Arun R
2025-10-22 9:01 ` Kandpal, Suraj
2025-10-15 4:07 ` [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL " Suraj Kandpal
2025-10-22 8:49 ` Murthy, Arun R
2025-10-22 8:58 ` Kandpal, Suraj
2025-10-22 9:06 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-22 9:13 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-23 7:29 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-23 7:36 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-23 7:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-23 7:42 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-23 7:49 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-15 4:08 ` [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-23 8:18 ` Murthy, Arun R
2025-10-23 9:24 ` Kandpal, Suraj
2025-10-23 9:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-23 8:27 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-23 8:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-23 8:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-23 8:43 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-23 9:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24 6:39 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24 7:00 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24 7:03 ` Murthy, Arun R [this message]
2025-10-15 4:08 ` [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24 7:14 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24 7:26 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-24 7:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped Suraj Kandpal
2025-10-24 7:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-15 4:59 ` ✓ i915.CI.BAT: success for Enable LT PHY Patchwork
2025-10-15 11:32 ` ✓ i915.CI.Full: " Patchwork
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