Re: [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values

["Murthy, Arun R" <arun.r.murthy@intel.com>]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Change the register bit naming for powerdown values from CX0 to
> XELPDP so that it can be used with LT Phy too.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 14 +++++++-------
>   drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 10 +++++-----
>   2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a2d2cecf7121..6d9ebc8717ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2850,11 +2850,11 @@ static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
>   
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
>   		     XELPDP_POWER_STATE_READY_MASK,
> -		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> +		     XELPDP_POWER_STATE_READY(XELPDP_P2_STATE_READY));
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
>   		     XELPDP_POWER_STATE_ACTIVE_MASK |
>   		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> -		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> +		     XELPDP_POWER_STATE_ACTIVE(XELPDP_P0_STATE_ACTIVE) |
>   		     XELPDP_PLL_LANE_STAGGERING_DELAY(0));
>   }
>   
> @@ -2927,7 +2927,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
>   			 phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
>   
>   	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -					    CX0_P2_STATE_RESET);
> +					    XELPDP_P2_STATE_RESET);
>   	intel_cx0_setup_powerdown(encoder);
>   
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
> @@ -3032,7 +3032,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>   	 * TODO: For DP alt mode use only one lane.
>   	 */
>   	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -					    CX0_P2_STATE_READY);
> +					    XELPDP_P2_STATE_READY);
>   
>   	/*
>   	 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000.
> @@ -3273,13 +3273,13 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
>   	struct intel_display *display = to_intel_display(encoder);
>   
>   	if (intel_encoder_is_c10phy(encoder))
> -		return CX0_P2PG_STATE_DISABLE;
> +		return XELPDP_P2PG_STATE_DISABLE;
>   
>   	if ((display->platform.battlemage && encoder->port == PORT_A) ||
>   	    (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
> -		return CX0_P2PG_STATE_DISABLE;
> +		return XELPDP_P2PG_STATE_DISABLE;
>   
> -	return CX0_P4PG_STATE_DISABLE;
> +	return XELPDP_P4PG_STATE_DISABLE;
>   }
>   
>   static void intel_cx0pll_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 77eae1d845f7..18b91c23d547 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -149,11 +149,11 @@
>   #define   XELPDP_PLL_LANE_STAGGERING_DELAY(val)		REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
>   #define   XELPDP_POWER_STATE_ACTIVE_MASK		REG_GENMASK(3, 0)
>   #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
> -#define   CX0_P0_STATE_ACTIVE				0x0
> -#define   CX0_P2_STATE_READY				0x2
> -#define   CX0_P2PG_STATE_DISABLE			0x9
> -#define   CX0_P4PG_STATE_DISABLE			0xC
> -#define   CX0_P2_STATE_RESET				0x2
> +#define   XELPDP_P0_STATE_ACTIVE			0x0
> +#define   XELPDP_P2_STATE_READY				0x2
> +#define   XELPDP_P2PG_STATE_DISABLE			0x9
> +#define   XELPDP_P4PG_STATE_DISABLE			0xC
> +#define   XELPDP_P2_STATE_RESET				0x2
>   
>   #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A			0x640d8
>   #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B			0x641d8