From: "Murthy, Arun R" <arun.r.murthy@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
<intel-xe@lists.freedesktop.org>,
<intel-gfx@lists.freedesktop.org>
Cc: <ankit.k.nautiyal@intel.com>, <uma.shankar@intel.com>,
<gustavo.sousa@intel.com>, <lucas.demarchi@intel.com>
Subject: Re: [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
Date: Thu, 23 Oct 2025 14:13:24 +0530 [thread overview]
Message-ID: <0975e49f-c1df-48e3-8894-5fd01f4e8917@intel.com> (raw)
In-Reply-To: <20251015040817.3431297-17-suraj.kandpal@intel.com>
On 15-10-2025 09:38, Suraj Kandpal wrote:
> Hook up the LT Phy enable and disable sequences using encoder->
> enable/disable_clock and reusing the TBT enable disable sequence from
> cx0 PHY since it remains the same.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 ++++---
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 +++
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 21 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +++
> 5 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 914b215d8bd4..986da034d4de 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -18,6 +18,7 @@
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_hdmi.h"
> +#include "intel_lt_phy.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_snps_hdmi_pll.h"
> @@ -3155,8 +3156,8 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
> }
> }
>
> -static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -3340,7 +3341,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
> intel_cx0_get_pclk_pll_request(lane);
> }
>
> -static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index f0f0efa2d48b..a37827482a32 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -64,5 +64,8 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> void intel_cx0_pll_power_save_wa(struct intel_display *display);
> void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
>
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c09aa759f4d4..6fcfdd0b0103 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -72,6 +72,7 @@
> #include "intel_hotplug.h"
> #include "intel_hti.h"
> #include "intel_lspcon.h"
> +#include "intel_lt_phy.h"
> #include "intel_mg_phy_regs.h"
> #include "intel_modeset_lock.h"
> #include "intel_panel.h"
> @@ -5224,7 +5225,11 @@ void intel_ddi_init(struct intel_display *display,
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
>
> - if (DISPLAY_VER(display) >= 14) {
> + if (HAS_LT_PHY(display)) {
> + encoder->enable_clock = intel_xe3plpd_pll_enable;
> + encoder->disable_clock = intel_xe3plpd_pll_disable;
> + encoder->port_pll_type = intel_mtl_port_pll_type;
> + } else if (DISPLAY_VER(display) >= 14) {
> encoder->enable_clock = intel_mtl_pll_enable;
> encoder->disable_clock = intel_mtl_pll_disable;
> encoder->port_pll_type = intel_mtl_port_pll_type;
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 747cce4a484a..d458909b5f12 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1692,3 +1692,24 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
>
> intel_lt_phy_transaction_end(encoder, wakeref);
> }
> +
> +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + intel_mtl_tbt_pll_enable(encoder, crtc_state);
> + else
> + intel_lt_phy_pll_enable(encoder, crtc_state);
> +}
> +
> +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + intel_mtl_tbt_pll_disable(encoder);
> + else
> + intel_lt_phy_pll_disable(encoder);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 499091e04e82..15d3d680871c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -20,6 +20,9 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder);
> int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>
> #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
>
next prev parent reply other threads:[~2025-10-23 8:43 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 4:07 [PATCH 00/25] Enable LT PHY Suraj Kandpal
2025-10-15 4:07 ` [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-20 11:10 ` Jani Nikula
2025-10-22 4:05 ` Kandpal, Suraj
2025-10-22 7:57 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-22 8:01 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-22 8:41 ` Murthy, Arun R
2025-10-22 9:01 ` Kandpal, Suraj
2025-10-15 4:07 ` [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL " Suraj Kandpal
2025-10-22 8:49 ` Murthy, Arun R
2025-10-22 8:58 ` Kandpal, Suraj
2025-10-22 9:06 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-22 9:13 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-23 7:29 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-23 7:36 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-23 7:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-23 7:42 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-23 7:49 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-15 4:08 ` [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-23 8:18 ` Murthy, Arun R
2025-10-23 9:24 ` Kandpal, Suraj
2025-10-23 9:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-23 8:27 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-23 8:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-23 8:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-23 8:43 ` Murthy, Arun R [this message]
2025-10-15 4:08 ` [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-23 9:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24 6:39 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24 7:00 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24 7:03 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24 7:14 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24 7:26 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-24 7:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped Suraj Kandpal
2025-10-24 7:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-15 4:59 ` ✓ i915.CI.BAT: success for Enable LT PHY Patchwork
2025-10-15 11:32 ` ✓ i915.CI.Full: " Patchwork
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