* [PATCH 1/4] drm/i915: Support flags in whitlist WAs
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
@ 2019-06-14 0:28 ` Robert M. Fosha
2019-06-14 6:48 ` Tvrtko Ursulin
2019-06-14 0:28 ` [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines Robert M. Fosha
` (4 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Robert M. Fosha @ 2019-06-14 0:28 UTC (permalink / raw)
To: intel-gfx
From: John Harrison <John.C.Harrison@Intel.com>
Newer hardware adds flags to the whitelist work-around register. These
allow per access direction privileges and ranges.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 165b0a45e009..ae82340fff45 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1012,7 +1012,7 @@ bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
}
static void
-whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
+whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
{
struct i915_wa wa = {
.reg = reg
@@ -1021,9 +1021,16 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
return;
+ wa.reg.reg |= flags;
_wa_add(wal, &wa);
}
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
+{
+ whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
+}
+
static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index edf9f93934a1..10fea5ab3fc3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2513,6 +2513,13 @@ enum i915_power_well_id {
#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_RD (1 << 28)
+#define RING_FORCE_TO_NONPRIV_WR (2 << 28)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
#define RING_MAX_NONPRIV_SLOTS 12
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
--
2.21.0.5.gaeb582a983
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 1/4] drm/i915: Support flags in whitlist WAs
2019-06-14 0:28 ` [PATCH 1/4] drm/i915: Support flags in whitlist WAs Robert M. Fosha
@ 2019-06-14 6:48 ` Tvrtko Ursulin
2019-06-18 1:13 ` John Harrison
0 siblings, 1 reply; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 6:48 UTC (permalink / raw)
To: Robert M. Fosha, intel-gfx
On 14/06/2019 01:28, Robert M. Fosha wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Newer hardware adds flags to the whitelist work-around register. These
> allow per access direction privileges and ranges.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 165b0a45e009..ae82340fff45 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1012,7 +1012,7 @@ bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
> }
>
> static void
> -whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> +whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
> {
> struct i915_wa wa = {
> .reg = reg
> @@ -1021,9 +1021,16 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
> return;
>
> + wa.reg.reg |= flags;
> _wa_add(wal, &wa);
> }
>
> +static void
> +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> +{
> + whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
> +}
> +
> static void gen9_whitelist_build(struct i915_wa_list *w)
> {
> /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index edf9f93934a1..10fea5ab3fc3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2513,6 +2513,13 @@ enum i915_power_well_id {
> #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
>
> #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
> +#define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ & Gen11+ */
Shouldn't this comment be against the RD and WR flags, while the above
is the legacy one?
> +#define RING_FORCE_TO_NONPRIV_RD (1 << 28)
> +#define RING_FORCE_TO_NONPRIV_WR (2 << 28)
> +#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
> +#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
> #define RING_MAX_NONPRIV_SLOTS 12
>
> #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
>
Regards,
Tvrtko
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/4] drm/i915: Support flags in whitlist WAs
2019-06-14 6:48 ` Tvrtko Ursulin
@ 2019-06-18 1:13 ` John Harrison
2019-06-18 6:51 ` Tvrtko Ursulin
0 siblings, 1 reply; 19+ messages in thread
From: John Harrison @ 2019-06-18 1:13 UTC (permalink / raw)
To: intel-gfx
On 6/13/2019 23:48, Tvrtko Ursulin wrote:
>
> On 14/06/2019 01:28, Robert M. Fosha wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Newer hardware adds flags to the whitelist work-around register. These
>> allow per access direction privileges and ranges.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
>> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 165b0a45e009..ae82340fff45 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1012,7 +1012,7 @@ bool intel_gt_verify_workarounds(struct
>> drm_i915_private *i915,
>> }
>> static void
>> -whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
>> +whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
>> {
>> struct i915_wa wa = {
>> .reg = reg
>> @@ -1021,9 +1021,16 @@ whitelist_reg(struct i915_wa_list *wal,
>> i915_reg_t reg)
>> if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
>> return;
>> + wa.reg.reg |= flags;
>> _wa_add(wal, &wa);
>> }
>> +static void
>> +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
>> +{
>> + whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
>> +}
>> +
>> static void gen9_whitelist_build(struct i915_wa_list *w)
>> {
>> /*
>> WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index edf9f93934a1..10fea5ab3fc3 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2513,6 +2513,13 @@ enum i915_power_well_id {
>> #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
>> #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) +
>> (i) * 4)
>> +#define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ &
>> Gen11+ */
>
> Shouldn't this comment be against the RD and WR flags, while the above
> is the legacy one?
Technically, this field does not exist at all on older hardware. However
these bits are MBZ hence are equivalent to having the value of RW being
set. To me, it makes more sense to be accurate and label the entire
field as newer hardware only.
John.
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/4] drm/i915: Support flags in whitlist WAs
2019-06-18 1:13 ` John Harrison
@ 2019-06-18 6:51 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-18 6:51 UTC (permalink / raw)
To: John Harrison, intel-gfx
On 18/06/2019 02:13, John Harrison wrote:
> On 6/13/2019 23:48, Tvrtko Ursulin wrote:
>>
>> On 14/06/2019 01:28, Robert M. Fosha wrote:
>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>> Newer hardware adds flags to the whitelist work-around register. These
>>> allow per access direction privileges and ranges.
>>>
>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
>>> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 165b0a45e009..ae82340fff45 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -1012,7 +1012,7 @@ bool intel_gt_verify_workarounds(struct
>>> drm_i915_private *i915,
>>> }
>>> static void
>>> -whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
>>> +whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
>>> {
>>> struct i915_wa wa = {
>>> .reg = reg
>>> @@ -1021,9 +1021,16 @@ whitelist_reg(struct i915_wa_list *wal,
>>> i915_reg_t reg)
>>> if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
>>> return;
>>> + wa.reg.reg |= flags;
>>> _wa_add(wal, &wa);
>>> }
>>> +static void
>>> +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
>>> +{
>>> + whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
>>> +}
>>> +
>>> static void gen9_whitelist_build(struct i915_wa_list *w)
>>> {
>>> /*
>>> WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index edf9f93934a1..10fea5ab3fc3 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -2513,6 +2513,13 @@ enum i915_power_well_id {
>>> #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
>>> #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) +
>>> (i) * 4)
>>> +#define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ &
>>> Gen11+ */
>>
>> Shouldn't this comment be against the RD and WR flags, while the above
>> is the legacy one?
>
> Technically, this field does not exist at all on older hardware. However
> these bits are MBZ hence are equivalent to having the value of RW being
> set. To me, it makes more sense to be accurate and label the entire
> field as newer hardware only.
Did not see your reply initially due not being copied.
Okay then I guess. Just going forward make sure the patches for old
workarounds don't use RING_FORCE_TO_NONPRIV_RW like the previous round
did. (Can't have it both ways. ;)
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
2019-06-14 0:28 ` [PATCH 1/4] drm/i915: Support flags in whitlist WAs Robert M. Fosha
@ 2019-06-14 0:28 ` Robert M. Fosha
2019-06-14 6:50 ` Tvrtko Ursulin
2019-06-14 0:28 ` [PATCH 3/4] drm/i915: Add whitelist workarounds for CFL Robert M. Fosha
` (3 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Robert M. Fosha @ 2019-06-14 0:28 UTC (permalink / raw)
To: intel-gfx
From: John Harrison <John.C.Harrison@Intel.com>
Newer hardware requires setting up whitelists on engines other than
render. So, extend the whitelist code to support all engines.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++++++++------
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ae82340fff45..5308a0864e78 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1043,48 +1043,79 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
whitelist_reg(w, GEN8_HDC_CHICKEN1);
}
-static void skl_whitelist_build(struct i915_wa_list *w)
+static void skl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ if (engine->class != RENDER_CLASS)
+ return;
+
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:skl */
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void bxt_whitelist_build(struct i915_wa_list *w)
+static void bxt_whitelist_build(struct intel_engine_cs *engine)
{
- gen9_whitelist_build(w);
+ if (engine->class != RENDER_CLASS)
+ return;
+
+ gen9_whitelist_build(&engine->whitelist);
}
-static void kbl_whitelist_build(struct i915_wa_list *w)
+static void kbl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ if (engine->class != RENDER_CLASS)
+ return;
+
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:kbl */
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void glk_whitelist_build(struct i915_wa_list *w)
+static void glk_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ if (engine->class != RENDER_CLASS)
+ return;
+
gen9_whitelist_build(w);
/* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
}
-static void cfl_whitelist_build(struct i915_wa_list *w)
+static void cfl_whitelist_build(struct intel_engine_cs *engine)
{
- gen9_whitelist_build(w);
+ if (engine->class != RENDER_CLASS)
+ return;
+
+ gen9_whitelist_build(&engine->whitelist);
}
-static void cnl_whitelist_build(struct i915_wa_list *w)
+static void cnl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ if (engine->class != RENDER_CLASS)
+ return;
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
whitelist_reg(w, GEN8_CS_CHICKEN1);
}
-static void icl_whitelist_build(struct i915_wa_list *w)
+static void icl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ if (engine->class != RENDER_CLASS)
+ return;
+
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
@@ -1100,25 +1131,22 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
struct drm_i915_private *i915 = engine->i915;
struct i915_wa_list *w = &engine->whitelist;
- if (engine->class != RENDER_CLASS)
- return;
-
wa_init_start(w, "whitelist");
if (IS_GEN(i915, 11))
- icl_whitelist_build(w);
+ icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
- cnl_whitelist_build(w);
+ cnl_whitelist_build(engine);
else if (IS_COFFEELAKE(i915))
- cfl_whitelist_build(w);
+ cfl_whitelist_build(engine);
else if (IS_GEMINILAKE(i915))
- glk_whitelist_build(w);
+ glk_whitelist_build(engine);
else if (IS_KABYLAKE(i915))
- kbl_whitelist_build(w);
+ kbl_whitelist_build(engine);
else if (IS_BROXTON(i915))
- bxt_whitelist_build(w);
+ bxt_whitelist_build(engine);
else if (IS_SKYLAKE(i915))
- skl_whitelist_build(w);
+ skl_whitelist_build(engine);
else if (INTEL_GEN(i915) <= 8)
return;
else
--
2.21.0.5.gaeb582a983
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines
2019-06-14 0:28 ` [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines Robert M. Fosha
@ 2019-06-14 6:50 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 6:50 UTC (permalink / raw)
To: Robert M. Fosha, intel-gfx
On 14/06/2019 01:28, Robert M. Fosha wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Newer hardware requires setting up whitelists on engines other than
> render. So, extend the whitelist code to support all engines.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++++++++------
> 1 file changed, 47 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ae82340fff45..5308a0864e78 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1043,48 +1043,79 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
> whitelist_reg(w, GEN8_HDC_CHICKEN1);
> }
>
> -static void skl_whitelist_build(struct i915_wa_list *w)
> +static void skl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> gen9_whitelist_build(w);
>
> /* WaDisableLSQCROPERFforOCL:skl */
> whitelist_reg(w, GEN8_L3SQCREG4);
> }
>
> -static void bxt_whitelist_build(struct i915_wa_list *w)
> +static void bxt_whitelist_build(struct intel_engine_cs *engine)
> {
> - gen9_whitelist_build(w);
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> + gen9_whitelist_build(&engine->whitelist);
> }
>
> -static void kbl_whitelist_build(struct i915_wa_list *w)
> +static void kbl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> gen9_whitelist_build(w);
>
> /* WaDisableLSQCROPERFforOCL:kbl */
> whitelist_reg(w, GEN8_L3SQCREG4);
> }
>
> -static void glk_whitelist_build(struct i915_wa_list *w)
> +static void glk_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> gen9_whitelist_build(w);
>
> /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
> whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> }
>
> -static void cfl_whitelist_build(struct i915_wa_list *w)
> +static void cfl_whitelist_build(struct intel_engine_cs *engine)
> {
> - gen9_whitelist_build(w);
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> + gen9_whitelist_build(&engine->whitelist);
> }
>
> -static void cnl_whitelist_build(struct i915_wa_list *w)
> +static void cnl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> -static void icl_whitelist_build(struct i915_wa_list *w)
> +static void icl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + if (engine->class != RENDER_CLASS)
> + return;
> +
> /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
>
> @@ -1100,25 +1131,22 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> struct drm_i915_private *i915 = engine->i915;
> struct i915_wa_list *w = &engine->whitelist;
>
> - if (engine->class != RENDER_CLASS)
> - return;
> -
> wa_init_start(w, "whitelist");
>
> if (IS_GEN(i915, 11))
> - icl_whitelist_build(w);
> + icl_whitelist_build(engine);
> else if (IS_CANNONLAKE(i915))
> - cnl_whitelist_build(w);
> + cnl_whitelist_build(engine);
> else if (IS_COFFEELAKE(i915))
> - cfl_whitelist_build(w);
> + cfl_whitelist_build(engine);
> else if (IS_GEMINILAKE(i915))
> - glk_whitelist_build(w);
> + glk_whitelist_build(engine);
> else if (IS_KABYLAKE(i915))
> - kbl_whitelist_build(w);
> + kbl_whitelist_build(engine);
> else if (IS_BROXTON(i915))
> - bxt_whitelist_build(w);
> + bxt_whitelist_build(engine);
> else if (IS_SKYLAKE(i915))
> - skl_whitelist_build(w);
> + skl_whitelist_build(engine);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/4] drm/i915: Add whitelist workarounds for CFL
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
2019-06-14 0:28 ` [PATCH 1/4] drm/i915: Support flags in whitlist WAs Robert M. Fosha
2019-06-14 0:28 ` [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines Robert M. Fosha
@ 2019-06-14 0:28 ` Robert M. Fosha
2019-06-14 6:54 ` Tvrtko Ursulin
2019-06-14 0:28 ` [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL Robert M. Fosha
` (2 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Robert M. Fosha @ 2019-06-14 0:28 UTC (permalink / raw)
To: intel-gfx
From: John Harrison <John.C.Harrison@Intel.com>
Updated whitelist table for CFL.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 35 ++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5308a0864e78..60bd515edaf1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1092,10 +1092,43 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
static void cfl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
if (engine->class != RENDER_CLASS)
return;
- gen9_whitelist_build(&engine->whitelist);
+ /* Whitelist entries from BSpec page 53688: */
+ gen9_whitelist_build(w);
+
+ /* WaSendPushConstantsFromMMIO:cfl */
+ whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2,
+ RING_FORCE_TO_NONPRIV_RW);
+
+ /* GEN9_CS_DEBUG_MODE1 */
+ whitelist_reg_ext(w, GEN9_CS_DEBUG_MODE1,
+ RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaAllowUmdWriteTRTTRootTable:cfl */
+ whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaAllowUMDToDisableVFAutoStrip:cfl */
+ whitelist_reg_ext(w, _MMIO(0x83A8), RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl
+ * NB: this also pulls in CL_PRIMITIVES_COUNT in same block
+ * as PS_INVOCATIONS_COUNT. Likewise, TIMESTAMP in the
+ * PS_DEPTH_COUNT block.
+ */
+ whitelist_reg_ext(w, CL_PRIMITIVES_COUNT,
+ RING_FORCE_TO_NONPRIV_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+ whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /* WaAllowUMDAccesstoOARegisters:cfl */
+ whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW);
}
static void cnl_whitelist_build(struct intel_engine_cs *engine)
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 3/4] drm/i915: Add whitelist workarounds for CFL
2019-06-14 0:28 ` [PATCH 3/4] drm/i915: Add whitelist workarounds for CFL Robert M. Fosha
@ 2019-06-14 6:54 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 6:54 UTC (permalink / raw)
To: Robert M. Fosha, intel-gfx
On 14/06/2019 01:28, Robert M. Fosha wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Updated whitelist table for CFL.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 35 ++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5308a0864e78..60bd515edaf1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1092,10 +1092,43 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
>
> static void cfl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> if (engine->class != RENDER_CLASS)
> return;
>
> - gen9_whitelist_build(&engine->whitelist);
> + /* Whitelist entries from BSpec page 53688: */
> + gen9_whitelist_build(w);
> +
> + /* WaSendPushConstantsFromMMIO:cfl */
> + whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2,
> + RING_FORCE_TO_NONPRIV_RW);
> +
> + /* GEN9_CS_DEBUG_MODE1 */
> + whitelist_reg_ext(w, GEN9_CS_DEBUG_MODE1,
> + RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaAllowUmdWriteTRTTRootTable:cfl */
> + whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW);
> + whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaAllowUMDToDisableVFAutoStrip:cfl */
> + whitelist_reg_ext(w, _MMIO(0x83A8), RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl
> + * NB: this also pulls in CL_PRIMITIVES_COUNT in same block
> + * as PS_INVOCATIONS_COUNT. Likewise, TIMESTAMP in the
> + * PS_DEPTH_COUNT block.
> + */
Nitpick but please use multi-line comments in style:
/*
*
*/
We are trying not to add more of the unpopular style.
> + whitelist_reg_ext(w, CL_PRIMITIVES_COUNT,
> + RING_FORCE_TO_NONPRIV_RW |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> + whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RW |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + /* WaAllowUMDAccesstoOARegisters:cfl */
> + whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW);
> + whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW);
AFAICS majority of the register here shouldn't use the whitelist_reg_ext
but normal whitelist_reg. It will help with readability a bit and the
special ones would stick out more.
> }
>
> static void cnl_whitelist_build(struct intel_engine_cs *engine)
>
With the two tweaks:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
` (2 preceding siblings ...)
2019-06-14 0:28 ` [PATCH 3/4] drm/i915: Add whitelist workarounds for CFL Robert M. Fosha
@ 2019-06-14 0:28 ` Robert M. Fosha
2019-06-14 6:57 ` Tvrtko Ursulin
2019-06-14 1:09 ` ✗ Fi.CI.CHECKPATCH: warning for Update whitelist support for new hardware Patchwork
2019-06-14 14:23 ` ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 1 reply; 19+ messages in thread
From: Robert M. Fosha @ 2019-06-14 0:28 UTC (permalink / raw)
To: intel-gfx
From: John Harrison <John.C.Harrison@Intel.com>
Updated whitelist table for ICL.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 87 +++++++++++++++++++--
1 file changed, 79 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 60bd515edaf1..aa99fb3ffbcb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1146,17 +1146,88 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
- if (engine->class != RENDER_CLASS)
- return;
+ switch (engine->class) {
+ case RENDER_CLASS:
+ /* WaSendPushConstantsFromMMIO:icl */
+ whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2,
+ RING_FORCE_TO_NONPRIV_RW);
- /* WaAllowUMDToModifyHalfSliceChicken7:icl */
- whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg_ext(w, GEN9_HALF_SLICE_CHICKEN7,
+ RING_FORCE_TO_NONPRIV_RW);
- /* WaAllowUMDToModifySamplerMode:icl */
- whitelist_reg(w, GEN10_SAMPLER_MODE);
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg_ext(w, GEN10_SAMPLER_MODE,
+ RING_FORCE_TO_NONPRIV_RW);
- /* WaEnableStateCacheRedirectToCS:icl */
- whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+ /* WaEnableStateCacheRedirectToCS:icl */
+ whitelist_reg_ext(w, GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+ whitelist_reg_ext(w, HALF_SLICE_CHICKEN2,
+ RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaDisableMidObjectPreemptioninUMD:icl */
+ whitelist_reg_ext(w, GEN8_CS_CHICKEN1,
+ RING_FORCE_TO_NONPRIV_RW);
+
+ /* FtrSSEUPowerGatingControlByUMD:icl */
+ whitelist_reg_ext(w, _MMIO(0x20C8), RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaUseOaReportTriggersForQuery:icl */
+ whitelist_reg_ext(w, OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_RW);
+
+ /* WaAllowUmdWriteTRTTRootTable:icl */
+ whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW);
+
+ /* CL_PRIMITIVE_COUNT/PS_INVOCATIONS_COUNT */
+ whitelist_reg_ext(w, CL_PRIMITIVES_COUNT,
+ RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /* PS_DEPTH_COUNT */
+ whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /* EUMETRICS_EVENT_0 -> _5 */
+ whitelist_reg_ext(w, _MMIO(0xD8C), RING_FORCE_TO_NONPRIV_RD);
+ whitelist_reg_ext(w, _MMIO(0xD90), RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+ whitelist_reg_ext(w, _MMIO(0xDA0), RING_FORCE_TO_NONPRIV_RD);
+
+ /* SRD_PERF_COUNTER */
+ whitelist_reg_ext(w, _MMIO(0x64844), RING_FORCE_TO_NONPRIV_RD);
+
+ /* WaAllowUMDAccesstoOARegisters:icl */
+ whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW);
+ break;
+ case VIDEO_DECODE_CLASS:
+ /* hucStatusRegOffset */
+ whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_RD);
+ /* hucUKernelHdrInfoRegOffset */
+ whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_RD);
+ /* hucStatus2RegOffset */
+ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_RD);
+
+ /* fall through */
+ case VIDEO_ENHANCEMENT_CLASS:
+ /* WATCHDOG_COUNT_CONTROL */
+ whitelist_reg_ext(w, _MMIO(0x178 + engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_RD);
+
+ /* WATCHDOG_COUNT_THRESHOLD */
+ whitelist_reg_ext(w, _MMIO(0x17C + engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_RD);
+ break;
+ default:
+ break;
+ }
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL
2019-06-14 0:28 ` [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL Robert M. Fosha
@ 2019-06-14 6:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 6:57 UTC (permalink / raw)
To: Robert M. Fosha, intel-gfx
On 14/06/2019 01:28, Robert M. Fosha wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Updated whitelist table for ICL.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 87 +++++++++++++++++++--
> 1 file changed, 79 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 60bd515edaf1..aa99fb3ffbcb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1146,17 +1146,88 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
> {
> struct i915_wa_list *w = &engine->whitelist;
>
> - if (engine->class != RENDER_CLASS)
> - return;
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /* WaSendPushConstantsFromMMIO:icl */
> + whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2,
> + RING_FORCE_TO_NONPRIV_RW);
>
> - /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> - whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> + /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> + whitelist_reg_ext(w, GEN9_HALF_SLICE_CHICKEN7,
> + RING_FORCE_TO_NONPRIV_RW);
>
> - /* WaAllowUMDToModifySamplerMode:icl */
> - whitelist_reg(w, GEN10_SAMPLER_MODE);
> + /* WaAllowUMDToModifySamplerMode:icl */
> + whitelist_reg_ext(w, GEN10_SAMPLER_MODE,
> + RING_FORCE_TO_NONPRIV_RW);
>
> - /* WaEnableStateCacheRedirectToCS:icl */
> - whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> + /* WaEnableStateCacheRedirectToCS:icl */
> + whitelist_reg_ext(w, GEN9_SLICE_COMMON_ECO_CHICKEN1,
> + RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaAllowUMDToModifyHalfSliceChicken2:icl */
> + whitelist_reg_ext(w, HALF_SLICE_CHICKEN2,
> + RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaDisableMidObjectPreemptioninUMD:icl */
> + whitelist_reg_ext(w, GEN8_CS_CHICKEN1,
> + RING_FORCE_TO_NONPRIV_RW);
> +
> + /* FtrSSEUPowerGatingControlByUMD:icl */
> + whitelist_reg_ext(w, _MMIO(0x20C8), RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaUseOaReportTriggersForQuery:icl */
> + whitelist_reg_ext(w, OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_RW);
> +
> + /* WaAllowUmdWriteTRTTRootTable:icl */
> + whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW);
> + whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW);
> +
> + /* CL_PRIMITIVE_COUNT/PS_INVOCATIONS_COUNT */
> + whitelist_reg_ext(w, CL_PRIMITIVES_COUNT,
> + RING_FORCE_TO_NONPRIV_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + /* PS_DEPTH_COUNT */
> + whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + /* EUMETRICS_EVENT_0 -> _5 */
> + whitelist_reg_ext(w, _MMIO(0xD8C), RING_FORCE_TO_NONPRIV_RD);
> + whitelist_reg_ext(w, _MMIO(0xD90), RING_FORCE_TO_NONPRIV_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> + whitelist_reg_ext(w, _MMIO(0xDA0), RING_FORCE_TO_NONPRIV_RD);
> +
> + /* SRD_PERF_COUNTER */
> + whitelist_reg_ext(w, _MMIO(0x64844), RING_FORCE_TO_NONPRIV_RD);
> +
> + /* WaAllowUMDAccesstoOARegisters:icl */
> + whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW);
> + whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW);
> + break;
> + case VIDEO_DECODE_CLASS:
> + /* hucStatusRegOffset */
> + whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
> + RING_FORCE_TO_NONPRIV_RD);
> + /* hucUKernelHdrInfoRegOffset */
> + whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
> + RING_FORCE_TO_NONPRIV_RD);
> + /* hucStatus2RegOffset */
> + whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
> + RING_FORCE_TO_NONPRIV_RD);
> +
> + /* fall through */
> + case VIDEO_ENHANCEMENT_CLASS:
> + /* WATCHDOG_COUNT_CONTROL */
> + whitelist_reg_ext(w, _MMIO(0x178 + engine->mmio_base),
> + RING_FORCE_TO_NONPRIV_RD);
> +
> + /* WATCHDOG_COUNT_THRESHOLD */
> + whitelist_reg_ext(w, _MMIO(0x17C + engine->mmio_base),
> + RING_FORCE_TO_NONPRIV_RD);
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
Again I suggest not using whitelist_reg_ext where not required. With
that changed:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Update whitelist support for new hardware
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
` (3 preceding siblings ...)
2019-06-14 0:28 ` [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL Robert M. Fosha
@ 2019-06-14 1:09 ` Patchwork
2019-06-14 14:23 ` ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-06-14 1:09 UTC (permalink / raw)
To: Robert M. Fosha; +Cc: intel-gfx
== Series Details ==
Series: Update whitelist support for new hardware
URL : https://patchwork.freedesktop.org/series/62076/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
75becc1f2fcf drm/i915: Support flags in whitlist WAs
4ac7341292ad drm/i915: Support whitelist workarounds on all engines
4330ded0139b drm/i915: Add whitelist workarounds for CFL
-:36: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#36: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:1109:
+ whitelist_reg_ext(w, GEN9_CS_DEBUG_MODE1,
+ RING_FORCE_TO_NONPRIV_RW);
total: 0 errors, 0 warnings, 1 checks, 44 lines checked
f0e2fb83377c drm/i915: Add whitelist workarounds for ICL
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✗ Fi.CI.BAT: failure for Update whitelist support for new hardware
2019-06-14 0:28 [PATCH 0/4] Update whitelist support for new hardware Robert M. Fosha
` (4 preceding siblings ...)
2019-06-14 1:09 ` ✗ Fi.CI.CHECKPATCH: warning for Update whitelist support for new hardware Patchwork
@ 2019-06-14 14:23 ` Patchwork
2019-06-14 17:19 ` Tvrtko Ursulin
5 siblings, 1 reply; 19+ messages in thread
From: Patchwork @ 2019-06-14 14:23 UTC (permalink / raw)
To: Robert M. Fosha; +Cc: intel-gfx
== Series Details ==
Series: Update whitelist support for new hardware
URL : https://patchwork.freedesktop.org/series/62076/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6265 -> Patchwork_13279
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13279 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13279, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13279:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_workarounds:
- fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-guc/igt@i915_selftest@live_workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-guc/igt@i915_selftest@live_workarounds.html
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html
- fi-whl-u: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-whl-u/igt@i915_selftest@live_workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-whl-u/igt@i915_selftest@live_workarounds.html
- fi-cfl-8700k: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-8700k/igt@i915_selftest@live_workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-8700k/igt@i915_selftest@live_workarounds.html
- fi-cml-u2: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cml-u2/igt@i915_selftest@live_workarounds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cml-u2/igt@i915_selftest@live_workarounds.html
Known issues
------------
Here are the changes found in Patchwork_13279 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@basic:
- fi-cml-u: [PASS][11] -> [INCOMPLETE][12] ([fdo#110566])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cml-u/igt@gem_exec_create@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cml-u/igt@gem_exec_create@basic.html
* igt@i915_selftest@live_blt:
- fi-skl-iommu: [PASS][13] -> [INCOMPLETE][14] ([fdo#108602])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-skl-iommu/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-skl-iommu/igt@i915_selftest@live_blt.html
#### Possible fixes ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (53 -> 47)
------------------------------
Additional (1): fi-byt-j1900
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6265 -> Patchwork_13279
CI_DRM_6265: 657b9f601946cab518d8911ea92dc0f437a1f4b4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5055: 495287320225e7f180d384cad7b207b77154438f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13279: f0e2fb83377c7146bce4b758e107f46194607038 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f0e2fb83377c drm/i915: Add whitelist workarounds for ICL
4330ded0139b drm/i915: Add whitelist workarounds for CFL
4ac7341292ad drm/i915: Support whitelist workarounds on all engines
75becc1f2fcf drm/i915: Support flags in whitlist WAs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: ✗ Fi.CI.BAT: failure for Update whitelist support for new hardware
2019-06-14 14:23 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-06-14 17:19 ` Tvrtko Ursulin
2019-06-14 18:17 ` John Harrison
0 siblings, 1 reply; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 17:19 UTC (permalink / raw)
To: intel-gfx, Patchwork, Robert M. Fosha
On 14/06/2019 15:23, Patchwork wrote:
> == Series Details ==
>
> Series: Update whitelist support for new hardware
> URL : https://patchwork.freedesktop.org/series/62076/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6265 -> Patchwork_13279
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_13279 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_13279, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_13279:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live_workarounds:
> - fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-guc/igt@i915_selftest@live_workarounds.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-guc/igt@i915_selftest@live_workarounds.html
> - fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html
> - fi-whl-u: [PASS][5] -> [DMESG-FAIL][6]
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-whl-u/igt@i915_selftest@live_workarounds.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-whl-u/igt@i915_selftest@live_workarounds.html
> - fi-cfl-8700k: [PASS][7] -> [DMESG-FAIL][8]
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cfl-8700k/igt@i915_selftest@live_workarounds.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cfl-8700k/igt@i915_selftest@live_workarounds.html
> - fi-cml-u2: [PASS][9] -> [DMESG-FAIL][10]
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cml-u2/igt@i915_selftest@live_workarounds.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cml-u2/igt@i915_selftest@live_workarounds.html
Read-back of 0x20ec (GEN9_CS_DEBUG_MODE1) seems to be causing issues. It
could be put on the wo_register list if appropriate. And/or made
RING_FORCE_TO_NONPRIV_RW.
However now I realize that handling of new whitelisting modes is missing
from the selftest altogether. All RING_FORCE_TO_NONPRIV_RD and
RING_FORCE_TO_NONPRIV_WR probably need explicit handling there - first
ones to check they cannot be written to, and skip read-back on the
second one.
Regards,
Tvrtko
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_13279 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_create@basic:
> - fi-cml-u: [PASS][11] -> [INCOMPLETE][12] ([fdo#110566])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-cml-u/igt@gem_exec_create@basic.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-cml-u/igt@gem_exec_create@basic.html
>
> * igt@i915_selftest@live_blt:
> - fi-skl-iommu: [PASS][13] -> [INCOMPLETE][14] ([fdo#108602])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-skl-iommu/igt@i915_selftest@live_blt.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-skl-iommu/igt@i915_selftest@live_blt.html
>
>
> #### Possible fixes ####
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6265/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
>
>
> [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
> [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
> [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
>
>
> Participating hosts (53 -> 47)
> ------------------------------
>
> Additional (1): fi-byt-j1900
> Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_6265 -> Patchwork_13279
>
> CI_DRM_6265: 657b9f601946cab518d8911ea92dc0f437a1f4b4 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5055: 495287320225e7f180d384cad7b207b77154438f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_13279: f0e2fb83377c7146bce4b758e107f46194607038 @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> f0e2fb83377c drm/i915: Add whitelist workarounds for ICL
> 4330ded0139b drm/i915: Add whitelist workarounds for CFL
> 4ac7341292ad drm/i915: Support whitelist workarounds on all engines
> 75becc1f2fcf drm/i915: Support flags in whitlist WAs
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13279/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for Update whitelist support for new hardware
2019-06-14 17:19 ` Tvrtko Ursulin
@ 2019-06-14 18:17 ` John Harrison
2019-06-14 18:22 ` Chris Wilson
0 siblings, 1 reply; 19+ messages in thread
From: John Harrison @ 2019-06-14 18:17 UTC (permalink / raw)
To: intel-gfx
On 6/14/2019 10:19, Tvrtko Ursulin wrote:
>
> Read-back of 0x20ec (GEN9_CS_DEBUG_MODE1) seems to be causing issues.
> It could be put on the wo_register list if appropriate. And/or made
> RING_FORCE_TO_NONPRIV_RW.
>
> However now I realize that handling of new whitelisting modes is
> missing from the selftest altogether. All RING_FORCE_TO_NONPRIV_RD and
> RING_FORCE_TO_NONPRIV_WR probably need explicit handling there - first
> ones to check they cannot be written to, and skip read-back on the
> second one.
>
> Regards,
>
> Tvrtko
It looks like there are multiple issues.
I think the quickest/simplest option right now is to drop a bunch of the
ICL updates (because there are too many for the current 12 slot maximum)
and to drop the problematic CFL updates.
The only changes that are urgently needed are the HUC status registers.
Unfortunately, they are read-only entries. So the self-test will need to
be updated to cope with those. Not sure what it can do though. Do we
just skip read-only entries? The test can't know what a valid value to
read back is.
The rest we can put back in later on once all the other issues have been
resolved.
John.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for Update whitelist support for new hardware
2019-06-14 18:17 ` John Harrison
@ 2019-06-14 18:22 ` Chris Wilson
2019-06-14 18:44 ` Tvrtko Ursulin
0 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-06-14 18:22 UTC (permalink / raw)
To: John Harrison, intel-gfx
Quoting John Harrison (2019-06-14 19:17:25)
> On 6/14/2019 10:19, Tvrtko Ursulin wrote:
> >
> > Read-back of 0x20ec (GEN9_CS_DEBUG_MODE1) seems to be causing issues.
> > It could be put on the wo_register list if appropriate. And/or made
> > RING_FORCE_TO_NONPRIV_RW.
> >
> > However now I realize that handling of new whitelisting modes is
> > missing from the selftest altogether. All RING_FORCE_TO_NONPRIV_RD and
> > RING_FORCE_TO_NONPRIV_WR probably need explicit handling there - first
> > ones to check they cannot be written to, and skip read-back on the
> > second one.
> >
> > Regards,
> >
> > Tvrtko
>
> It looks like there are multiple issues.
>
> I think the quickest/simplest option right now is to drop a bunch of the
> ICL updates (because there are too many for the current 12 slot maximum)
> and to drop the problematic CFL updates.
>
> The only changes that are urgently needed are the HUC status registers.
> Unfortunately, they are read-only entries. So the self-test will need to
> be updated to cope with those. Not sure what it can do though. Do we
> just skip read-only entries? The test can't know what a valid value to
> read back is.
There's an exception list [wo_register] for registers that don't
conform to the test expectations.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for Update whitelist support for new hardware
2019-06-14 18:22 ` Chris Wilson
@ 2019-06-14 18:44 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2019-06-14 18:44 UTC (permalink / raw)
To: Chris Wilson, John Harrison, intel-gfx
On 14/06/2019 19:22, Chris Wilson wrote:
> Quoting John Harrison (2019-06-14 19:17:25)
>> On 6/14/2019 10:19, Tvrtko Ursulin wrote:
>>>
>>> Read-back of 0x20ec (GEN9_CS_DEBUG_MODE1) seems to be causing issues.
>>> It could be put on the wo_register list if appropriate. And/or made
>>> RING_FORCE_TO_NONPRIV_RW.
>>>
>>> However now I realize that handling of new whitelisting modes is
>>> missing from the selftest altogether. All RING_FORCE_TO_NONPRIV_RD and
>>> RING_FORCE_TO_NONPRIV_WR probably need explicit handling there - first
>>> ones to check they cannot be written to, and skip read-back on the
>>> second one.
>>>
>>> Regards,
>>>
>>> Tvrtko
>>
>> It looks like there are multiple issues.
>>
>> I think the quickest/simplest option right now is to drop a bunch of the
>> ICL updates (because there are too many for the current 12 slot maximum)
>> and to drop the problematic CFL updates.
>>
>> The only changes that are urgently needed are the HUC status registers.
>> Unfortunately, they are read-only entries. So the self-test will need to
>> be updated to cope with those. Not sure what it can do though. Do we
>> just skip read-only entries? The test can't know what a valid value to
>> read back is.
Plan sounds good to me. (Drop everything apart from HuC.)
> There's an exception list [wo_register] for registers that don't
> conform to the test expectations.
But that's not appropriate for read-only ones. I think for these we
modify the selftest to read before and after writing and check value is
unchanged. Is that doable today or Monday at latest?
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread