From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/19] drm/i915/gt: Move new timelines to the end of active_list
Date: Tue, 19 Nov 2019 16:02:57 +0000 [thread overview]
Message-ID: <3e45f650-08be-1ab8-7302-3af6cc1f83b3@linux.intel.com> (raw)
In-Reply-To: <20191118230254.2615942-14-chris@chris-wilson.co.uk>
On 18/11/2019 23:02, Chris Wilson wrote:
> When adding a new active timeline, place it at the end of the list. This
> allows for intel_gt_retire_requests() to pick up the newcomer more
> quickly and hopefully complete the retirement sooner.
>
> References: 7936a22dd466 ("drm/i915/gt: Wait for new requests in intel_gt_retire_requests()")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index bd973d950064..b190a5d9ab02 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -359,7 +359,7 @@ void intel_timeline_enter(struct intel_timeline *tl)
>
> spin_lock(&timelines->lock);
> if (!atomic_fetch_inc(&tl->active_count))
> - list_add(&tl->link, &timelines->active_list);
> + list_add_tail(&tl->link, &timelines->active_list);
> spin_unlock(&timelines->lock);
> }
>
>
If I am not missing something this should be on the micro-optimisation
level, well, mini-optimisation. Since for instance now it could wait on
the most recent request and when that finishes do mostly signalled
checks, or even less. With the change it would first sweep the already
completed ones and then wait for the most recent one. Nevertheless, I
don't see a problem with it so:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 13/19] drm/i915/gt: Move new timelines to the end of active_list
Date: Tue, 19 Nov 2019 16:02:57 +0000 [thread overview]
Message-ID: <3e45f650-08be-1ab8-7302-3af6cc1f83b3@linux.intel.com> (raw)
Message-ID: <20191119160257.irHAW2IswBXz7Rg657jfz7rGRai9cNqyXzJQyg66aIs@z> (raw)
In-Reply-To: <20191118230254.2615942-14-chris@chris-wilson.co.uk>
On 18/11/2019 23:02, Chris Wilson wrote:
> When adding a new active timeline, place it at the end of the list. This
> allows for intel_gt_retire_requests() to pick up the newcomer more
> quickly and hopefully complete the retirement sooner.
>
> References: 7936a22dd466 ("drm/i915/gt: Wait for new requests in intel_gt_retire_requests()")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index bd973d950064..b190a5d9ab02 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -359,7 +359,7 @@ void intel_timeline_enter(struct intel_timeline *tl)
>
> spin_lock(&timelines->lock);
> if (!atomic_fetch_inc(&tl->active_count))
> - list_add(&tl->link, &timelines->active_list);
> + list_add_tail(&tl->link, &timelines->active_list);
> spin_unlock(&timelines->lock);
> }
>
>
If I am not missing something this should be on the micro-optimisation
level, well, mini-optimisation. Since for instance now it could wait on
the most recent request and when that finishes do mostly signalled
checks, or even less. With the change it would first sweep the already
completed ones and then wait for the most recent one. Nevertheless, I
don't see a problem with it so:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-19 16:03 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 23:02 Fast soft-rc6 Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 01/19] drm/i915/selftests: Force bonded submission to overlap Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 02/19] drm/i915/gem: Manually dump the debug trace on GEM_BUG_ON Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 03/19] drm/i915/gt: Close race between engine_park and intel_gt_retire_requests Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:15 ` Tvrtko Ursulin
2019-11-19 14:15 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 14:41 ` Chris Wilson
2019-11-19 14:41 ` [Intel-gfx] " Chris Wilson
2019-11-20 11:39 ` Tvrtko Ursulin
2019-11-20 11:39 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-20 11:51 ` Chris Wilson
2019-11-20 11:51 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 04/19] drm/i915/gt: Unlock engine-pm after queuing the kernel context switch Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:35 ` Tvrtko Ursulin
2019-11-19 14:35 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 14:50 ` Chris Wilson
2019-11-19 14:50 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:03 ` [PATCH] " Chris Wilson
2019-11-19 15:03 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 05/19] drm/i915/gt: Make intel_ring_unpin() safe for concurrent pint Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:54 ` Tvrtko Ursulin
2019-11-19 14:54 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 06/19] drm/i915/gt: Schedule request retirement when submission idles Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:04 ` Tvrtko Ursulin
2019-11-19 15:04 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:20 ` Chris Wilson
2019-11-19 16:20 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:33 ` Tvrtko Ursulin
2019-11-19 16:33 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:42 ` Chris Wilson
2019-11-19 16:42 ` [Intel-gfx] " Chris Wilson
2019-11-19 18:58 ` Chris Wilson
2019-11-19 18:58 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 07/19] drm/i915: Mark up the calling context for intel_wakeref_put() Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:57 ` Tvrtko Ursulin
2019-11-19 15:57 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:12 ` Chris Wilson
2019-11-19 16:12 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 08/19] drm/i915/gem: Merge GGTT vma flush into a single loop Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 09/19] drm/i915/gt: Only wait for register chipset flush if active Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 10/19] drm/i915: Protect the obj->vma.list during iteration Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 11/19] drm/i915: Wait until the intel_wakeref idle callback is complete Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:15 ` Tvrtko Ursulin
2019-11-19 16:15 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 12/19] drm/i915/gt: Declare timeline.lock to be irq-free Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:58 ` Tvrtko Ursulin
2019-11-19 15:58 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 13/19] drm/i915/gt: Move new timelines to the end of active_list Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:02 ` Tvrtko Ursulin [this message]
2019-11-19 16:02 ` Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 14/19] drm/i915/gt: Schedule next retirement worker first Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:07 ` Tvrtko Ursulin
2019-11-19 16:07 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 15/19] drm/i915/gt: Flush the requests after wedging on suspend Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:12 ` Tvrtko Ursulin
2019-11-19 16:12 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 17:22 ` Chris Wilson
2019-11-19 17:22 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 16/19] drm/i915/selftests: Flush the active callbacks Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 17/19] drm/i915/selftests: Be explicit in ERR_PTR handling Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 18/19] drm/i915/selftests: Exercise rc6 handling Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 19/19] drm/i915/gt: Track engine round-trip times Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:21 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/19] drm/i915/selftests: Force bonded submission to overlap Patchwork
2019-11-18 23:21 ` [Intel-gfx] " Patchwork
2019-11-19 0:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-19 0:04 ` [Intel-gfx] " Patchwork
2019-11-19 9:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-19 9:08 ` [Intel-gfx] " Patchwork
2019-11-19 19:04 ` ✗ Fi.CI.BUILD: failure for series starting with [01/19] drm/i915/selftests: Force bonded submission to overlap (rev2) Patchwork
2019-11-19 19:04 ` [Intel-gfx] " Patchwork
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