From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 04/19] drm/i915/gt: Unlock engine-pm after queuing the kernel context switch
Date: Tue, 19 Nov 2019 14:35:04 +0000 [thread overview]
Message-ID: <58557b4d-4266-9b4b-1bb3-923f23479107@linux.intel.com> (raw)
In-Reply-To: <20191118230254.2615942-5-chris@chris-wilson.co.uk>
On 18/11/2019 23:02, Chris Wilson wrote:
> In commit a79ca656b648 ("drm/i915: Push the wakeref->count deferral to
> the backend"), I erroneously concluded that we last modify the engine
> inside __i915_request_commit() meaning that we could enable concurrent
> submission for userspace as we enqueued this request. However, this
> falls into a trap with other users of the engine->kernel_context waking
> up and submitting their request before the idle-switch is queued, with
> the result that the kernel_context is executed out-of-sequence most
> likely upsetting the GPU and certainly ourselves when we try to retire
> the out-of-sequence requests.
>
> As such we need to hold onto the effective engine->kernel_context mutex
> lock (via the engine pm mutex proxy) until we have finish queuing the
> request to the engine.
>
> v2: Serialise against concurrent intel_gt_retire_requests()
>
> Fixes: a79ca656b648 ("drm/i915: Push the wakeref->count deferral to the backend")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 3c0f490ff2c7..722d3eec226e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -75,6 +75,7 @@ static inline void __timeline_mark_unlock(struct intel_context *ce,
>
> static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> {
> + struct intel_context *ce = engine->kernel_context;
> struct i915_request *rq;
> unsigned long flags;
> bool result = true;
> @@ -99,15 +100,13 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> * retiring the last request, thus all rings should be empty and
> * all timelines idle.
> */
> - flags = __timeline_mark_lock(engine->kernel_context);
> + flags = __timeline_mark_lock(ce);
>
> - rq = __i915_request_create(engine->kernel_context, GFP_NOWAIT);
> + rq = __i915_request_create(ce, GFP_NOWAIT);
> if (IS_ERR(rq))
> /* Context switch failed, hope for the best! Maybe reset? */
> goto out_unlock;
>
> - intel_timeline_enter(i915_request_timeline(rq));
> -
> /* Check again on the next retirement. */
> engine->wakeref_serial = engine->serial + 1;
> i915_request_add_active_barriers(rq);
> @@ -116,13 +115,17 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> rq->sched.attr.priority = I915_PRIORITY_BARRIER;
> __i915_request_commit(rq);
>
> + __i915_request_queue(rq, NULL);
> +
> /* Release our exclusive hold on the engine */
> __intel_wakeref_defer_park(&engine->wakeref);
> - __i915_request_queue(rq, NULL);
> +
> + /* And finally expose our selfselves to intel_gt_retire_requests()
ourselves
*/
> + intel_timeline_enter(ce->timeline);
I haven't really managed to follow this.
What are these other clients which can queue requests and what in this
block prevents them doing so?
The change seems to be moving the queuing to before
__intel_wakeref_defer_park and intel_timeline_enter to last. Wakeref
defer extends the engine lifetime until the submitted rq is retired. But
how is that consider "unlocking"?
Regards,
Tvrtko
>
> result = false;
> out_unlock:
> - __timeline_mark_unlock(engine->kernel_context, flags);
> + __timeline_mark_unlock(ce, flags);
> return result;
> }
>
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 04/19] drm/i915/gt: Unlock engine-pm after queuing the kernel context switch
Date: Tue, 19 Nov 2019 14:35:04 +0000 [thread overview]
Message-ID: <58557b4d-4266-9b4b-1bb3-923f23479107@linux.intel.com> (raw)
Message-ID: <20191119143504.HBgXmmHahWCHO9RYAXfiiVdM27Ei3bhewFI3PiFtWHg@z> (raw)
In-Reply-To: <20191118230254.2615942-5-chris@chris-wilson.co.uk>
On 18/11/2019 23:02, Chris Wilson wrote:
> In commit a79ca656b648 ("drm/i915: Push the wakeref->count deferral to
> the backend"), I erroneously concluded that we last modify the engine
> inside __i915_request_commit() meaning that we could enable concurrent
> submission for userspace as we enqueued this request. However, this
> falls into a trap with other users of the engine->kernel_context waking
> up and submitting their request before the idle-switch is queued, with
> the result that the kernel_context is executed out-of-sequence most
> likely upsetting the GPU and certainly ourselves when we try to retire
> the out-of-sequence requests.
>
> As such we need to hold onto the effective engine->kernel_context mutex
> lock (via the engine pm mutex proxy) until we have finish queuing the
> request to the engine.
>
> v2: Serialise against concurrent intel_gt_retire_requests()
>
> Fixes: a79ca656b648 ("drm/i915: Push the wakeref->count deferral to the backend")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 3c0f490ff2c7..722d3eec226e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -75,6 +75,7 @@ static inline void __timeline_mark_unlock(struct intel_context *ce,
>
> static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> {
> + struct intel_context *ce = engine->kernel_context;
> struct i915_request *rq;
> unsigned long flags;
> bool result = true;
> @@ -99,15 +100,13 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> * retiring the last request, thus all rings should be empty and
> * all timelines idle.
> */
> - flags = __timeline_mark_lock(engine->kernel_context);
> + flags = __timeline_mark_lock(ce);
>
> - rq = __i915_request_create(engine->kernel_context, GFP_NOWAIT);
> + rq = __i915_request_create(ce, GFP_NOWAIT);
> if (IS_ERR(rq))
> /* Context switch failed, hope for the best! Maybe reset? */
> goto out_unlock;
>
> - intel_timeline_enter(i915_request_timeline(rq));
> -
> /* Check again on the next retirement. */
> engine->wakeref_serial = engine->serial + 1;
> i915_request_add_active_barriers(rq);
> @@ -116,13 +115,17 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
> rq->sched.attr.priority = I915_PRIORITY_BARRIER;
> __i915_request_commit(rq);
>
> + __i915_request_queue(rq, NULL);
> +
> /* Release our exclusive hold on the engine */
> __intel_wakeref_defer_park(&engine->wakeref);
> - __i915_request_queue(rq, NULL);
> +
> + /* And finally expose our selfselves to intel_gt_retire_requests()
ourselves
*/
> + intel_timeline_enter(ce->timeline);
I haven't really managed to follow this.
What are these other clients which can queue requests and what in this
block prevents them doing so?
The change seems to be moving the queuing to before
__intel_wakeref_defer_park and intel_timeline_enter to last. Wakeref
defer extends the engine lifetime until the submitted rq is retired. But
how is that consider "unlocking"?
Regards,
Tvrtko
>
> result = false;
> out_unlock:
> - __timeline_mark_unlock(engine->kernel_context, flags);
> + __timeline_mark_unlock(ce, flags);
> return result;
> }
>
>
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next prev parent reply other threads:[~2019-11-19 14:35 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 23:02 Fast soft-rc6 Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 01/19] drm/i915/selftests: Force bonded submission to overlap Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 02/19] drm/i915/gem: Manually dump the debug trace on GEM_BUG_ON Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 03/19] drm/i915/gt: Close race between engine_park and intel_gt_retire_requests Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:15 ` Tvrtko Ursulin
2019-11-19 14:15 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 14:41 ` Chris Wilson
2019-11-19 14:41 ` [Intel-gfx] " Chris Wilson
2019-11-20 11:39 ` Tvrtko Ursulin
2019-11-20 11:39 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-20 11:51 ` Chris Wilson
2019-11-20 11:51 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 04/19] drm/i915/gt: Unlock engine-pm after queuing the kernel context switch Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:35 ` Tvrtko Ursulin [this message]
2019-11-19 14:35 ` Tvrtko Ursulin
2019-11-19 14:50 ` Chris Wilson
2019-11-19 14:50 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:03 ` [PATCH] " Chris Wilson
2019-11-19 15:03 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 05/19] drm/i915/gt: Make intel_ring_unpin() safe for concurrent pint Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 14:54 ` Tvrtko Ursulin
2019-11-19 14:54 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 06/19] drm/i915/gt: Schedule request retirement when submission idles Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:04 ` Tvrtko Ursulin
2019-11-19 15:04 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:20 ` Chris Wilson
2019-11-19 16:20 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:33 ` Tvrtko Ursulin
2019-11-19 16:33 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:42 ` Chris Wilson
2019-11-19 16:42 ` [Intel-gfx] " Chris Wilson
2019-11-19 18:58 ` Chris Wilson
2019-11-19 18:58 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 07/19] drm/i915: Mark up the calling context for intel_wakeref_put() Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:57 ` Tvrtko Ursulin
2019-11-19 15:57 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 16:12 ` Chris Wilson
2019-11-19 16:12 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 08/19] drm/i915/gem: Merge GGTT vma flush into a single loop Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 09/19] drm/i915/gt: Only wait for register chipset flush if active Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 10/19] drm/i915: Protect the obj->vma.list during iteration Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 11/19] drm/i915: Wait until the intel_wakeref idle callback is complete Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:15 ` Tvrtko Ursulin
2019-11-19 16:15 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 12/19] drm/i915/gt: Declare timeline.lock to be irq-free Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 15:58 ` Tvrtko Ursulin
2019-11-19 15:58 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 13/19] drm/i915/gt: Move new timelines to the end of active_list Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:02 ` Tvrtko Ursulin
2019-11-19 16:02 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 14/19] drm/i915/gt: Schedule next retirement worker first Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:07 ` Tvrtko Ursulin
2019-11-19 16:07 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-18 23:02 ` [PATCH 15/19] drm/i915/gt: Flush the requests after wedging on suspend Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-19 16:12 ` Tvrtko Ursulin
2019-11-19 16:12 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-19 17:22 ` Chris Wilson
2019-11-19 17:22 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 16/19] drm/i915/selftests: Flush the active callbacks Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 17/19] drm/i915/selftests: Be explicit in ERR_PTR handling Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 18/19] drm/i915/selftests: Exercise rc6 handling Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:02 ` [PATCH 19/19] drm/i915/gt: Track engine round-trip times Chris Wilson
2019-11-18 23:02 ` [Intel-gfx] " Chris Wilson
2019-11-18 23:21 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/19] drm/i915/selftests: Force bonded submission to overlap Patchwork
2019-11-18 23:21 ` [Intel-gfx] " Patchwork
2019-11-19 0:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-19 0:04 ` [Intel-gfx] " Patchwork
2019-11-19 9:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-19 9:08 ` [Intel-gfx] " Patchwork
2019-11-19 19:04 ` ✗ Fi.CI.BUILD: failure for series starting with [01/19] drm/i915/selftests: Force bonded submission to overlap (rev2) Patchwork
2019-11-19 19:04 ` [Intel-gfx] " Patchwork
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