From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
Date: Wed, 10 Oct 2012 23:37:36 +0100 [thread overview]
Message-ID: <453bf0$61is0t@azsmga001.ch.intel.com> (raw)
In-Reply-To: <1349903641-18378-3-git-send-email-daniel.vetter@ffwll.ch>
On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> It doesn't work since the gtt pte range sits in the middle of the mmio
> bar. We didn't notice that since both my and Chris' gen2 machines
> don't support PAT and hence all wc io mapping request will
> automatically be demoted to uc.
>
> This regression has been introduce in
>
> commit edef7e685da05c13cce50c0126189c80fe2c8f71
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Fri Sep 14 11:57:47 2012 +0100
>
> agp/intel: Use a write-combining map for updating PTEs
>
> Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thanks for the explanation,
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-10-10 22:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-10 21:13 [PATCH 1/3] drm/i915: rip out the pipe A quirk for i855gm Daniel Vetter
2012-10-10 21:14 ` [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code Daniel Vetter
2012-10-11 8:03 ` Chris Wilson
2012-10-10 21:14 ` [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Daniel Vetter
2012-10-10 22:37 ` Chris Wilson [this message]
2012-10-11 8:37 ` Daniel Vetter
2012-10-11 8:45 ` Chris Wilson
2012-10-11 9:05 ` Daniel Vetter
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