* [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
@ 2023-10-23 20:21 ` Andrzej Hajda
2023-10-24 8:14 ` Nirmoy Das
2023-10-24 9:10 ` Andi Shyti
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (5 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Andrzej Hajda @ 2023-10-23 20:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Jonathan Cavitt, Andrzej Hajda, Chris Wilson
Reserve one page in each vm for kernel space to use for things
such as workarounds.
v2: use real memory, do not decrease vm.total
v4: reserve only one page and explain flag
Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 38 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9895e18df0435a..1ac619a02a8567 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -5,6 +5,7 @@
#include <linux/log2.h>
+#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
#include "gen8_ppgtt.h"
@@ -950,6 +951,39 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
return ERR_PTR(err);
}
+static int gen8_init_rsvd(struct i915_address_space *vm)
+{
+ struct drm_i915_private *i915 = vm->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int ret;
+
+ /* The memory will be used only by GPU. */
+ obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
+ I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_GPU_ONLY);
+ if (IS_ERR(obj))
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto unref;
+ }
+
+ ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
+ if (ret)
+ goto unref;
+
+ vm->rsvd = i915_vma_make_unshrinkable(vma);
+
+unref:
+ i915_gem_object_put(obj);
+ return ret;
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1031,6 +1065,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
if (intel_vgpu_active(gt->i915))
gen8_ppgtt_notify_vgt(ppgtt, true);
+ err = gen8_init_rsvd(&ppgtt->vm);
+ if (err)
+ goto err_put;
+
return ppgtt;
err_put:
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index b471edac269920..5ac079e5f12f67 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -249,6 +249,7 @@ struct i915_address_space {
struct work_struct release_work;
struct drm_mm mm;
+ struct i915_vma *rsvd;
struct intel_gt *gt;
struct drm_i915_private *i915;
struct device *dma;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
@ 2023-10-24 8:14 ` Nirmoy Das
2023-10-24 9:10 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Nirmoy Das @ 2023-10-24 8:14 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Chris Wilson, Jonathan Cavitt
On 10/23/2023 10:21 PM, Andrzej Hajda wrote:
> Reserve one page in each vm for kernel space to use for things
> such as workarounds.
>
> v2: use real memory, do not decrease vm.total
> v4: reserve only one page and explain flag
>
> Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 38 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
> 2 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 9895e18df0435a..1ac619a02a8567 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -5,6 +5,7 @@
>
> #include <linux/log2.h>
>
> +#include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_lmem.h"
>
> #include "gen8_ppgtt.h"
> @@ -950,6 +951,39 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> return ERR_PTR(err);
> }
>
> +static int gen8_init_rsvd(struct i915_address_space *vm)
> +{
> + struct drm_i915_private *i915 = vm->i915;
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + int ret;
> +
> + /* The memory will be used only by GPU. */
> + obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
> + I915_BO_ALLOC_VOLATILE |
> + I915_BO_ALLOC_GPU_ONLY);
> + if (IS_ERR(obj))
> + obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + return PTR_ERR(obj);
> +
> + vma = i915_vma_instance(obj, vm, NULL);
> + if (IS_ERR(vma)) {
> + ret = PTR_ERR(vma);
> + goto unref;
> + }
> +
> + ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
> + if (ret)
> + goto unref;
> +
> + vm->rsvd = i915_vma_make_unshrinkable(vma);
> +
> +unref:
> + i915_gem_object_put(obj);
> + return ret;
> +}
> +
> /*
> * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
> * with a net effect resembling a 2-level page table in normal x86 terms. Each
> @@ -1031,6 +1065,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> if (intel_vgpu_active(gt->i915))
> gen8_ppgtt_notify_vgt(ppgtt, true);
>
> + err = gen8_init_rsvd(&ppgtt->vm);
> + if (err)
> + goto err_put;
> +
> return ppgtt;
>
> err_put:
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index b471edac269920..5ac079e5f12f67 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -249,6 +249,7 @@ struct i915_address_space {
> struct work_struct release_work;
>
> struct drm_mm mm;
> + struct i915_vma *rsvd;
> struct intel_gt *gt;
> struct drm_i915_private *i915;
> struct device *dma;
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
2023-10-24 8:14 ` Nirmoy Das
@ 2023-10-24 9:10 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-10-24 9:10 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx, Jonathan Cavitt, Chris Wilson
Hi Andrzej,
On Mon, Oct 23, 2023 at 10:21:45PM +0200, Andrzej Hajda wrote:
> Reserve one page in each vm for kernel space to use for things
> such as workarounds.
>
> v2: use real memory, do not decrease vm.total
> v4: reserve only one page and explain flag
>
> Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH v4 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
@ 2023-10-23 20:21 ` Andrzej Hajda
2023-10-24 11:37 ` Andi Shyti
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB Andrzej Hajda
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Andrzej Hajda @ 2023-10-23 20:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Jonathan Cavitt, Andrzej Hajda, Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
v3: drop unused enum definition
v4: move selftest to separate patch, use wa only on BCS0.
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 100 +++++++++++++++++++++++++++-
3 files changed, 104 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index fdd4ddd3a978a2..b8618ee3e3041a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -118,6 +118,9 @@
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3)
#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
+#define PER_CTX_BB_FORCE BIT(2)
+#define PER_CTX_BB_VALID BIT(0)
+
#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
#define ECOSKPD(base) _MMIO((base) + 0x1d0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 970bedf6b78a7b..9ffdb05e231e21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -82,6 +82,10 @@ struct drm_printer;
##__VA_ARGS__); \
} while (0)
+#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
+ IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \
+ engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
+
static inline bool gt_is_root(struct intel_gt *gt)
{
return !gt->info.id;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index eaf66d90316655..96ef901113eae9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -828,6 +828,18 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
return 0;
}
+static void
+lrc_setup_bb_per_ctx(u32 *regs,
+ const struct intel_engine_cs *engine,
+ u32 ctx_bb_ggtt_addr)
+{
+ GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
+ regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
+ ctx_bb_ggtt_addr |
+ PER_CTX_BB_FORCE |
+ PER_CTX_BB_VALID;
+}
+
static void
lrc_setup_indirect_ctx(u32 *regs,
const struct intel_engine_cs *engine,
@@ -1020,7 +1032,13 @@ static u32 context_wa_bb_offset(const struct intel_context *ce)
return PAGE_SIZE * ce->wa_bb_page;
}
-static u32 *context_indirect_bb(const struct intel_context *ce)
+/*
+ * per_ctx below determines which WABB section is used.
+ * When true, the function returns the location of the
+ * PER_CTX_BB. When false, the function returns the
+ * location of the INDIRECT_CTX.
+ */
+static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
{
void *ptr;
@@ -1029,6 +1047,7 @@ static u32 *context_indirect_bb(const struct intel_context *ce)
ptr = ce->lrc_reg_state;
ptr -= LRC_STATE_OFFSET; /* back to start of context image */
ptr += context_wa_bb_offset(ce);
+ ptr += per_ctx ? PAGE_SIZE : 0;
return ptr;
}
@@ -1105,7 +1124,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (GRAPHICS_VER(engine->i915) >= 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
- context_size += PAGE_SIZE;
+ /* INDIRECT_CTX and PER_CTX_BB need separate pages. */
+ context_size += PAGE_SIZE * 2;
}
if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
@@ -1407,12 +1427,85 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)
return gen12_emit_aux_table_inv(ce->engine, cs);
}
+static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)
+{
+ struct intel_gt *gt = ce->engine->gt;
+ int mocs = gt->mocs.uc_index << 1;
+
+ /**
+ * Wa_16018031267 / Wa_16018063123 requires that SW forces the
+ * main copy engine arbitration into round robin mode. We
+ * additionally need to submit the following WABB blt command
+ * to produce 4 subblits with each subblit generating 0 byte
+ * write requests as WABB:
+ *
+ * XY_FASTCOLOR_BLT
+ * BG0 -> 5100000E
+ * BG1 -> 0000003F (Dest pitch)
+ * BG2 -> 00000000 (X1, Y1) = (0, 0)
+ * BG3 -> 00040001 (X2, Y2) = (1, 4)
+ * BG4 -> scratch
+ * BG5 -> scratch
+ * BG6-12 -> 00000000
+ * BG13 -> 20004004 (Surf. Width= 2,Surf. Height = 5 )
+ * BG14 -> 00000010 (Qpitch = 4)
+ * BG15 -> 00000000
+ */
+ *cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2);
+ *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f;
+ *cs++ = 0;
+ *cs++ = 4 << 16 | 1;
+ *cs++ = lower_32_bits(i915_vma_offset(ce->vm->rsvd));
+ *cs++ = upper_32_bits(i915_vma_offset(ce->vm->rsvd));
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0x20004004;
+ *cs++ = 0x10;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *
+xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs)
+{
+ /* Wa_16018031267, Wa_16018063123 */
+ if (NEEDS_FASTCOLOR_BLT_WABB(ce->engine))
+ cs = xehp_emit_fastcolor_blt_wabb(ce, cs);
+
+ return cs;
+}
+
+static void
+setup_per_ctx_bb(const struct intel_context *ce,
+ const struct intel_engine_cs *engine,
+ u32 *(*emit)(const struct intel_context *, u32 *))
+{
+ /* Place PER_CTX_BB on next page after INDIRECT_CTX */
+ u32 * const start = context_wabb(ce, true);
+ u32 *cs;
+
+ cs = emit(ce, start);
+
+ /* PER_CTX_BB must manually terminate */
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));
+ lrc_setup_bb_per_ctx(ce->lrc_reg_state, engine,
+ lrc_indirect_bb(ce) + PAGE_SIZE);
+}
+
static void
setup_indirect_ctx_bb(const struct intel_context *ce,
const struct intel_engine_cs *engine,
u32 *(*emit)(const struct intel_context *, u32 *))
{
- u32 * const start = context_indirect_bb(ce);
+ u32 * const start = context_wabb(ce, false);
u32 *cs;
cs = emit(ce, start);
@@ -1511,6 +1604,7 @@ u32 lrc_update_regs(const struct intel_context *ce,
/* Mutually exclusive wrt to global indirect bb */
GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);
setup_indirect_ctx_bb(ce, engine, fn);
+ setup_per_ctx_bb(ce, engine, xehp_emit_per_ctx_bb);
}
return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
@ 2023-10-24 11:37 ` Andi Shyti
0 siblings, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-10-24 11:37 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx, Jonathan Cavitt, Nirmoy Das
Hi Andrzej,
On Mon, Oct 23, 2023 at 10:21:46PM +0200, Andrzej Hajda wrote:
> Apply WABB blit for Wa_16018031267 / Wa_16018063123.
>
> v3: drop unused enum definition
> v4: move selftest to separate patch, use wa only on BCS0.
>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Two little not binding notes below.
...
> -static u32 *context_indirect_bb(const struct intel_context *ce)
> +/*
> + * per_ctx below determines which WABB section is used.
> + * When true, the function returns the location of the
> + * PER_CTX_BB. When false, the function returns the
> + * location of the INDIRECT_CTX.
> + */
> +static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
> {
> void *ptr;
>
> @@ -1029,6 +1047,7 @@ static u32 *context_indirect_bb(const struct intel_context *ce)
> ptr = ce->lrc_reg_state;
> ptr -= LRC_STATE_OFFSET; /* back to start of context image */
> ptr += context_wa_bb_offset(ce);
> + ptr += per_ctx ? PAGE_SIZE : 0;
I'm not a big fan of bools here... I'd rather add as parameter
an offset value and just do:
ptr += offset;
Your choice, not strong on this.
>
> return ptr;
> }
> @@ -1105,7 +1124,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>
> if (GRAPHICS_VER(engine->i915) >= 12) {
> ce->wa_bb_page = context_size / PAGE_SIZE;
> - context_size += PAGE_SIZE;
> + /* INDIRECT_CTX and PER_CTX_BB need separate pages. */
> + context_size += PAGE_SIZE * 2;
> }
>
> if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
> @@ -1407,12 +1427,85 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)
> return gen12_emit_aux_table_inv(ce->engine, cs);
> }
>
> +static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)
> +{
> + struct intel_gt *gt = ce->engine->gt;
> + int mocs = gt->mocs.uc_index << 1;
> +
> + /**
> + * Wa_16018031267 / Wa_16018063123 requires that SW forces the
> + * main copy engine arbitration into round robin mode. We
> + * additionally need to submit the following WABB blt command
> + * to produce 4 subblits with each subblit generating 0 byte
> + * write requests as WABB:
> + *
> + * XY_FASTCOLOR_BLT
> + * BG0 -> 5100000E
> + * BG1 -> 0000003F (Dest pitch)
> + * BG2 -> 00000000 (X1, Y1) = (0, 0)
> + * BG3 -> 00040001 (X2, Y2) = (1, 4)
> + * BG4 -> scratch
> + * BG5 -> scratch
> + * BG6-12 -> 00000000
> + * BG13 -> 20004004 (Surf. Width= 2,Surf. Height = 5 )
> + * BG14 -> 00000010 (Qpitch = 4)
> + * BG15 -> 00000000
> + */
> + *cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2);
> + *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f;
> + *cs++ = 0;
> + *cs++ = 4 << 16 | 1;
> + *cs++ = lower_32_bits(i915_vma_offset(ce->vm->rsvd));
> + *cs++ = upper_32_bits(i915_vma_offset(ce->vm->rsvd));
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0x20004004;
> + *cs++ = 0x10;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static u32 *
> +xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs)
> +{
> + /* Wa_16018031267, Wa_16018063123 */
> + if (NEEDS_FASTCOLOR_BLT_WABB(ce->engine))
> + cs = xehp_emit_fastcolor_blt_wabb(ce, cs);
> +
> + return cs;
> +}
Is this function necessary? Can't we just add in
xehp_emit_fastcolor_blt_wabb()
if (!NEEDS_FASTCOLOR_BLT_WABB(ce->engine))
return cs;
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
@ 2023-10-23 20:21 ` Andrzej Hajda
2023-10-24 8:19 ` Nirmoy Das
2023-10-24 11:39 ` Andi Shyti
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (3 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Andrzej Hajda @ 2023-10-23 20:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Jonathan Cavitt, Andrzej Hajda, Nirmoy Das
Test re-uses logic form indirect ctx BB selftest.
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 ++++++++++++++++++++++++----------
1 file changed, 47 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 5f826b6dcf5d6f..e17b8777d21dc9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1555,7 +1555,7 @@ static int live_lrc_isolation(void *arg)
return err;
}
-static int indirect_ctx_submit_req(struct intel_context *ce)
+static int wabb_ctx_submit_req(struct intel_context *ce)
{
struct i915_request *rq;
int err = 0;
@@ -1579,7 +1579,8 @@ static int indirect_ctx_submit_req(struct intel_context *ce)
#define CTX_BB_CANARY_INDEX (CTX_BB_CANARY_OFFSET / sizeof(u32))
static u32 *
-emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
+emit_wabb_ctx_canary(const struct intel_context *ce,
+ u32 *cs, bool per_ctx)
{
*cs++ = MI_STORE_REGISTER_MEM_GEN8 |
MI_SRM_LRM_GLOBAL_GTT |
@@ -1587,26 +1588,43 @@ emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
*cs++ = i915_mmio_reg_offset(RING_START(0));
*cs++ = i915_ggtt_offset(ce->state) +
context_wa_bb_offset(ce) +
- CTX_BB_CANARY_OFFSET;
+ CTX_BB_CANARY_OFFSET +
+ (per_ctx ? PAGE_SIZE : 0);
*cs++ = 0;
return cs;
}
+static u32 *
+emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
+{
+ return emit_wabb_ctx_canary(ce, cs, false);
+}
+
+static u32 *
+emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
+{
+ return emit_wabb_ctx_canary(ce, cs, true);
+}
+
static void
-indirect_ctx_bb_setup(struct intel_context *ce)
+wabb_ctx_setup(struct intel_context *ce, bool per_ctx)
{
- u32 *cs = context_indirect_bb(ce);
+ u32 *cs = context_wabb(ce, per_ctx);
cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d;
- setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary);
+ if (per_ctx)
+ setup_per_ctx_bb(ce, ce->engine, emit_per_ctx_bb_canary);
+ else
+ setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary);
}
-static bool check_ring_start(struct intel_context *ce)
+static bool check_ring_start(struct intel_context *ce, bool per_ctx)
{
const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) -
- LRC_STATE_OFFSET + context_wa_bb_offset(ce);
+ LRC_STATE_OFFSET + context_wa_bb_offset(ce) +
+ (per_ctx ? PAGE_SIZE : 0);
if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START])
return true;
@@ -1618,21 +1636,21 @@ static bool check_ring_start(struct intel_context *ce)
return false;
}
-static int indirect_ctx_bb_check(struct intel_context *ce)
+static int wabb_ctx_check(struct intel_context *ce, bool per_ctx)
{
int err;
- err = indirect_ctx_submit_req(ce);
+ err = wabb_ctx_submit_req(ce);
if (err)
return err;
- if (!check_ring_start(ce))
+ if (!check_ring_start(ce, per_ctx))
return -EINVAL;
return 0;
}
-static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
+static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx)
{
struct intel_context *a, *b;
int err;
@@ -1667,14 +1685,14 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
* As ring start is restored apriori of starting the indirect ctx bb and
* as it will be different for each context, it fits to this purpose.
*/
- indirect_ctx_bb_setup(a);
- indirect_ctx_bb_setup(b);
+ wabb_ctx_setup(a, per_ctx);
+ wabb_ctx_setup(b, per_ctx);
- err = indirect_ctx_bb_check(a);
+ err = wabb_ctx_check(a, per_ctx);
if (err)
goto unpin_b;
- err = indirect_ctx_bb_check(b);
+ err = wabb_ctx_check(b, per_ctx);
unpin_b:
intel_context_unpin(b);
@@ -1688,7 +1706,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
return err;
}
-static int live_lrc_indirect_ctx_bb(void *arg)
+static int lrc_wabb_ctx(void *arg, bool per_ctx)
{
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
@@ -1697,7 +1715,7 @@ static int live_lrc_indirect_ctx_bb(void *arg)
for_each_engine(engine, gt, id) {
intel_engine_pm_get(engine);
- err = __live_lrc_indirect_ctx_bb(engine);
+ err = __lrc_wabb_ctx(engine, per_ctx);
intel_engine_pm_put(engine);
if (igt_flush_test(gt->i915))
@@ -1710,6 +1728,16 @@ static int live_lrc_indirect_ctx_bb(void *arg)
return err;
}
+static int live_lrc_indirect_ctx_bb(void *arg)
+{
+ return lrc_wabb_ctx(arg, false);
+}
+
+static int live_lrc_per_ctx_bb(void *arg)
+{
+ return lrc_wabb_ctx(arg, true);
+}
+
static void garbage_reset(struct intel_engine_cs *engine,
struct i915_request *rq)
{
@@ -1947,6 +1975,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_garbage),
SUBTEST(live_pphwsp_runtime),
SUBTEST(live_lrc_indirect_ctx_bb),
+ SUBTEST(live_lrc_per_ctx_bb),
};
if (!HAS_LOGICAL_RING_CONTEXTS(i915))
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB Andrzej Hajda
@ 2023-10-24 8:19 ` Nirmoy Das
2023-10-24 11:39 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Nirmoy Das @ 2023-10-24 8:19 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Jonathan Cavitt, Nirmoy Das
Hi Andrzej,
On 10/23/2023 10:21 PM, Andrzej Hajda wrote:
> Test re-uses logic form indirect ctx BB selftest.
>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
You can remove above and add my Reviewed-by: Nirmoy Das
<nirmoy.das@intel.com> for this patch.
Co-developed-by should be followed by a signed-off. Same for the
previous patch.
Regards,
Nirmoy
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 ++++++++++++++++++++++++----------
> 1 file changed, 47 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index 5f826b6dcf5d6f..e17b8777d21dc9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -1555,7 +1555,7 @@ static int live_lrc_isolation(void *arg)
> return err;
> }
>
> -static int indirect_ctx_submit_req(struct intel_context *ce)
> +static int wabb_ctx_submit_req(struct intel_context *ce)
> {
> struct i915_request *rq;
> int err = 0;
> @@ -1579,7 +1579,8 @@ static int indirect_ctx_submit_req(struct intel_context *ce)
> #define CTX_BB_CANARY_INDEX (CTX_BB_CANARY_OFFSET / sizeof(u32))
>
> static u32 *
> -emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
> +emit_wabb_ctx_canary(const struct intel_context *ce,
> + u32 *cs, bool per_ctx)
> {
> *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT |
> @@ -1587,26 +1588,43 @@ emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
> *cs++ = i915_mmio_reg_offset(RING_START(0));
> *cs++ = i915_ggtt_offset(ce->state) +
> context_wa_bb_offset(ce) +
> - CTX_BB_CANARY_OFFSET;
> + CTX_BB_CANARY_OFFSET +
> + (per_ctx ? PAGE_SIZE : 0);
> *cs++ = 0;
>
> return cs;
> }
>
> +static u32 *
> +emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
> +{
> + return emit_wabb_ctx_canary(ce, cs, false);
> +}
> +
> +static u32 *
> +emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs)
> +{
> + return emit_wabb_ctx_canary(ce, cs, true);
> +}
> +
> static void
> -indirect_ctx_bb_setup(struct intel_context *ce)
> +wabb_ctx_setup(struct intel_context *ce, bool per_ctx)
> {
> - u32 *cs = context_indirect_bb(ce);
> + u32 *cs = context_wabb(ce, per_ctx);
>
> cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d;
>
> - setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary);
> + if (per_ctx)
> + setup_per_ctx_bb(ce, ce->engine, emit_per_ctx_bb_canary);
> + else
> + setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary);
> }
>
> -static bool check_ring_start(struct intel_context *ce)
> +static bool check_ring_start(struct intel_context *ce, bool per_ctx)
> {
> const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) -
> - LRC_STATE_OFFSET + context_wa_bb_offset(ce);
> + LRC_STATE_OFFSET + context_wa_bb_offset(ce) +
> + (per_ctx ? PAGE_SIZE : 0);
>
> if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START])
> return true;
> @@ -1618,21 +1636,21 @@ static bool check_ring_start(struct intel_context *ce)
> return false;
> }
>
> -static int indirect_ctx_bb_check(struct intel_context *ce)
> +static int wabb_ctx_check(struct intel_context *ce, bool per_ctx)
> {
> int err;
>
> - err = indirect_ctx_submit_req(ce);
> + err = wabb_ctx_submit_req(ce);
> if (err)
> return err;
>
> - if (!check_ring_start(ce))
> + if (!check_ring_start(ce, per_ctx))
> return -EINVAL;
>
> return 0;
> }
>
> -static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> +static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx)
> {
> struct intel_context *a, *b;
> int err;
> @@ -1667,14 +1685,14 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> * As ring start is restored apriori of starting the indirect ctx bb and
> * as it will be different for each context, it fits to this purpose.
> */
> - indirect_ctx_bb_setup(a);
> - indirect_ctx_bb_setup(b);
> + wabb_ctx_setup(a, per_ctx);
> + wabb_ctx_setup(b, per_ctx);
>
> - err = indirect_ctx_bb_check(a);
> + err = wabb_ctx_check(a, per_ctx);
> if (err)
> goto unpin_b;
>
> - err = indirect_ctx_bb_check(b);
> + err = wabb_ctx_check(b, per_ctx);
>
> unpin_b:
> intel_context_unpin(b);
> @@ -1688,7 +1706,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> return err;
> }
>
> -static int live_lrc_indirect_ctx_bb(void *arg)
> +static int lrc_wabb_ctx(void *arg, bool per_ctx)
> {
> struct intel_gt *gt = arg;
> struct intel_engine_cs *engine;
> @@ -1697,7 +1715,7 @@ static int live_lrc_indirect_ctx_bb(void *arg)
>
> for_each_engine(engine, gt, id) {
> intel_engine_pm_get(engine);
> - err = __live_lrc_indirect_ctx_bb(engine);
> + err = __lrc_wabb_ctx(engine, per_ctx);
> intel_engine_pm_put(engine);
>
> if (igt_flush_test(gt->i915))
> @@ -1710,6 +1728,16 @@ static int live_lrc_indirect_ctx_bb(void *arg)
> return err;
> }
>
> +static int live_lrc_indirect_ctx_bb(void *arg)
> +{
> + return lrc_wabb_ctx(arg, false);
> +}
> +
> +static int live_lrc_per_ctx_bb(void *arg)
> +{
> + return lrc_wabb_ctx(arg, true);
> +}
> +
> static void garbage_reset(struct intel_engine_cs *engine,
> struct i915_request *rq)
> {
> @@ -1947,6 +1975,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
> SUBTEST(live_lrc_garbage),
> SUBTEST(live_pphwsp_runtime),
> SUBTEST(live_lrc_indirect_ctx_bb),
> + SUBTEST(live_lrc_per_ctx_bb),
> };
>
> if (!HAS_LOGICAL_RING_CONTEXTS(i915))
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB Andrzej Hajda
2023-10-24 8:19 ` Nirmoy Das
@ 2023-10-24 11:39 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-10-24 11:39 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx, Jonathan Cavitt, Nirmoy Das
Hi Andrzej,
On Mon, Oct 23, 2023 at 10:21:47PM +0200, Andrzej Hajda wrote:
> Test re-uses logic form indirect ctx BB selftest.
>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (2 preceding siblings ...)
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/gt: add selftest to exercise WABB Andrzej Hajda
@ 2023-10-23 20:21 ` Andrzej Hajda
2023-10-24 8:16 ` Nirmoy Das
2023-10-24 11:41 ` Andi Shyti
2023-10-24 19:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork
` (2 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Andrzej Hajda @ 2023-10-23 20:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Jonathan Cavitt, Andrzej Hajda, Nirmoy Das
From: Jonathan Cavitt <jonathan.cavitt@intel.com>
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index b8618ee3e3041a..c0c8c12edea104 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -124,6 +124,9 @@
#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11)
+#define XEHP_BLITTER_ROUND_ROBIN_MODE \
+ REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)
#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
#define ECO_GATING_CX_ONLY REG_BIT(3)
#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 192ac0e59afa13..108d9326735910 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2782,6 +2782,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
RING_SEMA_WAIT_POLL(engine->mmio_base),
1);
}
+ /* Wa_16018031267, Wa_16018063123 */
+ if (NEEDS_FASTCOLOR_BLT_WABB(engine))
+ wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
+ XEHP_BLITTER_SCHEDULING_MODE_MASK,
+ XEHP_BLITTER_ROUND_ROBIN_MODE);
}
static void
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
@ 2023-10-24 8:16 ` Nirmoy Das
2023-10-24 11:41 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Nirmoy Das @ 2023-10-24 8:16 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Jonathan Cavitt, Nirmoy Das
On 10/23/2023 10:21 PM, Andrzej Hajda wrote:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Set copy engine arbitration into round robin mode
> for part of Wa_16018031267 / Wa_16018063123 mitigation.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> index b8618ee3e3041a..c0c8c12edea104 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> @@ -124,6 +124,9 @@
> #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
> #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
> #define ECOSKPD(base) _MMIO((base) + 0x1d0)
> +#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11)
> +#define XEHP_BLITTER_ROUND_ROBIN_MODE \
> + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)
> #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> #define ECO_GATING_CX_ONLY REG_BIT(3)
> #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 192ac0e59afa13..108d9326735910 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2782,6 +2782,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> RING_SEMA_WAIT_POLL(engine->mmio_base),
> 1);
> }
> + /* Wa_16018031267, Wa_16018063123 */
> + if (NEEDS_FASTCOLOR_BLT_WABB(engine))
> + wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
> + XEHP_BLITTER_SCHEDULING_MODE_MASK,
> + XEHP_BLITTER_ROUND_ROBIN_MODE);
> }
>
> static void
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-24 8:16 ` Nirmoy Das
@ 2023-10-24 11:41 ` Andi Shyti
1 sibling, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-10-24 11:41 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx, Jonathan Cavitt, Nirmoy Das
Hi Andrzej,
On Mon, Oct 23, 2023 at 10:21:48PM +0200, Andrzej Hajda wrote:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Set copy engine arbitration into round robin mode
> for part of Wa_16018031267 / Wa_16018063123 mitigation.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (3 preceding siblings ...)
2023-10-23 20:21 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
@ 2023-10-24 19:48 ` Patchwork
2023-10-24 19:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-24 20:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-10-24 19:48 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/125474/
State : warning
== Summary ==
Error: dim checkpatch failed
b452e380d134 drm/i915: Reserve some kernel space per vm
6e92436440f6 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
-:11: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by Signed-off-by:
#11:
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-:12: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match
#12:
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:85:
+#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
+ IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \
+ engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
-:40: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'engine' may be better as '(engine)' to avoid precedence issues
#40: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:85:
+#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
+ IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \
+ engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
-:60: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#60: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836:
+ GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
-:175: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#175: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1498:
+ GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));
total: 0 errors, 4 warnings, 2 checks, 160 lines checked
70ab11ffb280 drm/i915/gt: add selftest to exercise WABB
-:8: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by Signed-off-by:
#8:
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-:9: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match
#9:
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
total: 0 errors, 2 warnings, 0 checks, 148 lines checked
c975fe64e42c drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
^ permalink raw reply [flat|nested] 15+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (4 preceding siblings ...)
2023-10-24 19:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork
@ 2023-10-24 19:48 ` Patchwork
2023-10-24 20:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-10-24 19:48 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/125474/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 15+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123
2023-10-23 20:21 [Intel-gfx] [PATCH v4 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
` (5 preceding siblings ...)
2023-10-24 19:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-10-24 20:06 ` Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-10-24 20:06 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11484 bytes --]
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/125474/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13781 -> Patchwork_125474v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_125474v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125474v1, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/index.html
Participating hosts (36 -> 38)
------------------------------
Additional (4): bat-dg2-8 bat-dg2-9 bat-adlp-9 fi-hsw-4770
Missing (2): fi-snb-2520m bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125474v1:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_create@basic-files:
- bat-dg2-11: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-11/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-11/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_fence@basic-busy@bcs0:
- bat-mtlp-8: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-mtlp-8/igt@gem_exec_fence@basic-busy@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-mtlp-8/igt@gem_exec_fence@basic-busy@bcs0.html
- bat-atsm-1: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-atsm-1/igt@gem_exec_fence@basic-busy@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-atsm-1/igt@gem_exec_fence@basic-busy@bcs0.html
- bat-dg2-8: NOTRUN -> [ABORT][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-8/igt@gem_exec_fence@basic-busy@bcs0.html
- bat-mtlp-6: [PASS][8] -> [ABORT][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-mtlp-6/igt@gem_exec_fence@basic-busy@bcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-mtlp-6/igt@gem_exec_fence@basic-busy@bcs0.html
- bat-dg2-9: NOTRUN -> [ABORT][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-9/igt@gem_exec_fence@basic-busy@bcs0.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_create@basic-files:
- {bat-dg2-14}: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-14/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-14/igt@gem_ctx_create@basic-files.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
Known issues
------------
Here are the changes found in Patchwork_125474v1 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-hsw-4770: NOTRUN -> [FAIL][15] ([i915#8293])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/fi-hsw-4770/boot.html
#### Possible fixes ####
* boot:
- bat-adlp-11: [FAIL][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-adlp-11/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adlp-9: NOTRUN -> [SKIP][18] ([i915#9318])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@debugfs_test@basic-hwmon.html
- bat-adlp-11: NOTRUN -> [SKIP][19] ([i915#9318])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-9: NOTRUN -> [SKIP][20] ([i915#4613]) +3 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-9: NOTRUN -> [SKIP][21] ([i915#3282])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@gem_tiled_pread_basic.html
- bat-adlp-11: NOTRUN -> [SKIP][22] ([i915#3282])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-9: NOTRUN -> [SKIP][23] ([i915#6621])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@i915_pm_rps@basic-api.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-adlp-9: NOTRUN -> [SKIP][24] ([i915#4103] / [i915#5608]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-11: NOTRUN -> [SKIP][25] ([i915#4103] / [i915#5608]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adlp-11: NOTRUN -> [SKIP][26] ([i915#3555] / [i915#3840])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_dsc@dsc-basic.html
- bat-adlp-9: NOTRUN -> [SKIP][27] ([i915#3555] / [i915#3840])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-modeset@a-dp5:
- bat-adlp-11: NOTRUN -> [DMESG-FAIL][28] ([i915#6868])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-modeset@a-dp5.html
* igt@kms_flip@basic-flip-vs-modeset@b-dp5:
- bat-adlp-11: NOTRUN -> [FAIL][29] ([i915#6121]) +2 other tests fail
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-modeset@b-dp5.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlp-11: NOTRUN -> [SKIP][30] ([i915#3637])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-9: NOTRUN -> [SKIP][31] ([fdo#109285])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-11: NOTRUN -> [SKIP][32] ([i915#4093]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-adlp-11: NOTRUN -> [SKIP][33] ([i915#4369])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][34] ([i915#1845])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlm-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- bat-adlp-9: NOTRUN -> [SKIP][35] ([i915#1072]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-9: NOTRUN -> [SKIP][36] ([i915#3555])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-9: NOTRUN -> [SKIP][37] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-adlm-1: [ABORT][38] -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-adlm-1/igt@i915_selftest@live@hangcheck.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlm-1/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* Linux: CI_DRM_13781 -> Patchwork_125474v1
CI-20190529: 20190529
CI_DRM_13781: a983c752eb74b4af7f72fe09008a1169d315a77f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125474v1: a983c752eb74b4af7f72fe09008a1169d315a77f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4fb96643784a drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
afdc0cd20e50 drm/i915/gt: add selftest to exercise WABB
3b8ea97ac718 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
75dfbc2223cd drm/i915: Reserve some kernel space per vm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/index.html
[-- Attachment #2: Type: text/html, Size: 13214 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread