[PATCH v2 00/10] CMTG enablement

[PATCH v2 00/10] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added LNL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (8):
  drm/i915/cmtg: enable cmtg LNL onwards
  drm/i915/cmtg: cmtg set clock select
  drm/i915/cmtg: set timings for cmtg
  drm/i915/cmtg: program vrr registers of cmtg
  drm/i915/cmtg: program set context latency of cmtg
  drm/i915/cmtg: set transcoder mn for cmtg
  drm/i915/cmtg: program sync to port for cmtg
  drm/i915/cmtg: enable cmtg ctl

Dibin Moolakadan Subrahmanian (2):
  drm/i915/cmtg: enable cmtg in secondary mode
  drm/i915/cmtg: disable CMTG on transcoder disable

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 140 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |   4 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  22 +++
 drivers/gpu/drm/i915/display/intel_crt.c      |   1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  52 ++++---
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   4 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   9 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      |   4 +
 10 files changed, 225 insertions(+), 23 deletions(-)

-- 
2.29.0

[PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards

[Animesh Manna]

Introduce a flag for cmtg. LNL onwards CMTG support will be added.
Set the flag as per DISPLAY_VER() check.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
 drivers/gpu/drm/i915/display/intel_dp.c            | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e6298279dc89..1081615a14fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1569,6 +1569,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enable;
+	} cmtg;
 };
 
 struct intel_plane_error {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e2fd01d1a1e4..ecf8ed0c0265 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	const struct drm_display_mode *fixed_mode;
 	struct intel_connector *connector = intel_dp->attached_connector;
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	int ret = 0, link_bpp_x16;
 
 	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
@@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
+	if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
+		crtc->cmtg.enable = true;
+
 	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
 							pipe_config);
 }
-- 
2.29.0

[PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select

[Animesh Manna]

Program CMTG Clk Select.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  9 ++++++--
 5 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..f5364f5a848f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +186,24 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	}
+
+	if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..bef2426b2787 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -7,7 +7,9 @@
 #define __INTEL_CMTG_H__
 
 struct intel_display;
+struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..8a767b659a23 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6a471c021c0e..a88f013e472b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_display_regs.h"
@@ -3417,9 +3418,13 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+	if (crtc->cmtg.enable)
+		intel_cmtg_set_clk_select(crtc_state);
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 04f63bdd0b87..f6c45bf9d0f3 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_reg.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -2246,11 +2247,15 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
+	} else {
 		intel_lt_phy_pll_enable(encoder, crtc_state);
+		if (crtc->cmtg.enable)
+			intel_cmtg_set_clk_select(crtc_state);
+	}
 }
 
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
-- 
2.29.0

[PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg

[Animesh Manna]

Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++
 drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++++++-------
 .../drm/i915/display/intel_display_types.h    |  2 +
 5 files changed, 67 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f5364f5a848f..4220eeece07f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc->cmtg.htotal);
+	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc->cmtg.hblank);
+	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc->cmtg.hsync);
+	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
+	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
+	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
+}
+
+void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
+{
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
+		return;
+
+	intel_cmtg_set_timings(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index bef2426b2787..b2bb60d160fa 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -9,6 +9,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 8a767b659a23..eb24827d22f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -20,4 +20,11 @@
 #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
 #define  CMTG_ENABLE			REG_BIT(31)
 
+#define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) * 0x100)
+#define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) * 0x100)
+#define TRANS_HSYNC_CMTG(id)		_MMIO(0x6F008 + (id) * 0x100)
+#define TRANS_VTOTAL_CMTG(id)		_MMIO(0x6F00C + (id) * 0x100)
+#define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) * 0x100)
+#define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) * 0x100)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 564d11925af3..976af9eb3c3a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -62,6 +62,7 @@
 #include "intel_casf.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 			intel_crtc_wait_for_next_vblank(wa_crtc);
 		}
 	}
+
+	if (crtc->cmtg.enable)
+		intel_cmtg_enable(new_crtc_state);
 }
 
 static void ilk_crtc_disable(struct intel_atomic_state *state,
@@ -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
 	int vsyncshift = 0;
+	u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
+	u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
 
 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
 
@@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
 			       vsyncshift);
 
-	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
-		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
-		       HTOTAL(adjusted_mode->crtc_htotal - 1));
-	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
-		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
-		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
-	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
-		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
-		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+	trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+			   HTOTAL(adjusted_mode->crtc_htotal - 1);
+	trans_hblank_val = HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+			   HBLANK_END(adjusted_mode->crtc_hblank_end - 1);
+	trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+			  HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
+	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), trans_htotal_val);
+	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), trans_hblank_val);
+	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), trans_hsync_val);
 
 	/*
 	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
@@ -2721,15 +2727,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	if (intel_vrr_always_use_vrr_tg(display))
 		crtc_vtotal = 1;
 
-	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
-		       VACTIVE(crtc_vdisplay - 1) |
-		       VTOTAL(crtc_vtotal - 1));
-	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
-		       VBLANK_START(crtc_vblank_start - 1) |
-		       VBLANK_END(crtc_vblank_end - 1));
-	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
-		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
-		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+	trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
+			   VTOTAL(crtc_vtotal - 1);
+	trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
+			   VBLANK_END(crtc_vblank_end - 1);
+	trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+			  VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
+	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), trans_vtotal_val);
+	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), trans_vblank_val);
+	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), trans_vsync_val);
 
 	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
 	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
@@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	if (crtc->cmtg.enable) {
+		crtc->cmtg.htotal = trans_htotal_val;
+		crtc->cmtg.hblank = trans_hblank_val;
+		crtc->cmtg.hsync = trans_hsync_val;
+		crtc->cmtg.vtotal = trans_vtotal_val;
+		crtc->cmtg.vblank = trans_vblank_val;
+		crtc->cmtg.vsync = trans_vsync_val;
+	}
 }
 
 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1081615a14fb..defb54dd0bbe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1572,6 +1572,8 @@ struct intel_crtc {
 
 	struct {
 		bool enable;
+		u32 htotal, hblank, hsync;
+		u32 vtotal, vblank, vsync;
 	} cmtg;
 };
 
-- 
2.29.0

[PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg

[Animesh Manna]

Enable vrr if it is enabled on cmtg registers.

v2: Use sw state instead of reading from hardware. [Jani]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c          | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h     |  5 +++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c           |  4 ++++
 4 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 4220eeece07f..26adf70cdd00 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -17,6 +17,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -220,6 +221,17 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
 	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
 	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
+
+	if (intel_vrr_possible(crtc_state) && intel_vrr_always_use_vrr_tg(display)) {
+		intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder),
+			       crtc_state->vrr.vmin - 1);
+		intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder),
+			       crtc_state->vrr.vmax - 1);
+		intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder),
+			       crtc_state->vrr.flipline - 1);
+		intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
+			       crtc->cmtg.vrr_ctl);
+	}
 }
 
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index eb24827d22f5..eab90415d0da 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -27,4 +27,9 @@
 #define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) * 0x100)
 #define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) * 0x100)
 
+#define TRANS_VRR_CTL_CMTG(id)		_MMIO(0x6F420 + (id) * 0x100)
+#define TRANS_VRR_VMAX_CMTG(id)		_MMIO(0x6F424 + (id) * 0x100)
+#define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) * 0x100)
+#define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) * 0x100)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index defb54dd0bbe..a87f3ec10aea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1574,6 +1574,7 @@ struct intel_crtc {
 		bool enable;
 		u32 htotal, hblank, hsync;
 		u32 vtotal, vblank, vsync;
+		u32 vrr_ctl;
 	} cmtg;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9d814cc2d608..2c1ae685400f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -892,6 +892,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	u32 vrr_ctl;
 
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
@@ -907,6 +908,9 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	if (cmrr_enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
+	if (crtc->cmtg.enable)
+		crtc->cmtg.vrr_ctl = vrr_ctl;
+
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
-- 
2.29.0

[PATCH v2 05/10] drm/i915/cmtg: program set context latency of cmtg

[Animesh Manna]

Program context latency for delayed vblank timings to create window2.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 4 ++++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 26adf70cdd00..cb1376f4c13f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -236,10 +236,14 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
 
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
 		return;
 
 	intel_cmtg_set_timings(crtc_state);
+
+	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
+		       intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index eab90415d0da..3cfd8eedb321 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,4 +32,6 @@
 #define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) * 0x100)
 #define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) * 0x100)
 
+#define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * 0x100)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg

[Animesh Manna]

Program CMTG link M/N.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index cb1376f4c13f..12a081dd7e4d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -234,6 +234,16 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
+
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -246,4 +256,6 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
 		       intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
+
+	intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 3cfd8eedb321..b766ded8686c 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,6 +32,9 @@
 #define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) * 0x100)
 #define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) * 0x100)
 
+#define TRANS_LINKM1_CMTG(id)          _MMIO(0x6F040 + (id) * 0x100)
+#define TRANS_LINKN1_CMTG(id)          _MMIO(0x6F044 + (id) * 0x100)
+
 #define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * 0x100)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg

[Animesh Manna]

Program Cmtg Sync to Port Sync. Set before enabling the timing generator.
While cmtg start running this bit will be cleared.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 3 +++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 12a081dd7e4d..3af4aefc760e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -258,4 +258,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 		       intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
 
 	intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
+
+	/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b766ded8686c..0ed767a797c0 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -18,7 +18,9 @@
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
 #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define TRANS_CMTG_CTL(id)		_MMIO(0x6fa88 + (id) * 0x100)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) * 0x100)
 #define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) * 0x100)
-- 
2.29.0

[PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl

[Animesh Manna]

Enable CMTG through control register.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 3af4aefc760e..f7364c7408d5 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -244,6 +244,19 @@ static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
 	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
 }
 
+static void intel_cmtg_ctl_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val = 0;
+
+	val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
+
+	val |= CMTG_ENABLE;
+
+	intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);
+}
+
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 
 	/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
 	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
+
+	/* Program Enable Cmtg */
+	intel_cmtg_ctl_enable(crtc_state);
 }
-- 
2.29.0

[PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence
and then enable secondary mode for cmtg.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f7364c7408d5..d1ec9b79cef2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 
 	/* Program Enable Cmtg */
 	intel_cmtg_ctl_enable(crtc_state);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n", cpu_transcoder);
+		return;
+	}
+
+	/*
+	 *  eDP transcoder registers as secondary to CMTG by setting
+	 *  TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].
+	 */
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+	drm_dbg_kms(display->drm, "CMTG:%d enabled\n", cpu_transcoder);
 }
-- 
2.29.0

[PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Add intel_cmtg_disable() to disable CMTG when the transcoder is disabled.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 33 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 5 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index d1ec9b79cef2..844e01b6fc9f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -18,6 +18,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -126,8 +127,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -158,6 +159,32 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
+		return;
+
+	val = intel_de_read(display, TRANS_VRR_CTL_CMTG(cpu_transcoder));
+	val &= ~VRR_CTL_VRR_ENABLE;
+	val &= ~VRR_CTL_FLIP_LINE_EN;
+	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     PORT_SYNC_MODE_ENABLE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG:%d disable timeout\n", cpu_transcoder);
+		return;
+	}
+
+	drm_dbg_kms(display->drm, "CMTG:%d disabled\n", cpu_transcoder);
+}
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -185,7 +212,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index b2bb60d160fa..4f70577be136 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -10,6 +10,7 @@ struct intel_display;
 struct intel_crtc_state;
 
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 0ed767a797c0..f11d5514c376 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -21,6 +21,7 @@
 #define TRANS_CMTG_CTL(id)		_MMIO(0x6fa88 + (id) * 0x100)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) * 0x100)
 #define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) * 0x100)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index b71a8d97cdbb..37a6a139f67b 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -35,6 +35,7 @@
 #include <drm/drm_probe_helper.h>
 #include <video/vga.h>
 
+#include "intel_cmtg.h"
 #include "intel_connector.h"
 #include "intel_crt.h"
 #include "intel_crt_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 976af9eb3c3a..622f9b690342 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1773,6 +1773,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	int i;
 
+	intel_cmtg_disable(old_crtc_state);
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
-- 
2.29.0

✗ i915.CI.BAT: failure for CMTG enablement (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11240 bytes --]

== Series Details ==

Series: CMTG enablement (rev2)
URL   : https://patchwork.freedesktop.org/series/157664/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17925 -> Patchwork_157664v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157664v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157664v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/index.html

Participating hosts (43 -> 41)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157664v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-adlp-6:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-adlp-6/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-adlp-6/igt@i915_module_load@load.html
    - bat-dg1-7:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-dg1-7/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-dg1-7/igt@i915_module_load@load.html
    - fi-glk-j4005:       [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-glk-j4005/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-glk-j4005/igt@i915_module_load@load.html
    - bat-adlp-9:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-adlp-9/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-adlp-9/igt@i915_module_load@load.html
    - bat-twl-2:          [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-twl-2/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-twl-2/igt@i915_module_load@load.html
    - bat-rpls-4:         [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-rpls-4/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-rpls-4/igt@i915_module_load@load.html
    - fi-kbl-7567u:       [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-kbl-7567u/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-kbl-7567u/igt@i915_module_load@load.html
    - fi-cfl-8700k:       [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-cfl-8700k/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-cfl-8700k/igt@i915_module_load@load.html
    - bat-twl-1:          [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-twl-1/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-twl-1/igt@i915_module_load@load.html
    - bat-jsl-5:          [PASS][19] -> [ABORT][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-jsl-5/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-jsl-5/igt@i915_module_load@load.html
    - bat-apl-1:          [PASS][21] -> [ABORT][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-apl-1/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-apl-1/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][23] -> [ABORT][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-dg2-14/igt@i915_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-dg2-14/igt@i915_module_load@load.html
    - fi-tgl-1115g4:      [PASS][25] -> [ABORT][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-tgl-1115g4/igt@i915_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-tgl-1115g4/igt@i915_module_load@load.html
    - fi-cfl-guc:         [PASS][27] -> [ABORT][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-cfl-guc/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-cfl-guc/igt@i915_module_load@load.html
    - bat-dg2-9:          [PASS][29] -> [ABORT][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-dg2-9/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-dg2-9/igt@i915_module_load@load.html
    - fi-hsw-4770:        [PASS][31] -> [ABORT][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-hsw-4770/igt@i915_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-hsw-4770/igt@i915_module_load@load.html
    - fi-cfl-8109u:       [PASS][33] -> [ABORT][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-cfl-8109u/igt@i915_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-cfl-8109u/igt@i915_module_load@load.html
    - bat-dg2-8:          [PASS][35] -> [ABORT][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-dg2-8/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-dg2-8/igt@i915_module_load@load.html
    - bat-adls-6:         [PASS][37] -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-adls-6/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-adls-6/igt@i915_module_load@load.html

  * igt@kms_busy@basic@flip:
    - bat-rplp-1:         [PASS][39] -> [ABORT][40] +1 other test abort
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-rplp-1/igt@kms_busy@basic@flip.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-rplp-1/igt@kms_busy@basic@flip.html

  * igt@kms_busy@basic@modeset:
    - bat-rplp-1:         [PASS][41] -> [DMESG-WARN][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-rplp-1/igt@kms_busy@basic@modeset.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-rplp-1/igt@kms_busy@basic@modeset.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-mtlp-9:         [PASS][43] -> [ABORT][44] +1 other test abort
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@basic-flip-vs-dpms@b-dp3:
    - bat-arls-5:         [PASS][45] -> [ABORT][46] +1 other test abort
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-arls-5/igt@kms_flip@basic-flip-vs-dpms@b-dp3.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-arls-5/igt@kms_flip@basic-flip-vs-dpms@b-dp3.html

  * igt@kms_flip@basic-flip-vs-dpms@b-edp1:
    - bat-mtlp-8:         [PASS][47] -> [ABORT][48] +1 other test abort
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-mtlp-8/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-mtlp-8/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html
    - bat-arlh-3:         [PASS][49] -> [ABORT][50] +1 other test abort
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-arlh-3/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-arlh-3/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html

  * igt@kms_flip@basic-flip-vs-dpms@b-hdmi-a2:
    - bat-arls-6:         [PASS][51] -> [ABORT][52] +1 other test abort
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-arls-6/igt@kms_flip@basic-flip-vs-dpms@b-hdmi-a2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-arls-6/igt@kms_flip@basic-flip-vs-dpms@b-hdmi-a2.html

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-kbl-2:          [PASS][53] -> [ABORT][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-kbl-2/igt@kms_force_connector_basic@force-connector-state.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-kbl-2/igt@kms_force_connector_basic@force-connector-state.html
    - fi-rkl-11600:       [PASS][55] -> [ABORT][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-rkl-11600/igt@kms_force_connector_basic@force-connector-state.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-rkl-11600/igt@kms_force_connector_basic@force-connector-state.html
    - fi-kbl-x1275:       [PASS][57] -> [ABORT][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
    - bat-dg1-6:          [PASS][59] -> [ABORT][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-dg1-6/igt@kms_force_connector_basic@force-connector-state.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-dg1-6/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       [PASS][61] -> [ABORT][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-jsl-1:          [PASS][63] -> [ABORT][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/bat-jsl-1/igt@kms_hdmi_inject@inject-audio.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/bat-jsl-1/igt@kms_hdmi_inject@inject-audio.html
    - fi-skl-6600u:       [PASS][65] -> [ABORT][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17925/fi-skl-6600u/igt@kms_hdmi_inject@inject-audio.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/fi-skl-6600u/igt@kms_hdmi_inject@inject-audio.html

  


Build changes
-------------

  * Linux: CI_DRM_17925 -> Patchwork_157664v2

  CI-20190529: 20190529
  CI_DRM_17925: 9f5242e63f0bab74d47ae6792e0c25a324184a6b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8730: 8730
  Patchwork_157664v2: 9f5242e63f0bab74d47ae6792e0c25a324184a6b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v2/index.html

[-- Attachment #2: Type: text/html, Size: 12209 bytes --]

RE: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards

[Kandpal, Suraj]

> Subject: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
> 
> Introduce a flag for cmtg. LNL onwards CMTG support will be added.
> Set the flag as per DISPLAY_VER() check.
> 

Use Capitalized versions of acronyms unless unavoidable(if you mention it as a part of a function)
both in commit subject and message, this review stands for all patch in series it should be *CMTG

Also please Bspec references to registers, sequences on all patches this makes life very easy to review
This is also a review for all the patches in the series

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
>  drivers/gpu/drm/i915/display/intel_dp.c            | 4 ++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e6298279dc89..1081615a14fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1569,6 +1569,10 @@ struct intel_crtc {  #endif
> 
>  	bool vblank_psr_notify;
> +
> +	struct {
> +		bool enable;
> +	} cmtg;
>  };
> 
>  struct intel_plane_error {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e2fd01d1a1e4..ecf8ed0c0265 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	const struct drm_display_mode *fixed_mode;
>  	struct intel_connector *connector = intel_dp->attached_connector;
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	int ret = 0, link_bpp_x16;
> 
>  	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
> @@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config, conn_state);
> 
> +	if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
> +		crtc->cmtg.enable = true;

Should be >= 20 since LNL's version was 20.
Also I don't see a point of having this as a variable in intel_crtc this can be checked as a macro or a function
Maybe you have to use intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) instead on intel_dp_is_edp but it should be better option
According to me.

Regards,
Suraj Kandpal

> +
>  	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp,
> connector,
>  							pipe_config);
>  }
> --
> 2.29.0

RE: [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select

[Kandpal, Suraj]

> Subject: [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select
> 
> Program CMTG Clk Select.
> 

Capitalize the CMTG is commit subject
Add Bspec link for register and sequences you are using

Regards,
Suraj Kandpal

> v2:
> - Correct mask for PHY B. [Jani]
> - Use REG_FIELD_PREP() for enable value. [Dibin]
> - Extend cmtg clock select for xe3plpd. [Dibin]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |  9 ++++++--
>  5 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..f5364f5a848f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_device.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_types.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,24 @@
> void intel_cmtg_sanitize(struct intel_display *display)
> 
>  	intel_cmtg_disable(display, &cmtg_config);  }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 clk_sel_clr = 0;
> +	u32 clk_sel_set = 0;
> +
> +	if (cpu_transcoder == TRANSCODER_A) {
> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> +	}
> +
> +	if (cpu_transcoder == TRANSCODER_B) {
> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> +	}
> +
> +	if (clk_sel_set)
> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..bef2426b2787 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
>  #define __INTEL_CMTG_H__
> 
>  struct intel_display;
> +struct intel_crtc_state;
> 
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..8a767b659a23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
> 
>  #define CMTG_CLK_SEL			_MMIO(0x46160)
>  #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
>  #define CMTG_CLK_SEL_A_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
>  #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
>  #define CMTG_CLK_SEL_B_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> 
>  #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6a471c021c0e..a88f013e472b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -9,6 +9,7 @@
>  #include <drm/drm_print.h>
> 
>  #include "intel_alpm.h"
> +#include "intel_cmtg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_display_regs.h"
> @@ -3417,9 +3418,13 @@ void intel_mtl_pll_enable_clock(struct
> intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> +
> +	if (crtc->cmtg.enable)
> +		intel_cmtg_set_clk_select(crtc_state);
>  }
> 
>  /*
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 04f63bdd0b87..f6c45bf9d0f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -6,6 +6,7 @@
>  #include <drm/drm_print.h>
> 
>  #include "i915_reg.h"
> +#include "intel_cmtg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> @@ -2246,11 +2247,15 @@ void intel_xe3plpd_pll_enable(struct
> intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state)  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 
> -	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> -	else
> +	} else {
>  		intel_lt_phy_pll_enable(encoder, crtc_state);
> +		if (crtc->cmtg.enable)
> +			intel_cmtg_set_clk_select(crtc_state);
> +	}
>  }
> 
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
> --
> 2.29.0

RE: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg

[Kandpal, Suraj]

> Subject: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
> 

* CMTG

> Timing registers are separate for CMTG, read transcoder register and program
> cmtg transcoder with those values.

*CMTG

> 
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]

Why also I don't see this comment from Dibin anywhere
Bspec Links
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++
>  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++++++-------
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  5 files changed, 67 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f5364f5a848f..4220eeece07f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> +
> +static void intel_cmtg_set_timings(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.htotal);
> +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.hblank);
> +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.hsync);
> +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
> +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
> +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> +crtc->cmtg.vsync); }
> +
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> +		return;
> +
> +	intel_cmtg_set_timings(crtc_state);

I don't like the idea of this being called here this belongs at intel_set_transcoder_timings with others
Unless Bspec says otherwise.

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index bef2426b2787..b2bb60d160fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -9,6 +9,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 8a767b659a23..eb24827d22f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,11 @@
>  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
>  #define  CMTG_ENABLE			REG_BIT(31)
> 
> +#define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) *
> 0x100)
> +#define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) *
> 0x100)
> +#define TRANS_HSYNC_CMTG(id)		_MMIO(0x6F008 + (id) *
> 0x100)
> +#define TRANS_VTOTAL_CMTG(id)		_MMIO(0x6F00C + (id) *
> 0x100)
> +#define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) *
> 0x100)
> +#define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) *
> 0x100)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 564d11925af3..976af9eb3c3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -62,6 +62,7 @@
>  #include "intel_casf.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
>  			intel_crtc_wait_for_next_vblank(wa_crtc);
>  		}
>  	}
> +
> +	if (crtc->cmtg.enable)
> +		intel_cmtg_enable(new_crtc_state);

I would rather have you have a separate function which you be the last patch that finally calls intel_cmtg_enable so that you don't enable
a half baked feature in between the patch series. Complete all the parts of your code and join them at last with the intel_cmtg_enable

>  }
> 
>  static void ilk_crtc_disable(struct intel_atomic_state *state, @@ -2654,6
> +2658,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
>  	int vsyncshift = 0;
> +	u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> +	u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
> 
>  	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> 
> @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
>  			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
>  			       vsyncshift);
> 
> -	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> -		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> -		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> -	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> -		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> -		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> -	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> -		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> -		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> +	trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> +			   HTOTAL(adjusted_mode->crtc_htotal - 1);
> +	trans_hblank_val = HBLANK_START(adjusted_mode-
> >crtc_hblank_start - 1) |
> +			   HBLANK_END(adjusted_mode->crtc_hblank_end -
> 1);
> +	trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start -
> 1) |
> +			  HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> +	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> trans_htotal_val);
> +	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> trans_hblank_val);
> +	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> +trans_hsync_val);
> 
>  	/*
>  	 * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal @@ -2721,15 +2727,15 @@ static void
> intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	if (intel_vrr_always_use_vrr_tg(display))
>  		crtc_vtotal = 1;
> 
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> -		       VACTIVE(crtc_vdisplay - 1) |
> -		       VTOTAL(crtc_vtotal - 1));
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> -		       VBLANK_START(crtc_vblank_start - 1) |
> -		       VBLANK_END(crtc_vblank_end - 1));
> -	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> -		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> -		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> +	trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> +			   VTOTAL(crtc_vtotal - 1);
> +	trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> +			   VBLANK_END(crtc_vblank_end - 1);
> +	trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start -
> 1) |
> +			  VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> +	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> trans_vtotal_val);
> +	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> trans_vblank_val);
> +	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> +trans_vsync_val);


Rather than this pass adjusted mode to intel_cmtg_set_timing and do that calculation there

> 
>  	/* Workaround: when the EDP input selection is B, the VTOTAL_B
> must be
>  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This
> is @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
>  		intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	if (crtc->cmtg.enable) {
> +		crtc->cmtg.htotal = trans_htotal_val;
> +		crtc->cmtg.hblank = trans_hblank_val;
> +		crtc->cmtg.hsync = trans_hsync_val;
> +		crtc->cmtg.vtotal = trans_vtotal_val;
> +		crtc->cmtg.vblank = trans_vblank_val;
> +		crtc->cmtg.vsync = trans_vsync_val;
> +	}
>  }

If my above advice is taken this is not needed

> 
>  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1081615a14fb..defb54dd0bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1572,6 +1572,8 @@ struct intel_crtc {
> 
>  	struct {
>  		bool enable;
> +		u32 htotal, hblank, hsync;
> +		u32 vtotal, vblank, vsync;

Again this also wont be needed then

Regards,
Suraj Kandpal

>  	} cmtg;
>  };
> 
> --
> 2.29.0

RE: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards

[Jani Nikula]

On Thu, 05 Feb 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
>> 
>> Introduce a flag for cmtg. LNL onwards CMTG support will be added.
>> Set the flag as per DISPLAY_VER() check.
>> 
>
> Use Capitalized versions of acronyms unless unavoidable(if you mention it as a part of a function)
> both in commit subject and message, this review stands for all patch in series it should be *CMTG
>
> Also please Bspec references to registers, sequences on all patches this makes life very easy to review
> This is also a review for all the patches in the series
>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
>>  drivers/gpu/drm/i915/display/intel_dp.c            | 4 ++++
>>  2 files changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e6298279dc89..1081615a14fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1569,6 +1569,10 @@ struct intel_crtc {  #endif
>> 
>>  	bool vblank_psr_notify;
>> +
>> +	struct {
>> +		bool enable;
>> +	} cmtg;
>>  };
>> 
>>  struct intel_plane_error {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e2fd01d1a1e4..ecf8ed0c0265 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder
>> *encoder,
>>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>  	const struct drm_display_mode *fixed_mode;
>>  	struct intel_connector *connector = intel_dp->attached_connector;
>> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>>  	int ret = 0, link_bpp_x16;
>> 
>>  	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
>> @@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder
>> *encoder,
>>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>>  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
>> pipe_config, conn_state);
>> 
>> +	if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
>> +		crtc->cmtg.enable = true;
>
> Should be >= 20 since LNL's version was 20.
> Also I don't see a point of having this as a variable in intel_crtc this can be checked as a macro or a function

Yeah, compute config should not modify anything but the crtc state.

BR,
Jani.


> Maybe you have to use intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) instead on intel_dp_is_edp but it should be better option
> According to me.
>
> Regards,
> Suraj Kandpal
>
>> +
>>  	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp,
>> connector,
>>  							pipe_config);
>>  }
>> --
>> 2.29.0
>

-- 
Jani Nikula, Intel

Re: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg

[Jani Nikula]

On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Timing registers are separate for CMTG, read transcoder register
> and program cmtg transcoder with those values.
>
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++
>  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++++++-------
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  5 files changed, 67 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f5364f5a848f..4220eeece07f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
>  }
> +
> +static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc->cmtg.htotal);
> +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc->cmtg.hblank);
> +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc->cmtg.hsync);
> +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
> +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
> +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
> +}
> +
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
> +		return;
> +
> +	intel_cmtg_set_timings(crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index bef2426b2787..b2bb60d160fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -9,6 +9,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
>  
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 8a767b659a23..eb24827d22f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,11 @@
>  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  
> +#define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) * 0x100)

What is id? If it's a transcoder, please use trans for the param name.

> +#define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) * 0x100)
> +#define TRANS_HSYNC_CMTG(id)		_MMIO(0x6F008 + (id) * 0x100)
> +#define TRANS_VTOTAL_CMTG(id)		_MMIO(0x6F00C + (id) * 0x100)
> +#define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) * 0x100)
> +#define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) * 0x100)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 564d11925af3..976af9eb3c3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -62,6 +62,7 @@
>  #include "intel_casf.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>  			intel_crtc_wait_for_next_vblank(wa_crtc);
>  		}
>  	}
> +
> +	if (crtc->cmtg.enable)
> +		intel_cmtg_enable(new_crtc_state);
>  }
>  
>  static void ilk_crtc_disable(struct intel_atomic_state *state,
> @@ -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
>  	int vsyncshift = 0;
> +	u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> +	u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
>  
>  	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
>  
> @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
>  			       vsyncshift);
>  
> -	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> -		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> -		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> -	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> -		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> -		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> -	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> -		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> -		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> +	trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> +			   HTOTAL(adjusted_mode->crtc_htotal - 1);
> +	trans_hblank_val = HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> +			   HBLANK_END(adjusted_mode->crtc_hblank_end - 1);
> +	trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> +			  HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> +	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), trans_htotal_val);
> +	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), trans_hblank_val);
> +	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), trans_hsync_val);
>  
>  	/*
>  	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> @@ -2721,15 +2727,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	if (intel_vrr_always_use_vrr_tg(display))
>  		crtc_vtotal = 1;
>  
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> -		       VACTIVE(crtc_vdisplay - 1) |
> -		       VTOTAL(crtc_vtotal - 1));
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> -		       VBLANK_START(crtc_vblank_start - 1) |
> -		       VBLANK_END(crtc_vblank_end - 1));
> -	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> -		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> -		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> +	trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> +			   VTOTAL(crtc_vtotal - 1);
> +	trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> +			   VBLANK_END(crtc_vblank_end - 1);
> +	trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> +			  VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> +	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), trans_vtotal_val);
> +	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), trans_vblank_val);
> +	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), trans_vsync_val);
>  
>  	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
>  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	if (crtc->cmtg.enable) {
> +		crtc->cmtg.htotal = trans_htotal_val;
> +		crtc->cmtg.hblank = trans_hblank_val;
> +		crtc->cmtg.hsync = trans_hsync_val;
> +		crtc->cmtg.vtotal = trans_vtotal_val;
> +		crtc->cmtg.vblank = trans_vblank_val;
> +		crtc->cmtg.vsync = trans_vsync_val;
> +	}
>  }
>  
>  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1081615a14fb..defb54dd0bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1572,6 +1572,8 @@ struct intel_crtc {
>  
>  	struct {
>  		bool enable;
> +		u32 htotal, hblank, hsync;
> +		u32 vtotal, vblank, vsync;

Why are these stored in the crtc?

>  	} cmtg;
>  };

-- 
Jani Nikula, Intel

Re: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl

[Jani Nikula]

On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Enable CMTG through control register.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 3af4aefc760e..f7364c7408d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -244,6 +244,19 @@ static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
>  	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
>  }
>  
> +static void intel_cmtg_ctl_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val = 0;
> +
> +	val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
> +
> +	val |= CMTG_ENABLE;
> +
> +	intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);

This is just a single line intel_de_rmw().

> +}
> +
>  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>  
>  	/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
>  	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> +
> +	/* Program Enable Cmtg */
> +	intel_cmtg_ctl_enable(crtc_state);

If there's intel_de_rmw() before, why is this a function?

>  }

-- 
Jani Nikula, Intel

Re: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode

[Jani Nikula]

On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>
> Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence
> and then enable secondary mode for cmtg.
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f7364c7408d5..d1ec9b79cef2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>  
>  	/* Program Enable Cmtg */
>  	intel_cmtg_ctl_enable(crtc_state);
> +
> +	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
> +				       CMTG_SYNC_TO_PORT, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n", cpu_transcoder);
> +		return;
> +	}

This should be part of the previous patch, right?

> +
> +	/*
> +	 *  eDP transcoder registers as secondary to CMTG by setting
> +	 *  TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].

What does this even mean?

> +	 */
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> +
> +	drm_dbg_kms(display->drm, "CMTG:%d enabled\n", cpu_transcoder);

See transcoder_name().

>  }

-- 
Jani Nikula, Intel

RE: [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg

[Kandpal, Suraj]

> Subject: [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg

* CMTG
* VRR

> 
> Enable vrr if it is enabled on cmtg registers.

*VRR
* CMTG

> 
> v2: Use sw state instead of reading from hardware. [Jani]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c          | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h     |  5 +++++
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  drivers/gpu/drm/i915/display/intel_vrr.c           |  4 ++++
>  4 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 4220eeece07f..26adf70cdd00 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -17,6 +17,7 @@
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> +#include "intel_vrr.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -220,6 +221,17 @@
> static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
>  	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
>  	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
>  	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.vsync);
> +
> +	if (intel_vrr_possible(crtc_state) &&
> intel_vrr_always_use_vrr_tg(display)) {
> +		intel_de_write(display,
> TRANS_VRR_VMIN_CMTG(cpu_transcoder),
> +			       crtc_state->vrr.vmin - 1);
> +		intel_de_write(display,
> TRANS_VRR_VMAX_CMTG(cpu_transcoder),
> +			       crtc_state->vrr.vmax - 1);
> +		intel_de_write(display,
> TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder),
> +			       crtc_state->vrr.flipline - 1);

IMHO These three need to be called from 
intel_vrr_set_fixed_rr_timings() 
you can wrap this up in a function of its own called intel_cmtg_set_fixed_rr_timings()


> +		intel_de_write(display,
> TRANS_VRR_CTL_CMTG(cpu_transcoder),
> +			       crtc->cmtg.vrr_ctl);

This needs to directly be called from intel_vrr_tg_enable
Which also saves you from having you save the variable in intel_crtc
Which shouldn't be there in the first place (maybe in crtc_state if needed but I don't see the real need of having it at all.

Regards,
Suraj Kandpal

> +	}
>  }
> 
>  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index eb24827d22f5..eab90415d0da 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -27,4 +27,9 @@
>  #define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) *
> 0x100)
>  #define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) *
> 0x100)
> 
> +#define TRANS_VRR_CTL_CMTG(id)		_MMIO(0x6F420 + (id) *
> 0x100)
> +#define TRANS_VRR_VMAX_CMTG(id)		_MMIO(0x6F424 + (id) *
> 0x100)
> +#define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) *
> 0x100)
> +#define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) *
> 0x100)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index defb54dd0bbe..a87f3ec10aea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1574,6 +1574,7 @@ struct intel_crtc {
>  		bool enable;
>  		u32 htotal, hblank, hsync;
>  		u32 vtotal, vblank, vsync;
> +		u32 vrr_ctl;
>  	} cmtg;
>  };
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9d814cc2d608..2c1ae685400f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -892,6 +892,7 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	u32 vrr_ctl;
> 
>  	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), @@ -
> 907,6 +908,9 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state
> *crtc_state,
>  	if (cmrr_enable)
>  		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> 
> +	if (crtc->cmtg.enable)
> +		crtc->cmtg.vrr_ctl = vrr_ctl;
> +
>  	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);  }
> 
> --
> 2.29.0

RE: [PATCH v2 05/10] drm/i915/cmtg: program set context latency of cmtg

[Kandpal, Suraj]

> Subject: [PATCH v2 05/10] drm/i915/cmtg: program set context latency of
> cmtg

* CMTG

> 
> Program context latency for delayed vblank timings to create window2.
> 

Bspec link

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c      | 4 ++++
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 26adf70cdd00..cb1376f4c13f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -236,10 +236,14 @@ static void intel_cmtg_set_timings(const struct
> intel_crtc_state *crtc_state)
> 
>  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>  	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
>  		return;
> 
>  	intel_cmtg_set_timings(crtc_state);
> +
> +	intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> +		       intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display,
> +cpu_transcoder)));

So at least three things need to change here:
- We are actively trying to move away from doing inline intel_de_reads like this with arguments passed to function.
- We also try not to read from HW and write back to HW . We need to write our derived S/w value to HW. Readback needs to only
be for verification purpose. We only use H/w read when we are sort of out of options on a viable solution to derive the value at that place.
From what I can see since you are using the exact values that is coded in TRANS_CONTEXT_LATENCY your work can be done by crtc_state->set_context_latency
- This belongs in intel_cmtg_set_timings (which I said before needs to be called from intel_set_transcoder_timings ( Also I think you should rename function to intel_cmtg_set_transcoder_timings))


>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index eab90415d0da..3cfd8eedb321 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,4 +32,6 @@
>  #define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) *
> 0x100)
>  #define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) *
> 0x100)
> 
> +#define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) *
> 0x100)
> +

Usually we call this index instead of id

Regards,
Suraj Kandpal

>  #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0

RE: [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg

[Kandpal, Suraj]

> Subject: [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg

* CMTG

> 
> Program CMTG link M/N.
> 

Bspec link

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c      | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  3 +++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index cb1376f4c13f..12a081dd7e4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -234,6 +234,16 @@ static void intel_cmtg_set_timings(const struct
> intel_crtc_state *crtc_state)
>  	}
>  }
> 
> +static void intel_cpu_cmtg_transcoder_set_m_n(const struct

Should be intel_cmtg_transcoder_set_m_n

Regards,
Suraj Kandpal

> +intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
> +
> +	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n-
> >link_m);
> +	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder),
> +m_n->link_n); }
> +
>  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state); @@ -246,4
> +256,6 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
> 
>  	intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
>  		       intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
> +
> +	intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 3cfd8eedb321..b766ded8686c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,6 +32,9 @@
>  #define TRANS_VRR_VMIN_CMTG(id)		_MMIO(0x6F434 + (id) *
> 0x100)
>  #define TRANS_VRR_FLIPLINE_CMTG(id)	_MMIO(0x6F438 + (id) *
> 0x100)
> 
> +#define TRANS_LINKM1_CMTG(id)          _MMIO(0x6F040 + (id) * 0x100)
> +#define TRANS_LINKN1_CMTG(id)          _MMIO(0x6F044 + (id) * 0x100)
> +
>  #define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) *
> 0x100)
> 
>  #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0

RE: [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Animesh Manna
> Sent: Tuesday, February 3, 2026 7:14 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Manna, Animesh <animesh.manna@intel.com>
> Subject: [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg

* CMTG

> 
> Program Cmtg Sync to Port Sync. Set before enabling the timing generator.
> While cmtg start running this bit will be cleared.

* CMTG
Bspec link

> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c      | 3 +++
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 12a081dd7e4d..3af4aefc760e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -258,4 +258,7 @@ void intel_cmtg_enable(const struct intel_crtc_state
> *crtc_state)
>  		       intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
> 
>  	intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
> +
> +	/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index b766ded8686c..0ed767a797c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -18,7 +18,9 @@
> 
>  #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
>  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> +#define TRANS_CMTG_CTL(id)		_MMIO(0x6fa88 + (id) * 0x100)

What's the point of defining TRANS_CMTG_CTL_A/B if you are not going to use it
Also have a look at how _TRANS_MMIO works
Use that a lot of you register definitions can use that without having to use a formula for
Every def.

Regards,
Suraj Kandpal

>  #define  CMTG_ENABLE			REG_BIT(31)
> +#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> 
>  #define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) *
> 0x100)
>  #define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) *
> 0x100)
> --
> 2.29.0

RE: [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable

[Kandpal, Suraj]

> Subject: [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder
> disable
> 
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> 
> Add intel_cmtg_disable() to disable CMTG when the transcoder is disabled.
> 

Bspec link

Adding comment here unrelated but I see no patches which redout your CMTG state dump it and verify it I think
You need to added those patches as well

Regards,
Suraj Kandpal

> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 33 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  1 +
>  5 files changed, 34 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index d1ec9b79cef2..844e01b6fc9f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -18,6 +18,7 @@
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_vrr.h"
> +#include "intel_vrr_regs.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -126,8 +127,8 @@
> static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
>  	return cmtg_config->trans_a_secondary || cmtg_config-
> >trans_b_secondary;  }
> 
> -static void intel_cmtg_disable(struct intel_display *display,
> -			       struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> +				   struct intel_cmtg_config *cmtg_config)
>  {
>  	u32 clk_sel_clr = 0;
>  	u32 clk_sel_set = 0;
> @@ -158,6 +159,32 @@ static void intel_cmtg_disable(struct intel_display
> *display,
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> 
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> +		return;
> +
> +	val = intel_de_read(display,
> TRANS_VRR_CTL_CMTG(cpu_transcoder));
> +	val &= ~VRR_CTL_VRR_ENABLE;
> +	val &= ~VRR_CTL_FLIP_LINE_EN;
> +	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> +		     PORT_SYNC_MODE_ENABLE, 0);
> +
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);
> +
> +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG:%d disable timeout\n",
> cpu_transcoder);
> +		return;
> +	}
> +
> +	drm_dbg_kms(display->drm, "CMTG:%d disabled\n", cpu_transcoder);
> }
>  /*
>   * Read out CMTG configuration and, on platforms that allow disabling it
> without
>   * a modeset, do it.
> @@ -185,7 +212,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
>  		return;
> 
> -	intel_cmtg_disable(display, &cmtg_config);
> +	intel_cmtg_disable_all(display, &cmtg_config);
>  }
> 
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state) diff -
> -git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index b2bb60d160fa..4f70577be136 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -10,6 +10,7 @@ struct intel_display;
>  struct intel_crtc_state;
> 
>  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 0ed767a797c0..f11d5514c376 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -21,6 +21,7 @@
>  #define TRANS_CMTG_CTL(id)		_MMIO(0x6fa88 + (id) * 0x100)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> +#define  CMTG_STATE			REG_BIT(23)
> 
>  #define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) *
> 0x100)
>  #define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) *
> 0x100)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index b71a8d97cdbb..37a6a139f67b 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -35,6 +35,7 @@
>  #include <drm/drm_probe_helper.h>
>  #include <video/vga.h>
> 
> +#include "intel_cmtg.h"
>  #include "intel_connector.h"
>  #include "intel_crt.h"
>  #include "intel_crt_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 976af9eb3c3a..622f9b690342 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1773,6 +1773,7 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
>  	struct intel_crtc *pipe_crtc;
>  	int i;
> 
> +	intel_cmtg_disable(old_crtc_state);
>  	/*
>  	 * FIXME collapse everything to one hook.
>  	 * Need care with mst->ddi interactions.
> --
> 2.29.0

RE: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:17 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
> 
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Timing registers are separate for CMTG, read transcoder register and
> > program cmtg transcoder with those values.
> >
> > v2:
> > - Use sw state instead of reading directly from hardware. [Jani]
> > - Move set_timing later after encoder enable. [Dibin]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++
> >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
> >  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++
> >  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++++++-------
> >  .../drm/i915/display/intel_display_types.h    |  2 +
> >  5 files changed, 67 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index f5364f5a848f..4220eeece07f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> >  	if (clk_sel_set)
> >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> > +
> > +static void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.htotal);
> > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.hblank);
> > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.hsync);
> > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
> > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
> > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > +crtc->cmtg.vsync); }
> > +
> > +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> > +		return;
> > +
> > +	intel_cmtg_set_timings(crtc_state);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index bef2426b2787..b2bb60d160fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -9,6 +9,7 @@
> >  struct intel_display;
> >  struct intel_crtc_state;
> >
> > +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > *display);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index 8a767b659a23..eb24827d22f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -20,4 +20,11 @@
> >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> >  #define  CMTG_ENABLE			REG_BIT(31)
> >
> > +#define TRANS_HTOTAL_CMTG(id)		_MMIO(0x6F000 + (id) *
> 0x100)
> 
> What is id? If it's a transcoder, please use trans for the param name.

Ok.

> 
> > +#define TRANS_HBLANK_CMTG(id)		_MMIO(0x6F004 + (id) *
> 0x100)
> > +#define TRANS_HSYNC_CMTG(id)		_MMIO(0x6F008 + (id) *
> 0x100)
> > +#define TRANS_VTOTAL_CMTG(id)		_MMIO(0x6F00C + (id) *
> 0x100)
> > +#define TRANS_VBLANK_CMTG(id)		_MMIO(0x6F010 + (id) *
> 0x100)
> > +#define TRANS_VSYNC_CMTG(id)		_MMIO(0x6F014 + (id) *
> 0x100)
> > +
> >  #endif /* __INTEL_CMTG_REGS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 564d11925af3..976af9eb3c3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -62,6 +62,7 @@
> >  #include "intel_casf.h"
> >  #include "intel_cdclk.h"
> >  #include "intel_clock_gating.h"
> > +#include "intel_cmtg.h"
> >  #include "intel_color.h"
> >  #include "intel_crt.h"
> >  #include "intel_crtc.h"
> > @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> >  			intel_crtc_wait_for_next_vblank(wa_crtc);
> >  		}
> >  	}
> > +
> > +	if (crtc->cmtg.enable)
> > +		intel_cmtg_enable(new_crtc_state);
> >  }
> >
> >  static void ilk_crtc_disable(struct intel_atomic_state *state, @@
> > -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> >  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> >  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> >  	int vsyncshift = 0;
> > +	u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> > +	u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
> >
> >  	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> >
> > @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> >  			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
> >  			       vsyncshift);
> >
> > -	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> > -		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > -		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > -	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> > -		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > -		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > -	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> > -		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > -		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > +	trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > +			   HTOTAL(adjusted_mode->crtc_htotal - 1);
> > +	trans_hblank_val = HBLANK_START(adjusted_mode-
> >crtc_hblank_start - 1) |
> > +			   HBLANK_END(adjusted_mode->crtc_hblank_end -
> 1);
> > +	trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start -
> 1) |
> > +			  HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> > +	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> trans_htotal_val);
> > +	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> trans_hblank_val);
> > +	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> > +trans_hsync_val);
> >
> >  	/*
> >  	 * For platforms that always use VRR Timing Generator, the
> > VTOTAL.Vtotal @@ -2721,15 +2727,15 @@ static void
> intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> >  	if (intel_vrr_always_use_vrr_tg(display))
> >  		crtc_vtotal = 1;
> >
> > -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> > -		       VACTIVE(crtc_vdisplay - 1) |
> > -		       VTOTAL(crtc_vtotal - 1));
> > -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> > -		       VBLANK_START(crtc_vblank_start - 1) |
> > -		       VBLANK_END(crtc_vblank_end - 1));
> > -	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> > -		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > -		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > +	trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> > +			   VTOTAL(crtc_vtotal - 1);
> > +	trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> > +			   VBLANK_END(crtc_vblank_end - 1);
> > +	trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start -
> 1) |
> > +			  VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> > +	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> trans_vtotal_val);
> > +	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> trans_vblank_val);
> > +	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> > +trans_vsync_val);
> >
> >  	/* Workaround: when the EDP input selection is B, the VTOTAL_B
> must be
> >  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C.
> This is
> > @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> >  		intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> >  			       crtc_state->min_hblank);
> >  	}
> > +
> > +	if (crtc->cmtg.enable) {
> > +		crtc->cmtg.htotal = trans_htotal_val;
> > +		crtc->cmtg.hblank = trans_hblank_val;
> > +		crtc->cmtg.hsync = trans_hsync_val;
> > +		crtc->cmtg.vtotal = trans_vtotal_val;
> > +		crtc->cmtg.vblank = trans_vblank_val;
> > +		crtc->cmtg.vsync = trans_vsync_val;
> > +	}
> >  }
> >
> >  static void intel_set_transcoder_timings_lrr(const struct
> > intel_crtc_state *crtc_state) diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1081615a14fb..defb54dd0bbe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1572,6 +1572,8 @@ struct intel_crtc {
> >
> >  	struct {
> >  		bool enable;
> > +		u32 htotal, hblank, hsync;
> > +		u32 vtotal, vblank, vsync;
> 
> Why are these stored in the crtc?

Cannot store in crtc_state store as it is const. Some adjustment is done before writing to these registers.
So exact same register value need to keep for cmtg as it need to enable as secondary mode after modeset.
Storing in Intel_crtc I felt is a way, but open for any better approach.

Regards,
Animesh
> 
> >  	} cmtg;
> >  };
> 
> --
> Jani Nikula, Intel

RE: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:20 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl
> 
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Enable CMTG through control register.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 3af4aefc760e..f7364c7408d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -244,6 +244,19 @@ static void
> intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
> >  	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder),
> > m_n->link_n);  }
> >
> > +static void intel_cmtg_ctl_enable(const struct intel_crtc_state
> > +*crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	u32 val = 0;
> > +
> > +	val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
> > +
> > +	val |= CMTG_ENABLE;
> > +
> > +	intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);
> 
> This is just a single line intel_de_rmw().
> 
> > +}
> > +
> >  void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)  {
> >  	struct intel_display *display = to_intel_display(crtc_state); @@
> > -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state
> > *crtc_state)
> >
> >  	/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> >  	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> > CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> > +
> > +	/* Program Enable Cmtg */
> > +	intel_cmtg_ctl_enable(crtc_state);
> 
> If there's intel_de_rmw() before, why is this a function?

Got it, will take care in next version.
> 
> >  }
> 
> --
> Jani Nikula, Intel

RE: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:23 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary
> mode
> 
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > From: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> >
> > Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence and then
> > enable secondary mode for cmtg.
> >
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index f7364c7408d5..d1ec9b79cef2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct
> > intel_crtc_state *crtc_state)
> >
> >  	/* Program Enable Cmtg */
> >  	intel_cmtg_ctl_enable(crtc_state);
> > +
> > +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder),
> > +				       CMTG_SYNC_TO_PORT, 50)) {
> > +		drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n",
> cpu_transcoder);
> > +		return;
> > +	}
> 
> This should be part of the previous patch, right?

Yes, will take care in next version.

> 
> > +
> > +	/*
> > +	 *  eDP transcoder registers as secondary to CMTG by setting
> > +	 *  TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].
> 
> What does this even mean?

CMTG will be enabled in secondary mode. Some copy-paste issue, will rephrase the above comment.

> 
> > +	 */
> > +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> > +0, CMTG_SECONDARY_MODE);
> > +
> > +	drm_dbg_kms(display->drm, "CMTG:%d enabled\n",
> cpu_transcoder);
> 
> See transcoder_name().
> 
> >  }
> 
> --
> Jani Nikula, Intel