From: Matthew Auld <matthew.auld@intel.com>
To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
Date: Tue, 30 Mar 2021 10:26:56 +0100 [thread overview]
Message-ID: <690d9939-ef42-386c-9f12-e38bfd7c1282@intel.com> (raw)
In-Reply-To: <20210328225709.18541-13-daniele.ceraolospurio@intel.com>
On 28/03/2021 23:57, Daniele Ceraolo Spurio wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support PAVP.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 45d60e3d98e3..3ad3413c459f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -7,6 +7,7 @@
> #include "gem/i915_gem_region.h"
>
> #include "i915_drv.h"
> +#include "i915_user_extensions.h"
>
> static int
> i915_gem_create(struct drm_file *file,
> @@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
> &args->size, &args->handle);
> }
>
> +struct create_ext {
> + struct drm_i915_private *i915;
> +};
> +
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct create_ext *ext_data)
> +{
> + if (!(args->param & I915_OBJECT_PARAM)) {
> + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int create_setparam(struct i915_user_extension __user *base, void *data)
> +{
> + struct drm_i915_gem_create_ext_setparam ext;
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + return __create_setparam(&ext.param, data);
> +}
> +
> +static const i915_user_extension_fn create_extensions[] = {
> + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
> +};
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_i915_gem_create *args = data;
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
>
> i915_gem_flush_free_objects(i915);
>
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + &ext_data);
> + if (ret)
> + return ret;
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 02d5b2b6ee39..f13e1ca2087b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1707,7 +1707,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 7a2088eccc9f..d5e502269a55 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
> #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -729,6 +730,27 @@ struct drm_i915_gem_create {
> __u32 pad;
> };
>
> +struct drm_i915_gem_create_ext {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> + (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> + __u64 extensions;
> +
> +};
> +
> struct drm_i915_gem_pread {
> /** Handle for the object being read. */
> __u32 handle;
> @@ -1720,6 +1742,31 @@ struct drm_i915_gem_context_param {
> __u64 value;
> };
>
> +struct drm_i915_gem_object_param {
> + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> + __u32 handle;
> +
> + /* Data pointer size */
> + __u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM (1ull << 32)
> +
> + __u64 param;
> +
> + /* Data value or pointer */
> + __u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> + struct i915_user_extension base;
> + struct drm_i915_gem_object_param param;
> +};
> +
Fwiw there were some minor uAPI changes(like using a separate ioctl)
needed for this, as per the upstream review feedback for the placements
extension. I think the required changes should already be incorporated here:
https://patchwork.freedesktop.org/series/86866/
> /**
> * Context SSEU programming
> *
>
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next prev parent reply other threads:[~2021-03-30 9:27 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
2021-03-29 13:55 ` Michal Wajdeczko
2021-04-08 21:38 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
2021-03-29 14:15 ` Michal Wajdeczko
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
2021-04-08 21:47 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
2021-04-08 21:50 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
2021-04-08 21:52 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
2021-04-08 22:01 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
2021-04-09 9:16 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
2021-04-09 9:38 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
2021-04-20 14:31 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
2021-04-01 12:06 ` Lionel Landwerlin
2021-04-15 17:20 ` Daniel Vetter
2021-04-20 14:35 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
2021-03-30 9:26 ` Matthew Auld [this message]
2021-04-15 17:16 ` Daniel Vetter
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
2021-04-01 12:05 ` Lionel Landwerlin
2021-04-01 20:45 ` Daniele Ceraolo Spurio
2021-04-20 14:40 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
2021-04-20 14:48 ` Rodrigo Vivi
2021-04-20 22:00 ` Ville Syrjälä
2021-04-27 10:43 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
2021-04-28 11:25 ` Gupta, Anshuman
2021-04-28 12:03 ` Ville Syrjälä
2021-04-28 17:32 ` Daniele Ceraolo Spurio
2021-04-28 20:04 ` Ville Syrjälä
2021-04-28 20:39 ` Daniele Ceraolo Spurio
2021-04-30 6:56 ` Gupta, Anshuman
2021-04-30 12:52 ` Ville Syrjälä
2021-04-30 7:01 ` Gupta, Anshuman
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
2021-04-27 10:45 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
2021-04-30 7:12 ` Gupta, Anshuman
2021-04-30 12:55 ` Ville Syrjälä
2021-05-07 18:42 ` Rodrigo Vivi
2021-05-14 13:41 ` Teres Alexis, Alan Previn
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
2021-03-28 23:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev3) Patchwork
2021-03-28 23:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-28 23:39 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-03-29 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-29 1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-04-01 12:07 ` [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Lionel Landwerlin
2021-04-27 13:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP (rev5) Patchwork
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