From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: "Gaurav, Kumar" <kumar.gaurav@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
Date: Fri, 30 Apr 2021 07:12:53 +0000 [thread overview]
Message-ID: <96d9782a7e864448a4d311f4eeaa6923@intel.com> (raw)
In-Reply-To: <YIhePcRcpKEoBmAE@intel.com>
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, April 28, 2021 12:26 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Gaurav, Kumar <kumar.gaurav@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Ceraolo Spurio, Daniele
> <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
>
> On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> > When protected sufaces has flipped and pxp session is disabled,
> > display black pixels by using plane color CTM correction.
> >
> > v2:
> > - Display black pixels in aysnc flip too.
>
> We can't change any of that with an async flip.
I was thinking of an scenario , when application flip the protected surfaces with synchronous flips
and driver has enable the plane decryption, can application issue an intermediate async flip with
protected surfaces afterwards ?
If above is possible, is it possible to display black pixels in case of pxp session invalidation at the time of
Plane commit?
Thanks,
Anshuman
>
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Cc: Shankar Uma <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > ---
> > .../drm/i915/display/skl_universal_plane.c | 51 ++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++
> > 2 files changed, 95 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 74489217e580..a666b86df726 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -934,6 +934,33 @@ static u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
> > return plane_color_ctl;
> > }
> >
> > +static void intel_load_plane_csc_black(struct intel_plane
> > +*intel_plane) {
> > + struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
> > + enum pipe pipe = intel_plane->pipe;
> > + enum plane_id plane = intel_plane->id;
> > + u16 postoff = 0;
> > +
> > + drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
> > + intel_plane->base.name, plane);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0),
> postoff);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1),
> postoff);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2),
> > +postoff); }
> > +
> > static void
> > skl_program_plane(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state, @@ -1039,13
> +1066,22
> > @@ skl_program_plane(struct intel_plane *plane,
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > + plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> > +plane_id));
> >
> > if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > - plane_state->plane_decryption)
> > + plane_state->plane_decryption) {
> > plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > - else
> > + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> > + } else if (plane_state->plane_decryption) {
> > + intel_load_plane_csc_black(plane);
> > + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> > + } else {
> > plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> > + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> > + }
> >
> > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > + plane_color_ctl);
> > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >
> > if (plane_state->scaler_id >= 0)
> > @@ -1066,6 +1102,7 @@ skl_plane_async_flip(struct intel_plane *plane,
> > enum pipe pipe = plane->pipe;
> > u32 surf_addr = plane_state->view.color_plane[0].offset;
> > u32 plane_ctl = plane_state->ctl;
> > + u32 plane_color_ctl = 0;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >
> > @@ -1075,6 +1112,16 @@ skl_plane_async_flip(struct intel_plane *plane,
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > +
> > + if (!intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > + plane_state->plane_decryption) {
> > + plane_color_ctl = intel_de_read_fw(dev_priv,
> PLANE_COLOR_CTL(pipe, plane_id));
> > + intel_load_plane_csc_black(plane);
> > + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> plane_id),
> > + plane_color_ctl);
> > + }
> > +
> > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > intel_plane_ggtt_offset(plane_state) + surf_addr);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index fbaf9199001d..0a4deca1098b
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7119,6 +7119,7 @@ enum {
> > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> > #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /*
> Pre-ICL */
> > #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 <<
> 21) /* ICL+ */
> > #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> > #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> > #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> > @@ -11191,6 +11192,51 @@ enum skl_power_gate {
> > _PAL_PREC_MULTI_SEG_DATA_A, \
> > _PAL_PREC_MULTI_SEG_DATA_B)
> >
> > +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) +
> > +(i) * 4)
> > +
> > +/* Plane CSC Registers */
> > +#define _PLANE_CSC_RY_GY_1_A 0x70210
> > +#define _PLANE_CSC_RY_GY_2_A 0x70310
> > +
> > +#define _PLANE_CSC_RY_GY_1_B 0x71210
> > +#define _PLANE_CSC_RY_GY_2_B 0x71310
> > +
> > +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A,
> \
> > + _PLANE_CSC_RY_GY_1_B)
> > +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe,
> _PLANE_INPUT_CSC_RY_GY_2_A, \
> > + _PLANE_INPUT_CSC_RY_GY_2_B)
> > +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane,
> \
> > +
> _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> > +
> _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> > +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> > +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe,
> _PLANE_CSC_PREOFF_HI_1_A, \
> > + _PLANE_CSC_PREOFF_HI_1_B)
> > +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe,
> _PLANE_CSC_PREOFF_HI_2_A, \
> > + _PLANE_CSC_PREOFF_HI_2_B)
> > +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
> _PLANE_CSC_PREOFF_HI_1(pipe) + \
> > + (index) * 4,
> _PLANE_CSC_PREOFF_HI_2(pipe) + \
> > + (index) * 4)
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> > +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> > +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_1_A, \
> > + _PLANE_CSC_POSTOFF_HI_1_B)
> > +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_2_A, \
> > + _PLANE_CSC_POSTOFF_HI_2_B)
> > +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane,
> _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> > + (index) * 4,
> _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> > + (index) * 4)
> > +
> > /* pipe CSC & degamma/gamma LUTs on CHV */
> > #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> > #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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next prev parent reply other threads:[~2021-04-30 7:12 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
2021-03-29 13:55 ` Michal Wajdeczko
2021-04-08 21:38 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
2021-03-29 14:15 ` Michal Wajdeczko
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
2021-04-08 21:47 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
2021-04-08 21:50 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
2021-04-08 21:52 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
2021-04-08 22:01 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
2021-04-09 9:16 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
2021-04-09 9:38 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
2021-04-20 14:31 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
2021-04-01 12:06 ` Lionel Landwerlin
2021-04-15 17:20 ` Daniel Vetter
2021-04-20 14:35 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
2021-03-30 9:26 ` Matthew Auld
2021-04-15 17:16 ` Daniel Vetter
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
2021-04-01 12:05 ` Lionel Landwerlin
2021-04-01 20:45 ` Daniele Ceraolo Spurio
2021-04-20 14:40 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
2021-04-20 14:48 ` Rodrigo Vivi
2021-04-20 22:00 ` Ville Syrjälä
2021-04-27 10:43 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
2021-04-28 11:25 ` Gupta, Anshuman
2021-04-28 12:03 ` Ville Syrjälä
2021-04-28 17:32 ` Daniele Ceraolo Spurio
2021-04-28 20:04 ` Ville Syrjälä
2021-04-28 20:39 ` Daniele Ceraolo Spurio
2021-04-30 6:56 ` Gupta, Anshuman
2021-04-30 12:52 ` Ville Syrjälä
2021-04-30 7:01 ` Gupta, Anshuman
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
2021-04-27 10:45 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
2021-04-30 7:12 ` Gupta, Anshuman [this message]
2021-04-30 12:55 ` Ville Syrjälä
2021-05-07 18:42 ` Rodrigo Vivi
2021-05-14 13:41 ` Teres Alexis, Alan Previn
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
2021-03-28 23:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev3) Patchwork
2021-03-28 23:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-28 23:39 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-03-29 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-29 1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-04-01 12:07 ` [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Lionel Landwerlin
2021-04-27 13:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP (rev5) Patchwork
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