From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping
Date: Wed, 17 Feb 2021 17:25:22 +0000 [thread overview]
Message-ID: <717eed5be5ec9145f33c087f63bd71f01688821d.camel@intel.com> (raw)
In-Reply-To: <YCbwceGlRhcPJikB@intel.com>
On Fri, 2021-02-12 at 23:17 +0200, Ville Syrjälä wrote:
> On Fri, Feb 12, 2021 at 07:42:17PM +0000, Souza, Jose wrote:
> > On Fri, 2021-02-12 at 21:20 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 12, 2021 at 10:21:59AM -0800, José Roberto de Souza wrote:
> > > > The cfgcr0/1_clk_off mapping is wrong for adl-s what could cause
> > > > the wrong clock being disabled and leaving a not needed clock
> > > > running consuming more power than needed.
> > > >
> > > > Bspec: 50287
> > > > Bspec: 53812
> > > > Bspec: 53723
> > > > Fixes: d6d2bc996e45 ("drm/i915/adl_s: Configure Port clock registers for ADL-S")
> > > > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++
> > > > 2 files changed, 15 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 2d6906f6995f..7631e080349d 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1585,7 +1585,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
> > > > static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> > > > enum phy phy)
> > > > {
> > > > - if (IS_ROCKETLAKE(dev_priv)) {
> > > > + if (IS_ALDERLAKE_S(dev_priv)) {
> > > > + return ADLS_DPCLKA_CFGCR_DDI_CLK_OFF(phy);
> > > > + } else if (IS_ROCKETLAKE(dev_priv)) {
> > > > return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> > > > } else if (intel_phy_is_combo(dev_priv, phy)) {
> > > > return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 224ad897af34..7c69b50ccc5c 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -10416,6 +10416,18 @@ enum skl_power_gate {
> > > > ADLS_DPCLKA_DDIJ_SEL_MASK, \
> > > > ADLS_DPCLKA_DDIK_SEL_MASK)
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > +#define _ADLS_DPCLKA_DDIA_CLK_OFF REG_BIT(10)
> > > > +#define _ADLS_DPCLKA_DDIB_CLK_OFF REG_BIT(11)
> > > > +#define _ADLS_DPCLKA_DDII_CLK_OFF REG_BIT(24)
> > > > +#define _ADLS_DPCLKA_DDIJ_CLK_OFF REG_BIT(4)
> > > > +#define _ADLS_DPCLKA_DDIK_CLK_OFF REG_BIT(5)
> > >
> > > So shose are apparently split between the two registers. Why aren't
> > > we defining these so that it would be obvious which register they
> > > live in? This stuff is confusing enough with the hw folks churning
> > > the bits around randomly on every platform, so I don't think we
> > > should add to the confusion by obfuscating the bit defines. I do
> > > like that you named the bits, which isn't case for the other
> > > platforms. Would be nice to fix it all up actually.
> > >
> > > Hmm. However, this new defintion seem to match
> > > ICL_DPCLKA_CFGCR0_DDI_CLK_OFF() 100%. So how can this be fixing
> > > something? Also ICL for sure can't have that many combo PHYs can
> > > it? We should nuke the extra stuff from the ICL defintion if it's
> > > no longer used.
> >
> > Good catch & my bad.
> > Was fixing it for other platform and tought that it might be broken
> > for ADL-S too but as all ports are combo ports
> > ICL_DPCLKA_CFGCR0_DDI_CLK_OFF will do the right job.
> >
> > Dropping this patch.
>
> I wouldn't mind having this patch, or rather a patch to clean up/clarify
> all the DPCLKA_CFGCR bits on every platform. As it stands cross checking
> against the spec is a bit tedious.
Okay, will try to do something better around here.
>
> But at least right now I don't have to rebase my DDI clock routing
> series [1] :) That one still has a few trivial patches looking for review
> btw *wink* *nudge*.
Lucas already did =]
Let me know if you have anything else pending that is not huge.
>
> [1] https://patchwork.freedesktop.org/series/86544/
>
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next prev parent reply other threads:[~2021-02-17 17:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 18:21 [Intel-gfx] [PATCH 1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping José Roberto de Souza
2021-02-12 18:22 ` [Intel-gfx] [PATCH 2/3] drm/i915: Remove dead code from skl_pipe_wm_get_hw_state() José Roberto de Souza
2021-02-12 18:33 ` Ville Syrjälä
2021-02-12 18:22 ` [Intel-gfx] [PATCH 3/3] drm/i915: Fix plane watermark mismatches José Roberto de Souza
2021-02-12 18:35 ` Ville Syrjälä
2021-02-12 19:44 ` Souza, Jose
2021-02-12 21:13 ` Ville Syrjälä
2021-02-17 17:24 ` Souza, Jose
2021-02-17 22:14 ` Ville Syrjälä
2021-02-18 17:25 ` Souza, Jose
2021-02-18 18:21 ` Ville Syrjälä
2021-02-19 19:35 ` Souza, Jose
2021-02-12 18:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping Patchwork
2021-02-12 18:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-12 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-12 19:15 ` [Intel-gfx] [PATCH 1/3] " Aditya Swarup
2021-02-12 19:20 ` Ville Syrjälä
2021-02-12 19:42 ` Souza, Jose
2021-02-12 21:17 ` Ville Syrjälä
2021-02-17 17:25 ` Souza, Jose [this message]
2021-02-12 20:15 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
2021-02-17 17:32 ` Souza, Jose
2021-02-18 20:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping (rev2) Patchwork
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