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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix plane watermark mismatches
Date: Fri, 12 Feb 2021 20:35:55 +0200	[thread overview]
Message-ID: <YCbKi3rpV3pWwkHw@intel.com> (raw)
In-Reply-To: <20210212182201.155043-3-jose.souza@intel.com>

On Fri, Feb 12, 2021 at 10:22:01AM -0800, José Roberto de Souza wrote:
> Found a system were firmware/BIOS left the plane_res_b and plane_res_l
> set with non-zero values for disable planes.

It pretty much happens always since the reset value is not zero.
IIRC we made the state chcker pedantic enough to complain about
that, so we need to clean it up.

> As the planes are disabled i915 will not even try to sanitize it so
> here returning earlier if both skl_wm_levels being compared are
> disabled, if that is true no need to check the other fields as HW
> will ignore it.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8cc67f9c4e58..c630dc10c34b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5633,6 +5633,8 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
>  			 const struct skl_wm_level *l2)
>  {
> +	if (l1->plane_en == false && l2->plane_en == false)
> +		return true;
>  	return l1->plane_en == l2->plane_en &&
>  		l1->ignore_lines == l2->ignore_lines &&
>  		l1->plane_res_l == l2->plane_res_l &&
> -- 
> 2.30.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-02-12 18:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-12 18:21 [Intel-gfx] [PATCH 1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping José Roberto de Souza
2021-02-12 18:22 ` [Intel-gfx] [PATCH 2/3] drm/i915: Remove dead code from skl_pipe_wm_get_hw_state() José Roberto de Souza
2021-02-12 18:33   ` Ville Syrjälä
2021-02-12 18:22 ` [Intel-gfx] [PATCH 3/3] drm/i915: Fix plane watermark mismatches José Roberto de Souza
2021-02-12 18:35   ` Ville Syrjälä [this message]
2021-02-12 19:44     ` Souza, Jose
2021-02-12 21:13       ` Ville Syrjälä
2021-02-17 17:24         ` Souza, Jose
2021-02-17 22:14           ` Ville Syrjälä
2021-02-18 17:25             ` Souza, Jose
2021-02-18 18:21               ` Ville Syrjälä
2021-02-19 19:35                 ` Souza, Jose
2021-02-12 18:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping Patchwork
2021-02-12 18:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-12 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-12 19:15 ` [Intel-gfx] [PATCH 1/3] " Aditya Swarup
2021-02-12 19:20 ` Ville Syrjälä
2021-02-12 19:42   ` Souza, Jose
2021-02-12 21:17     ` Ville Syrjälä
2021-02-17 17:25       ` Souza, Jose
2021-02-12 20:15 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
2021-02-17 17:32   ` Souza, Jose
2021-02-18 20:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping (rev2) Patchwork

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