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From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix plane watermark mismatches
Date: Thu, 18 Feb 2021 17:25:54 +0000	[thread overview]
Message-ID: <cbb1fdee5dea7737ec209a114c84cd5aef5c11e4.camel@intel.com> (raw)
In-Reply-To: <YC2VVWNAMSLqRdLR@intel.com>

On Thu, 2021-02-18 at 00:14 +0200, Ville Syrjälä wrote:
> On Wed, Feb 17, 2021 at 05:24:03PM +0000, Souza, Jose wrote:
> > On Fri, 2021-02-12 at 23:13 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 12, 2021 at 07:44:22PM +0000, Souza, Jose wrote:
> > > > On Fri, 2021-02-12 at 20:35 +0200, Ville Syrjälä wrote:
> > > > > On Fri, Feb 12, 2021 at 10:22:01AM -0800, José Roberto de Souza wrote:
> > > > > > Found a system were firmware/BIOS left the plane_res_b and plane_res_l
> > > > > > set with non-zero values for disable planes.
> > > > > 
> > > > > It pretty much happens always since the reset value is not zero.
> > > > > IIRC we made the state chcker pedantic enough to complain about
> > > > > that, so we need to clean it up.
> > > > 
> > > > Are you planning to fix it soon?
> > > 
> > > Fix what exactly? I guess you're seeing an actual problem of some sort?
> > 
> > Your comment above made me understand that you were planning to fix this plane watermark mismatches for disabled planes in other way other than what
> > this patch does.
> > Or should we proceed with this solution? 
> 
> There should be no mismatches with the current scheme.
> We explicitly program wms to 0 for disabled planes.
> 

It still happens when we take over the state that BIOS/firmware left.

[  118.222939] [drm:drm_atomic_commit] committing 00000000676e6290
[  118.241712] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
[  118.242314] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
[  118.242726] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
[  118.243020] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
[  118.257685] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257698] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257706] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257714] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257721] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257729] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257737] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2 level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257745] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A plane 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257753] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe A plane 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257761] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257769] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257776] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257784] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257792] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257800] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257807] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3 level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257815] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A plane 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257823] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe A plane 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257920] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257929] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257939] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257949] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257956] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257965] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257975] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4 level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257984] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A plane 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.257993] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe A plane 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258002] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258011] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258020] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258029] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258037] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258046] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258054] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5 level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258063] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A plane 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258073] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe A plane 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[  118.258494] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:381:eDP-1]
[  118.259022] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:116:pipe A]
[  118.259811] i915 0000:00:02.0: [drm:intel_ddi_read_func_ctl [i915]] [ENCODER:380:DDI B/PHY B] Fec status: 0
[  118.260284] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 0




Other option would be to call intel_plane_disable_noatomic() even for non-visible planes:

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6014c643a89d..20b3844c8875 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15882,11 +15882,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,

                /* Disable everything but the primary plane */
                for_each_intel_plane_on_crtc(dev, crtc, plane) {
-                       const struct intel_plane_state *plane_state =
-                               to_intel_plane_state(plane->base.state);
-
-                       if (plane_state->uapi.visible &&
-                           plane->base.type != DRM_PLANE_TYPE_PRIMARY)
+                       if (plane->base.type != DRM_PLANE_TYPE_PRIMARY)
                                intel_plane_disable_noatomic(crtc, plane);
                }

What do you think?
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  reply	other threads:[~2021-02-18 17:25 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-12 18:21 [Intel-gfx] [PATCH 1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping José Roberto de Souza
2021-02-12 18:22 ` [Intel-gfx] [PATCH 2/3] drm/i915: Remove dead code from skl_pipe_wm_get_hw_state() José Roberto de Souza
2021-02-12 18:33   ` Ville Syrjälä
2021-02-12 18:22 ` [Intel-gfx] [PATCH 3/3] drm/i915: Fix plane watermark mismatches José Roberto de Souza
2021-02-12 18:35   ` Ville Syrjälä
2021-02-12 19:44     ` Souza, Jose
2021-02-12 21:13       ` Ville Syrjälä
2021-02-17 17:24         ` Souza, Jose
2021-02-17 22:14           ` Ville Syrjälä
2021-02-18 17:25             ` Souza, Jose [this message]
2021-02-18 18:21               ` Ville Syrjälä
2021-02-19 19:35                 ` Souza, Jose
2021-02-12 18:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping Patchwork
2021-02-12 18:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-12 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-12 19:15 ` [Intel-gfx] [PATCH 1/3] " Aditya Swarup
2021-02-12 19:20 ` Ville Syrjälä
2021-02-12 19:42   ` Souza, Jose
2021-02-12 21:17     ` Ville Syrjälä
2021-02-17 17:25       ` Souza, Jose
2021-02-12 20:15 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
2021-02-17 17:32   ` Souza, Jose
2021-02-18 20:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping (rev2) Patchwork

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