[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[PATCH 0/3] DPCD Backlight Control

[Yetunde Adebisi]

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 

- Patch 3 Implements functionaly for DPCD Backlight Control for special
DP-LVDS add-on cards.

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
    size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)
  drm/i915: Add backlight Control using DPCD registers for DP connectors

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/i915_params.c            |   4 +
 drivers/gpu/drm/i915/i915_params.h            |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  42 +++++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   8 ++
 drivers/gpu/drm/i915/intel_panel.c            |  38 ++++--
 include/drm/drm_dp_helper.h                   |   1 +
 8 files changed, 256 insertions(+), 16 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[PATCH 2/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)

[Yetunde Adebisi]

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
	(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/i915_params.c            |   4 +
 drivers/gpu/drm/i915/i915_params.h            |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   6 +
 drivers/gpu/drm/i915/intel_panel.c            |   5 +
 7 files changed, 198 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..11cc3e6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
 	  dvo_tfp410.o \
 	  intel_crt.o \
 	  intel_ddi.o \
+	  intel_dp_aux_backlight.o \
 	  intel_dp_link_training.o \
 	  intel_dp_mst.o \
 	  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
 	.guc_log_level = -1,
 	.enable_dp_mst = true,
 	.inject_load_failure = 0,
+	.enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
 MODULE_PARM_DESC(inject_load_failure,
 	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+	"Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
 	bool verbose_state_checks;
 	bool nuclear_pageflip;
 	bool enable_dp_mst;
+	bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3bdd8ba..9e9e7f1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3109,7 +3109,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
 			void *buffer, size_t size)
 {
@@ -3776,7 +3776,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint8_t rev;
 
 	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
 				    sizeof(intel_dp->dpcd)) < 0)
@@ -3812,6 +3811,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			DRM_DEBUG_KMS("PSR2 %s on sink",
 				dev_priv->psr.psr2_support ? "supported" : "not supported");
 		}
+
+		/* Read the eDP Display control capabilities registers */
+		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
+						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
+								sizeof(intel_dp->edp_dpcd)))
+			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
+					intel_dp->edp_dpcd);
 	}
 
 	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3819,10 +3827,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
 	/* Intermediate frequency support */
-	if (is_edp(intel_dp) &&
-	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
-	    (rev >= 0x03)) { /* eDp v1.4 or higher */
+	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 		int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 0000000..a5361d6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+	uint8_t reg_val = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			&reg_val, sizeof(reg_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_DISPLAY_CONTROL_REGISTER);
+		return;
+	}
+	if (enable)
+		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+	else
+		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			reg_val) < 0) {
+		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
+				enable ? "enable" : "disable");
+	}
+}
+
+/*
+ * Read the current backlight value from DPCD register(s) based
+ * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
+ */
+static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t read_val[2] = { 0x0 };
+	uint16_t level = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			&read_val, sizeof(read_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+		return 0;
+	}
+	level = read_val[0];
+	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		level = (read_val[0] << 8 | read_val[1]);
+
+	return level;
+}
+
+/*
+ * Sends the current backlight level over the aux channel, checking if its using
+ * 8-bit or 16 bit value (MSB and LSB)
+ */
+static void
+intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t vals[2] = { 0x0 };
+
+	vals[0] = level;
+
+	/* Write the MSB and/or LSB */
+	 if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+		vals[0] = (level & 0xFF00) >> 8;
+		vals[1] = (level & 0xFF);
+	}
+	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			vals, sizeof(vals)) < 0) {
+		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+		return;
+	}
+}
+
+static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t dpcd_buf = 0;
+
+	set_aux_backlight_enable(intel_dp, true);
+
+	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
+			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
+			((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
+					DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+				(dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
+}
+
+static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
+{
+	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
+}
+
+static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
+			enum pipe pipe)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	struct intel_panel *panel = &connector->panel;
+
+	intel_dp_aux_enable_backlight(connector);
+
+	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		panel->backlight.max = 0xFFFF;
+	else
+		panel->backlight.max = 0xFF;
+
+	panel->backlight.min = 0;
+	panel->backlight.level = intel_dp_aux_get_backlight(connector);
+
+	panel->backlight.enabled = panel->backlight.level != 0;
+
+	return 0;
+}
+
+static bool
+intel_dp_aux_display_control_capable(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+
+	/* Check the  eDP Display control capabilities registers to determine if
+	 * the panel can support backlight control over the aux channel
+	 */
+	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
+			(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+			!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
+					(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
+
+		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
+		return true;
+	}
+	return false;
+}
+
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
+{
+	struct intel_panel *panel = &intel_connector->panel;
+
+	if (!intel_dp_aux_display_control_capable(intel_connector))
+		return -ENODEV;
+
+	panel->backlight.setup = intel_dp_aux_setup_backlight;
+	panel->backlight.enable = intel_dp_aux_enable_backlight;
+	panel->backlight.disable = intel_dp_aux_disable_backlight;
+	panel->backlight.set = intel_dp_aux_set_backlight;
+	panel->backlight.get = intel_dp_aux_get_backlight;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b450..782a103 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -803,6 +803,7 @@ struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 	uint8_t num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
@@ -1318,6 +1319,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
+ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
+		void *buffer, size_t size);
+
+/* intel_dp_aux_backlight.c */
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 8c8996f..cdfcdad 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1718,6 +1718,11 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		container_of(panel, struct intel_connector, panel);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
+	if (i915.enable_dpcd_backlight &&
+			(connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
+					intel_dp_aux_init_backlight_funcs(connector) == 0))
+		return;
+
 	if (IS_BROXTON(dev_priv)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;
-- 
1.9.3

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[PATCH 3/3] drm/i915: Add backlight Control using DPCD registers for DP connectors

[Yetunde Adebisi]

This patch enables support for DPCD backlight control for DP connectors.
The VESA spec defines DPCD backlight control only for eDP but some add-on
cards like the Chrontel CH7511B DP-LVDS cards have the display control
DPCD registers enabled.
This patch registers a backlight device exposed via sysfs that controls the
connected panel backlight by writing to DPCD registers on the CH7511B
add-on card

Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               | 25 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c |  7 ++++++
 drivers/gpu/drm/i915/intel_drv.h              |  2 ++
 drivers/gpu/drm/i915/intel_panel.c            | 33 +++++++++++++++++++--------
 4 files changed, 57 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9e9e7f1..8bbfb7f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5631,6 +5631,30 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
 	return downclock_mode;
 }
 
+/*
+ * Called on DP connector initialization to check for aux backlight control
+ * capability on the sink device and if present, initialize it.
+ */
+static void intel_dp_init_aux_backlight(struct intel_dp *intel_dp,
+		struct drm_connector *connector)
+{
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+
+	if (is_edp(intel_dp))
+		return;
+
+	if (i915.enable_dpcd_backlight &&
+			(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
+					intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
+							sizeof(intel_dp->edp_dpcd)) &&
+							intel_dp_aux_init_backlight_funcs(intel_connector) == 0) {
+		intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+		intel_connector->panel.backlight.power = intel_dp_aux_backlight_power;
+		intel_connector->panel.backlight.enabled = true;
+		}
+}
+
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 				     struct intel_connector *intel_connector)
 {
@@ -5868,6 +5892,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		goto fail;
 	}
 
+	intel_dp_init_aux_backlight(intel_dp, connector);
 	intel_dp_add_properties(intel_dp, connector);
 
 	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index a5361d6..efa657f 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -168,3 +168,10 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
 
 	return 0;
 }
+
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+				      bool enable)
+{
+	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base),
+			enable);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 782a103..ab92e89 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1324,6 +1324,8 @@ ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
 
 /* intel_dp_aux_backlight.c */
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+				      bool enable);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index cdfcdad..d678e55 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1193,16 +1193,29 @@ static int intel_backlight_device_register(struct intel_connector *connector)
 	else
 		props.power = FB_BLANK_POWERDOWN;
 
-	/*
-	 * Note: using the same name independent of the connector prevents
-	 * registration of multiple backlight devices in the driver.
-	 */
-	panel->backlight.device =
-		backlight_device_register("intel_backlight",
-					  connector->base.kdev,
-					  connector,
-					  &intel_backlight_device_ops, &props);
-
+	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+		char *name = kasprintf(GFP_KERNEL, "intel_aux_backlight-%s",
+				connector->base.name);
+		if (!name)
+			return -ENOMEM;
+
+		panel->backlight.device =
+			backlight_device_register(name,
+						  connector->base.kdev,
+						  connector,
+						  &intel_backlight_device_ops, &props);
+			kfree(name);
+	} else {
+		/*
+		 * Note: using the same name independent of the connector prevents
+		 * registration of multiple backlight devices in the driver.
+		 */
+		panel->backlight.device =
+			backlight_device_register("intel_backlight",
+						  connector->base.kdev,
+						  connector,
+						  &intel_backlight_device_ops, &props);
+	}
 	if (IS_ERR(panel->backlight.device)) {
 		DRM_ERROR("Failed to register backlight: %ld\n",
 			  PTR_ERR(panel->backlight.device));
-- 
1.9.3

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Re: [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Jani Nikula]

On Wed, 30 Mar 2016, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote:
> This is used when reading Display Control capability Registers on the sink
> device.
>
> cc: Jani Nikula <jani.nikula@intel.com>
> cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  include/drm/drm_dp_helper.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1252108..92d9a52 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
>  #define DP_BRANCH_OUI_HEADER_SIZE	0xc
>  #define DP_RECEIVER_CAP_SIZE		0xf
>  #define EDP_PSR_RECEIVER_CAP_SIZE	2
> +#define EDP_DISPLAY_CTL_CAP_SIZE	3
>  
>  void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>  void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 2/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)

[Jani Nikula]

On Wed, 30 Mar 2016, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote:
> This patch adds support for eDP backlight control using DPCD registers to
> backlight hooks in intel_panel.
>
> It checks for backlight control over AUX channel capability and sets up
> function pointers to get and set the backlight brightness level if
> supported.
>
> v2: Moved backlight functions from intel_dp.c into a new file
> intel_dp_aux_backlight.c. Also moved reading of eDP display control
> registers to intel_dp_get_dpcd
>
> v3: Correct some formatting mistakes
>
> v4: Updated to use AUX backlight control if PWM control is not possible
> 	(Jani)
> v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
> v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
> backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
> v7: Add enable_dpcd_backlight module parameter.
> v8: Rebase onto latest drm-intel-nightly branch
>
> This patch depends on http://patchwork.freedesktop.org/patch/64253/
>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>

Please accept my apologies for taking so long to get back to
this. Overall looks fine, a couple of "mechanic" changes required (see
comments inline below).

As follow-up later on we should look at using vbt as in [1] to replace
the module parameter. This smells like the "panel driver
interface". Maybe.

BR,
Jani.

[1] http://mid.gmane.org/1459346623-30752-3-git-send-email-jani.nikula@intel.com


> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/i915_params.c            |   4 +
>  drivers/gpu/drm/i915/i915_params.h            |   1 +
>  drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
>  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h              |   6 +
>  drivers/gpu/drm/i915/intel_panel.c            |   5 +
>  7 files changed, 198 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7ffb51b..11cc3e6 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
>  	  dvo_tfp410.o \
>  	  intel_crt.o \
>  	  intel_ddi.o \
> +	  intel_dp_aux_backlight.o \
>  	  intel_dp_link_training.o \
>  	  intel_dp_mst.o \
>  	  intel_dp.o \
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 1779f02..383c076 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
>  	.guc_log_level = -1,
>  	.enable_dp_mst = true,
>  	.inject_load_failure = 0,
> +	.enable_dpcd_backlight = false,
>  };
>  
>  module_param_named(modeset, i915.modeset, int, 0400);
> @@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
>  module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
>  MODULE_PARM_DESC(inject_load_failure,
>  	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
> +module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600);
> +MODULE_PARM_DESC(enable_dpcd_backlight,
> +	"Enable support for DPCD backlight control (default:false)");
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 02bc278..65e73dd 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -61,6 +61,7 @@ struct i915_params {
>  	bool verbose_state_checks;
>  	bool nuclear_pageflip;
>  	bool enable_dp_mst;
> +	bool enable_dpcd_backlight;
>  };
>  
>  extern struct i915_params i915 __read_mostly;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3bdd8ba..9e9e7f1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3109,7 +3109,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>   * Sinks are *supposed* to come up within 1ms from an off state, but we're also
>   * supposed to retry 3 times per the spec.
>   */
> -static ssize_t
> +ssize_t
>  intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
>  			void *buffer, size_t size)

I'm going to have to ask you send another version dropping all the
changes to _wake, and switching to use the plain drm_dp_dpcd_read()
instead of intel_dp_dpcd_read_wake() all around. Otherwise, we'll
conflict badly with [2] getting merged.

[2] http://mid.gmane.org/1459175606-13875-1-git-send-email-cpaul@redhat.com

>  {
> @@ -3776,7 +3776,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint8_t rev;
>  
>  	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
>  				    sizeof(intel_dp->dpcd)) < 0)
> @@ -3812,6 +3811,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  			DRM_DEBUG_KMS("PSR2 %s on sink",
>  				dev_priv->psr.psr2_support ? "supported" : "not supported");
>  		}
> +
> +		/* Read the eDP Display control capabilities registers */
> +		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
> +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> +				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> +						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
> +								sizeof(intel_dp->edp_dpcd)))
> +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
> +					intel_dp->edp_dpcd);
>  	}
>  
>  	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> @@ -3819,10 +3827,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
>  
>  	/* Intermediate frequency support */
> -	if (is_edp(intel_dp) &&
> -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
> -	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> +	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */

Please turn these two hunks above plus the addition of
intel_dp->edp_dpcd into a standalone prep patch. Please keep using _wake
version here (we'll resolve this conflict).

>  		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>  		int i;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> new file mode 100644
> index 0000000..a5361d6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -0,0 +1,170 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "intel_drv.h"
> +
> +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
> +{
> +	uint8_t reg_val = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			&reg_val, sizeof(reg_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_DISPLAY_CONTROL_REGISTER);
> +		return;
> +	}
> +	if (enable)
> +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> +	else
> +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> +
> +	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			reg_val) < 0) {
> +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> +				enable ? "enable" : "disable");
> +	}
> +}
> +
> +/*
> + * Read the current backlight value from DPCD register(s) based
> + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> + */
> +static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t read_val[2] = { 0x0 };
> +	uint16_t level = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			&read_val, sizeof(read_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
> +		return 0;
> +	}
> +	level = read_val[0];
> +	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		level = (read_val[0] << 8 | read_val[1]);
> +
> +	return level;
> +}
> +
> +/*
> + * Sends the current backlight level over the aux channel, checking if its using
> + * 8-bit or 16 bit value (MSB and LSB)
> + */
> +static void
> +intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t vals[2] = { 0x0 };
> +
> +	vals[0] = level;
> +
> +	/* Write the MSB and/or LSB */
> +	 if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
> +		vals[0] = (level & 0xFF00) >> 8;
> +		vals[1] = (level & 0xFF);
> +	}
> +	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			vals, sizeof(vals)) < 0) {
> +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
> +		return;
> +	}
> +}
> +
> +static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t dpcd_buf = 0;
> +
> +	set_aux_backlight_enable(intel_dp, true);
> +
> +	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
> +			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
> +			((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> +					DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
> +		drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> +				(dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
> +}
> +
> +static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
> +{
> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
> +}
> +
> +static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
> +			enum pipe pipe)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	struct intel_panel *panel = &connector->panel;
> +
> +	intel_dp_aux_enable_backlight(connector);
> +
> +	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		panel->backlight.max = 0xFFFF;
> +	else
> +		panel->backlight.max = 0xFF;
> +
> +	panel->backlight.min = 0;
> +	panel->backlight.level = intel_dp_aux_get_backlight(connector);
> +
> +	panel->backlight.enabled = panel->backlight.level != 0;
> +
> +	return 0;
> +}
> +
> +static bool
> +intel_dp_aux_display_control_capable(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +
> +	/* Check the  eDP Display control capabilities registers to determine if
> +	 * the panel can support backlight control over the aux channel
> +	 */
> +	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> +			(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> +			!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
> +					(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
> +
> +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> +		return true;
> +	}
> +	return false;
> +}
> +
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
> +{
> +	struct intel_panel *panel = &intel_connector->panel;
> +
> +	if (!intel_dp_aux_display_control_capable(intel_connector))
> +		return -ENODEV;
> +
> +	panel->backlight.setup = intel_dp_aux_setup_backlight;
> +	panel->backlight.enable = intel_dp_aux_enable_backlight;
> +	panel->backlight.disable = intel_dp_aux_disable_backlight;
> +	panel->backlight.set = intel_dp_aux_set_backlight;
> +	panel->backlight.get = intel_dp_aux_get_backlight;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c87b450..782a103 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -803,6 +803,7 @@ struct intel_dp {
>  	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> +	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];

So this change should go with the changes in intel_dp.c

>  	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>  	uint8_t num_sink_rates;
>  	int sink_rates[DP_MAX_SUPPORTED_RATES];
> @@ -1318,6 +1319,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
>  bool
>  intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
> +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
> +		void *buffer, size_t size);

And you can drop this.

> +
> +/* intel_dp_aux_backlight.c */
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
>  
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 8c8996f..cdfcdad 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1718,6 +1718,11 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>  		container_of(panel, struct intel_connector, panel);
>  	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>  
> +	if (i915.enable_dpcd_backlight &&
> +			(connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
> +					intel_dp_aux_init_backlight_funcs(connector) == 0))
> +		return;
> +
>  	if (IS_BROXTON(dev_priv)) {
>  		panel->backlight.setup = bxt_setup_backlight;
>  		panel->backlight.enable = bxt_enable_backlight;

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 3/3] drm/i915: Add backlight Control using DPCD registers for DP connectors

[Jani Nikula]

On Wed, 30 Mar 2016, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote:
> This patch enables support for DPCD backlight control for DP connectors.
> The VESA spec defines DPCD backlight control only for eDP but some add-on
> cards like the Chrontel CH7511B DP-LVDS cards have the display control
> DPCD registers enabled.
> This patch registers a backlight device exposed via sysfs that controls the
> connected panel backlight by writing to DPCD registers on the CH7511B
> add-on card

I'm not convinced. Seems like a gross spec violating hack to work around
the issue that CH7511B is not configured as eDP in the first place.

BR,
Jani.


>
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c               | 25 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp_aux_backlight.c |  7 ++++++
>  drivers/gpu/drm/i915/intel_drv.h              |  2 ++
>  drivers/gpu/drm/i915/intel_panel.c            | 33 +++++++++++++++++++--------
>  4 files changed, 57 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9e9e7f1..8bbfb7f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5631,6 +5631,30 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
>  	return downclock_mode;
>  }
>  
> +/*
> + * Called on DP connector initialization to check for aux backlight control
> + * capability on the sink device and if present, initialize it.
> + */
> +static void intel_dp_init_aux_backlight(struct intel_dp *intel_dp,
> +		struct drm_connector *connector)
> +{
> +	struct intel_connector *intel_connector = to_intel_connector(connector);
> +
> +	if (is_edp(intel_dp))
> +		return;
> +
> +	if (i915.enable_dpcd_backlight &&
> +			(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> +					intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
> +							sizeof(intel_dp->edp_dpcd)) &&
> +							intel_dp_aux_init_backlight_funcs(intel_connector) == 0) {
> +		intel_panel_setup_backlight(connector, INVALID_PIPE);
> +
> +		intel_connector->panel.backlight.power = intel_dp_aux_backlight_power;
> +		intel_connector->panel.backlight.enabled = true;
> +		}
> +}
> +
>  static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  				     struct intel_connector *intel_connector)
>  {
> @@ -5868,6 +5892,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		goto fail;
>  	}
>  
> +	intel_dp_init_aux_backlight(intel_dp, connector);
>  	intel_dp_add_properties(intel_dp, connector);
>  
>  	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index a5361d6..efa657f 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -168,3 +168,10 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
>  
>  	return 0;
>  }
> +
> +void intel_dp_aux_backlight_power(struct intel_connector *connector,
> +				      bool enable)
> +{
> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base),
> +			enable);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 782a103..ab92e89 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1324,6 +1324,8 @@ ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
>  
>  /* intel_dp_aux_backlight.c */
>  int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
> +void intel_dp_aux_backlight_power(struct intel_connector *connector,
> +				      bool enable);
>  
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index cdfcdad..d678e55 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1193,16 +1193,29 @@ static int intel_backlight_device_register(struct intel_connector *connector)
>  	else
>  		props.power = FB_BLANK_POWERDOWN;
>  
> -	/*
> -	 * Note: using the same name independent of the connector prevents
> -	 * registration of multiple backlight devices in the driver.
> -	 */
> -	panel->backlight.device =
> -		backlight_device_register("intel_backlight",
> -					  connector->base.kdev,
> -					  connector,
> -					  &intel_backlight_device_ops, &props);
> -
> +	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
> +		char *name = kasprintf(GFP_KERNEL, "intel_aux_backlight-%s",
> +				connector->base.name);
> +		if (!name)
> +			return -ENOMEM;
> +
> +		panel->backlight.device =
> +			backlight_device_register(name,
> +						  connector->base.kdev,
> +						  connector,
> +						  &intel_backlight_device_ops, &props);
> +			kfree(name);
> +	} else {
> +		/*
> +		 * Note: using the same name independent of the connector prevents
> +		 * registration of multiple backlight devices in the driver.
> +		 */
> +		panel->backlight.device =
> +			backlight_device_register("intel_backlight",
> +						  connector->base.kdev,
> +						  connector,
> +						  &intel_backlight_device_ops, &props);
> +	}
>  	if (IS_ERR(panel->backlight.device)) {
>  		DRM_ERROR("Failed to register backlight: %ld\n",
>  			  PTR_ERR(panel->backlight.device));

-- 
Jani Nikula, Intel Open Source Technology Center
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✓ Fi.CI.BAT: success for DPCD Backlight Control (rev5)

[Patchwork]

== Series Details ==

Series: DPCD Backlight Control (rev5)
URL   : https://patchwork.freedesktop.org/series/1864/
State : success

== Summary ==

Series 1864v5 DPCD Backlight Control
http://patchwork.freedesktop.org/api/1.0/series/1864/revisions/5/mbox/


bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:158  dwarn:1   dfail:0   fail:0   skip:37 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:3    pass:2    dwarn:0   dfail:0   fail:0   skip:0  
skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:85   pass:69   dwarn:0   dfail:0   fail:0   skip:15 

Results at /archive/results/CI_IGT_test/Patchwork_1758/

03c0f854e93263563f559d2bc8e47fb51adae697 drm-intel-nightly: 2016y-03m-31d-10h-50m-15s UTC integration manifest
1e571fdbeaa28ce2b3b943b13c2cfa61e06fc025 drm/i915: Add backlight Control using DPCD registers for DP connectors
f29b8fe12e0b7285774241f53e9ac7239687adc2 drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)
3d25dc84cdec4a5f687c57a434845c123bee7a4a drm/dp: Add definition for Display Control DPCD Registers capability size

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[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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