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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code
Date: Thu, 17 May 2018 20:49:27 +0300	[thread overview]
Message-ID: <87in7m41g8.fsf@intel.com> (raw)
In-Reply-To: <20180517170309.28630-5-ville.syrjala@linux.intel.com>

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> i965 does not have native DP. Let's rename the remaining gen4 references
> in the DP code to g4x.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cd4c60bfc4c2..102070940095 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -56,7 +56,7 @@ struct dp_link_dpll {
>  	struct dpll dpll;
>  };
>  
> -static const struct dp_link_dpll gen4_dpll[] = {
> +static const struct dp_link_dpll g4x_dpll[] = {
>  	{ 162000,
>  		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
>  	{ 270000,
> @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  	int i, count = 0;
>  
>  	if (IS_G4X(dev_priv)) {
> -		divisor = gen4_dpll;
> -		count = ARRAY_SIZE(gen4_dpll);
> +		divisor = g4x_dpll;
> +		count = ARRAY_SIZE(g4x_dpll);
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
> @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  }
>  
>  static uint32_t
> -gen4_signal_levels(uint8_t train_set)
> +g4x_signal_levels(uint8_t train_set)
>  {
>  	uint32_t	signal_levels = 0;
>  
> @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
> -		signal_levels = gen4_signal_levels(train_set);
> +		signal_levels = g4x_signal_levels(train_set);
>  		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-05-17 17:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-17 17:03 [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too Ville Syrjala
2018-05-17 17:03 ` [PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+ Ville Syrjala
2018-05-17 17:42   ` Jani Nikula
2018-05-17 17:03 ` [PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP Ville Syrjala
2018-05-17 17:45   ` Jani Nikula
2018-05-17 17:03 ` [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs Ville Syrjala
2018-05-17 17:48   ` Jani Nikula
2018-05-17 17:50     ` Ville Syrjälä
2018-05-17 17:03 ` [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code Ville Syrjala
2018-05-17 17:49   ` Jani Nikula [this message]
2018-05-18 14:27     ` Ville Syrjälä
2018-05-17 17:40 ` [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too Jani Nikula
2018-05-17 18:16 ` ✓ Fi.CI.BAT: success for series starting with [1/5] " Patchwork
2018-05-17 23:00 ` ✓ Fi.CI.IGT: " Patchwork

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