From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
Date: Thu, 17 May 2018 20:40:00 +0300 [thread overview]
Message-ID: <87tvr641vz.fsf@intel.com> (raw)
In-Reply-To: <20180517170309.28630-1-ville.syrjala@linux.intel.com>
On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
> fall through the if ladder in a weird way. This function will look at
> the actual buf trans tables we have for HSW/BDW to determine the max
> vswing level.
>
> It looks to me like the current code leads HSW port A down the IVB port
> A path, HSW port B+ and BDW fall through to the very end. Both cases do
> result in the correct max vswing level 2, but it's very hard to see that
> from the code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
What a PITA patch to review that there are no functional changes!
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2cc58596ff5a..4755bb1b0b40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3220,12 +3220,12 @@ uint8_t
> intel_dp_voltage_max(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> - enum port port = dp_to_dig_port(intel_dp)->base.port;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + enum port port = encoder->port;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + if (HAS_DDI(dev_priv))
> return intel_ddi_dp_voltage_max(encoder);
> - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev_priv) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2018-05-17 17:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-17 17:03 [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too Ville Syrjala
2018-05-17 17:03 ` [PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+ Ville Syrjala
2018-05-17 17:42 ` Jani Nikula
2018-05-17 17:03 ` [PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP Ville Syrjala
2018-05-17 17:45 ` Jani Nikula
2018-05-17 17:03 ` [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs Ville Syrjala
2018-05-17 17:48 ` Jani Nikula
2018-05-17 17:50 ` Ville Syrjälä
2018-05-17 17:03 ` [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code Ville Syrjala
2018-05-17 17:49 ` Jani Nikula
2018-05-18 14:27 ` Ville Syrjälä
2018-05-17 17:40 ` Jani Nikula [this message]
2018-05-17 18:16 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too Patchwork
2018-05-17 23:00 ` ✓ Fi.CI.IGT: " Patchwork
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