[PATCH 0/6] drm/i915: gvt register macro cleanups, unused macro removals

[PATCH 0/6] drm/i915: gvt register macro cleanups, unused macro removals

[Jani Nikula]

Clean up gvt a bit mainly to be able to remove direct _DSPBSURF
reference, but do some drive-by cleanups on top. And then proceed to
remove _DSPBSURF and other unused register macros.

BR,
Jani.

Jani Nikula (6):
  drm/i915/gvt: remove the unused end parameter from calc_index()
  drm/i915/gvt: use proper i915_reg_t for calc_index() parameters
  drm/i915/gvt: rename range variable to stride
  drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE()
  drm/i915: remove unused pipe/plane B register macros
  drm/i915: remove unused HSW_STEREO_3D_CTL register macros

 drivers/gpu/drm/i915/gvt/handlers.c | 29 +++++++++++++++--------------
 drivers/gpu/drm/i915/i915_reg.h     | 29 -----------------------------
 2 files changed, 15 insertions(+), 43 deletions(-)

-- 
2.39.2

[PATCH 1/6] drm/i915/gvt: remove the unused end parameter from calc_index()

[Jani Nikula]

All callers of calc_index() pass 0 for the end parameter. Remove it.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b3b5fdbee64f..a2e9d24d646e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -882,12 +882,11 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
 #define INVALID_INDEX (~0U)
 
 static unsigned int calc_index(unsigned int offset, unsigned int start,
-	unsigned int next, unsigned int end, i915_reg_t i915_end)
+			       unsigned int next, i915_reg_t _end)
 {
+	u32 end = i915_mmio_reg_offset(_end);
 	unsigned int range = next - start;
 
-	if (!end)
-		end = i915_mmio_reg_offset(i915_end);
 	if (offset < start || offset > end)
 		return INVALID_INDEX;
 	offset -= start;
@@ -895,13 +894,13 @@ static unsigned int calc_index(unsigned int offset, unsigned int start,
 }
 
 #define FDI_RX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
+	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C))
 
 #define FDI_TX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
+	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C))
 
 #define FDI_RX_IMR_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
+	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C))
 
 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 		unsigned int offset, void *p_data, unsigned int bytes)
@@ -945,7 +944,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 }
 
 #define DP_TP_CTL_TO_PORT(offset) \
-	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
+	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E))
 
 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1009,7 +1008,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 }
 
 #define DSPSURF_TO_PIPE(offset) \
-	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C))
+	calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1032,7 +1031,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 #define SPRSURF_TO_PIPE(offset) \
-	calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
+	calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C))
 
 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
-- 
2.39.2

[PATCH 2/6] drm/i915/gvt: use proper i915_reg_t for calc_index() parameters

[Jani Nikula]

In order to be able to use the proper register macros instead of the
underscore prefixed ones, pass i915_reg_t for the calc_index()
parameters.

Side note: DSPSURF is really about planes, not pipes. Fixed stride
doesn't work for plane C for CHV (but that's okay for gvt). This doesn't
support planes beyond C either. But all that is unrelated to the change
at hand.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a2e9d24d646e..b005ab0104ee 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -881,9 +881,11 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
 
 #define INVALID_INDEX (~0U)
 
-static unsigned int calc_index(unsigned int offset, unsigned int start,
-			       unsigned int next, i915_reg_t _end)
+static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
+			       i915_reg_t _next, i915_reg_t _end)
 {
+	u32 start = i915_mmio_reg_offset(_start);
+	u32 next = i915_mmio_reg_offset(_next);
 	u32 end = i915_mmio_reg_offset(_end);
 	unsigned int range = next - start;
 
@@ -894,13 +896,13 @@ static unsigned int calc_index(unsigned int offset, unsigned int start,
 }
 
 #define FDI_RX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C))
+	calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
 
 #define FDI_TX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C))
+	calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
 
 #define FDI_RX_IMR_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C))
+	calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
 
 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 		unsigned int offset, void *p_data, unsigned int bytes)
@@ -944,7 +946,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 }
 
 #define DP_TP_CTL_TO_PORT(offset) \
-	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E))
+	calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
 
 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1008,7 +1010,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 }
 
 #define DSPSURF_TO_PIPE(offset) \
-	calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C))
+	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1031,7 +1033,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 #define SPRSURF_TO_PIPE(offset) \
-	calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C))
+	calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
 
 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
-- 
2.39.2

[PATCH 3/6] drm/i915/gvt: rename range variable to stride

[Jani Nikula]

Range is a bit odd name for what really is stride. Rename. Switch to u32
while at it.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b005ab0104ee..f79dd6cfc75b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -887,12 +887,12 @@ static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
 	u32 start = i915_mmio_reg_offset(_start);
 	u32 next = i915_mmio_reg_offset(_next);
 	u32 end = i915_mmio_reg_offset(_end);
-	unsigned int range = next - start;
+	u32 stride = next - start;
 
 	if (offset < start || offset > end)
 		return INVALID_INDEX;
 	offset -= start;
-	return offset / range;
+	return offset / stride;
 }
 
 #define FDI_RX_CTL_TO_PIPE(offset) \
-- 
2.39.2

[PATCH 4/6] drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE()

[Jani Nikula]

Do not rely on having dev_priv local variable, pass it to the macro.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index f79dd6cfc75b..0f09344d3c20 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1009,14 +1009,14 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 	return 0;
 }
 
-#define DSPSURF_TO_PIPE(offset) \
+#define DSPSURF_TO_PIPE(dev_priv, offset) \
 	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
-	u32 pipe = DSPSURF_TO_PIPE(offset);
+	u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset);
 	int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
 
 	write_vreg(vgpu, offset, p_data, bytes);
-- 
2.39.2

[PATCH 5/6] drm/i915: remove unused pipe/plane B register macros

[Jani Nikula]

None of these are used. The parametrized register macros all depend on
the pipe/plane A offset macros alone. Remove the unused ones.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 23 -----------------------
 1 file changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15ad35178f1a..2d834c32a3fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2214,29 +2214,6 @@
 #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
-/* Pipe B */
-#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
-#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
-#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
-#define _PIPEBFRAMEHIGH		0x71040
-#define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
-
-
-/* Display B control */
-#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
-#define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
-#define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
-#define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
-#define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
-#define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
-#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
-#define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
-#define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-#define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-#define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
-
 /* ICL DSI 0 and 1 */
 #define _PIPEDSI0CONF		0x7b008
 #define _PIPEDSI1CONF		0x7b808
-- 
2.39.2

Re: [PATCH 5/6] drm/i915: remove unused pipe/plane B register macros

[Ville Syrjälä]

On Fri, Jun 07, 2024 at 01:51:28PM +0300, Jani Nikula wrote:
> None of these are used. The parametrized register macros all depend on
> the pipe/plane A offset macros alone. Remove the unused ones.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 23 -----------------------
>  1 file changed, 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 15ad35178f1a..2d834c32a3fa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2214,29 +2214,6 @@
>  #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>  
> -/* Pipe B */
> -#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
> -#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> -#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
> -#define _PIPEBFRAMEHIGH		0x71040
> -#define _PIPEBFRAMEPIXEL	0x71044
> -#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
> -#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
> -

All the _ stuff should go for sure.

> -
> -/* Display B control */
> -#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
> -#define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)

Unlikely we'll ever use this, but if desired we could relocate
this next to all the other DSPCNTR bits. With perhaps a note that
it only applies to plane B.

> -#define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)

This too could be relocated, with a note that it only applies to plane
B/C. Though as far as plane Z order goes I think there's at least one
more bit for that we've not even defined, so this isn't super useful
as is.

> -#define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> -#define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
> -#define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
> -#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
> -#define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
> -#define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -#define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -#define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
> -
>  /* ICL DSI 0 and 1 */
>  #define _PIPEDSI0CONF		0x7b008
>  #define _PIPEDSI1CONF		0x7b808
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 5/6] drm/i915: remove unused pipe/plane B register macros

[Jani Nikula]

On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 07, 2024 at 01:51:28PM +0300, Jani Nikula wrote:
>> None of these are used. The parametrized register macros all depend on
>> the pipe/plane A offset macros alone. Remove the unused ones.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 23 -----------------------
>>  1 file changed, 23 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 15ad35178f1a..2d834c32a3fa 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2214,29 +2214,6 @@
>>  #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>>  
>> -/* Pipe B */
>> -#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
>> -#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
>> -#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
>> -#define _PIPEBFRAMEHIGH		0x71040
>> -#define _PIPEBFRAMEPIXEL	0x71044
>> -#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
>> -#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
>> -
>
> All the _ stuff should go for sure.
>
>> -
>> -/* Display B control */
>> -#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
>> -#define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
>
> Unlikely we'll ever use this, but if desired we could relocate
> this next to all the other DSPCNTR bits. With perhaps a note that
> it only applies to plane B.

Huh. I can't actually find a platform where bit 15 would be "alpha trans
enable". It's either 180 degree rotation or decompression of compressed
surfaces.

>> -#define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
>
> This too could be relocated, with a note that it only applies to plane
> B/C. Though as far as plane Z order goes I think there's at least one
> more bit for that we've not even defined, so this isn't super useful
> as is.

And here it's either reserved or relocated rotation in bits 0-1.

What am I missing?

BR,
Jani.


>
>> -#define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
>> -#define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>> -#define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>> -#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>> -#define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>> -#define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>> -#define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>> -#define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
>> -
>>  /* ICL DSI 0 and 1 */
>>  #define _PIPEDSI0CONF		0x7b008
>>  #define _PIPEDSI1CONF		0x7b808
>> -- 
>> 2.39.2

-- 
Jani Nikula, Intel

Re: [PATCH 5/6] drm/i915: remove unused pipe/plane B register macros

[Ville Syrjälä]

On Fri, Jun 07, 2024 at 03:12:40PM +0300, Jani Nikula wrote:
> On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Jun 07, 2024 at 01:51:28PM +0300, Jani Nikula wrote:
> >> None of these are used. The parametrized register macros all depend on
> >> the pipe/plane A offset macros alone. Remove the unused ones.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 23 -----------------------
> >>  1 file changed, 23 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 15ad35178f1a..2d834c32a3fa 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2214,29 +2214,6 @@
> >>  #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
> >>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
> >>  
> >> -/* Pipe B */
> >> -#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
> >> -#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> >> -#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
> >> -#define _PIPEBFRAMEHIGH		0x71040
> >> -#define _PIPEBFRAMEPIXEL	0x71044
> >> -#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
> >> -#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
> >> -
> >
> > All the _ stuff should go for sure.
> >
> >> -
> >> -/* Display B control */
> >> -#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
> >> -#define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
> >
> > Unlikely we'll ever use this, but if desired we could relocate
> > this next to all the other DSPCNTR bits. With perhaps a note that
> > it only applies to plane B.
> 
> Huh. I can't actually find a platform where bit 15 would be "alpha trans
> enable". It's either 180 degree rotation or decompression of compressed
> surfaces.
> 
> >> -#define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
> >
> > This too could be relocated, with a note that it only applies to plane
> > B/C. Though as far as plane Z order goes I think there's at least one
> > more bit for that we've not even defined, so this isn't super useful
> > as is.
> 
> And here it's either reserved or relocated rotation in bits 0-1.
> 
> What am I missing?

These only exist on gen2/3. i965 plane C still has the other
Z order bit (2) that we haven't defined hus far. And by g4x
it's all gone since plane C is also gone.

-- 
Ville Syrjälä
Intel

[PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Jani Nikula]

Remove the unused HSW_STEREO_3D_CTL register macros.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d834c32a3fa..127b113189ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3385,12 +3385,6 @@
 #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
 							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
 
-#define _HSW_STEREO_3D_CTL_A		0x70020
-#define   S3D_ENABLE			(1 << 31)
-#define _HSW_STEREO_3D_CTL_B		0x71020
-
-#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
-
 #define _PCH_TRANS_HTOTAL_B          0xe1000
 #define _PCH_TRANS_HBLANK_B          0xe1004
 #define _PCH_TRANS_HSYNC_B           0xe1008
-- 
2.39.2

Re: [PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Ville Syrjälä]

On Fri, Jun 07, 2024 at 01:51:29PM +0300, Jani Nikula wrote:
> Remove the unused HSW_STEREO_3D_CTL register macros.

I don't enjoy having to trawl the specs to find registers.
So I prefer to keep everything that isn't actually wrong.

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2d834c32a3fa..127b113189ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3385,12 +3385,6 @@
>  #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
>  							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
>  
> -#define _HSW_STEREO_3D_CTL_A		0x70020
> -#define   S3D_ENABLE			(1 << 31)
> -#define _HSW_STEREO_3D_CTL_B		0x71020
> -
> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
> -
>  #define _PCH_TRANS_HTOTAL_B          0xe1000
>  #define _PCH_TRANS_HBLANK_B          0xe1004
>  #define _PCH_TRANS_HSYNC_B           0xe1008
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Jani Nikula]

On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 07, 2024 at 01:51:29PM +0300, Jani Nikula wrote:
>> Remove the unused HSW_STEREO_3D_CTL register macros.
>
> I don't enjoy having to trawl the specs to find registers.
> So I prefer to keep everything that isn't actually wrong.

Shall I apply this [1] then?

BR,
Jani.


[1] https://lore.kernel.org/r/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com


>
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 6 ------
>>  1 file changed, 6 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 2d834c32a3fa..127b113189ef 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3385,12 +3385,6 @@
>>  #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
>>  							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
>>  
>> -#define _HSW_STEREO_3D_CTL_A		0x70020
>> -#define   S3D_ENABLE			(1 << 31)
>> -#define _HSW_STEREO_3D_CTL_B		0x71020
>> -
>> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
>> -
>>  #define _PCH_TRANS_HTOTAL_B          0xe1000
>>  #define _PCH_TRANS_HBLANK_B          0xe1004
>>  #define _PCH_TRANS_HSYNC_B           0xe1008
>> -- 
>> 2.39.2

-- 
Jani Nikula, Intel

Re: [PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Rodrigo Vivi]

On Fri, Jun 07, 2024 at 03:21:22PM +0300, Jani Nikula wrote:
> On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Jun 07, 2024 at 01:51:29PM +0300, Jani Nikula wrote:
> >> Remove the unused HSW_STEREO_3D_CTL register macros.
> >
> > I don't enjoy having to trawl the specs to find registers.

I really doubt that this register will be ever useful for anything.
IIRC it was not even useful when we introduced it.

> > So I prefer to keep everything that isn't actually wrong.

on this side we could just get the autogenerated headers from spec
and dump them all here with all the bits, is this what we really want?

> 
> Shall I apply this [1] then?

ack from my side on either way.

> 
> BR,
> Jani.
> 
> 
> [1] https://lore.kernel.org/r/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com
> 
> 
> >
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 6 ------
> >>  1 file changed, 6 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 2d834c32a3fa..127b113189ef 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -3385,12 +3385,6 @@
> >>  #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
> >>  							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
> >>  
> >> -#define _HSW_STEREO_3D_CTL_A		0x70020
> >> -#define   S3D_ENABLE			(1 << 31)
> >> -#define _HSW_STEREO_3D_CTL_B		0x71020
> >> -
> >> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
> >> -
> >>  #define _PCH_TRANS_HTOTAL_B          0xe1000
> >>  #define _PCH_TRANS_HBLANK_B          0xe1004
> >>  #define _PCH_TRANS_HSYNC_B           0xe1008
> >> -- 
> >> 2.39.2
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Ville Syrjälä]

On Fri, Jun 07, 2024 at 03:21:22PM +0300, Jani Nikula wrote:
> On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Jun 07, 2024 at 01:51:29PM +0300, Jani Nikula wrote:
> >> Remove the unused HSW_STEREO_3D_CTL register macros.
> >
> > I don't enjoy having to trawl the specs to find registers.
> > So I prefer to keep everything that isn't actually wrong.
> 
> Shall I apply this [1] then?

Works for me.

> 
> BR,
> Jani.
> 
> 
> [1] https://lore.kernel.org/r/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com
> 
> 
> >
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 6 ------
> >>  1 file changed, 6 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 2d834c32a3fa..127b113189ef 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -3385,12 +3385,6 @@
> >>  #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
> >>  							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
> >>  
> >> -#define _HSW_STEREO_3D_CTL_A		0x70020
> >> -#define   S3D_ENABLE			(1 << 31)
> >> -#define _HSW_STEREO_3D_CTL_B		0x71020
> >> -
> >> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
> >> -
> >>  #define _PCH_TRANS_HTOTAL_B          0xe1000
> >>  #define _PCH_TRANS_HBLANK_B          0xe1004
> >>  #define _PCH_TRANS_HSYNC_B           0xe1008
> >> -- 
> >> 2.39.2
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 6/6] drm/i915: remove unused HSW_STEREO_3D_CTL register macros

[Jani Nikula]

On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 07, 2024 at 03:21:22PM +0300, Jani Nikula wrote:
>> On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Fri, Jun 07, 2024 at 01:51:29PM +0300, Jani Nikula wrote:
>> >> Remove the unused HSW_STEREO_3D_CTL register macros.
>> >
>> > I don't enjoy having to trawl the specs to find registers.
>> > So I prefer to keep everything that isn't actually wrong.
>> 
>> Shall I apply this [1] then?
>
> Works for me.

Thanks, pushed that one to din.

BR,
Jani.

>
>> 
>> BR,
>> Jani.
>> 
>> 
>> [1] https://lore.kernel.org/r/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com
>> 
>> 
>> >
>> >> 
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/i915_reg.h | 6 ------
>> >>  1 file changed, 6 deletions(-)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >> index 2d834c32a3fa..127b113189ef 100644
>> >> --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> @@ -3385,12 +3385,6 @@
>> >>  #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)	_MMIO_TRANS2(dev_priv, trans,\
>> >>  							     _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
>> >>  
>> >> -#define _HSW_STEREO_3D_CTL_A		0x70020
>> >> -#define   S3D_ENABLE			(1 << 31)
>> >> -#define _HSW_STEREO_3D_CTL_B		0x71020
>> >> -
>> >> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
>> >> -
>> >>  #define _PCH_TRANS_HTOTAL_B          0xe1000
>> >>  #define _PCH_TRANS_HBLANK_B          0xe1004
>> >>  #define _PCH_TRANS_HSYNC_B           0xe1008
>> >> -- 
>> >> 2.39.2
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915: gvt register macro cleanups, unused macro removals

[Patchwork]

== Series Details ==

Series: drm/i915: gvt register macro cleanups, unused macro removals
URL   : https://patchwork.freedesktop.org/series/134600/
State : warning

== Summary ==

Error: dim checkpatch failed
66e6c4a777e0 drm/i915/gvt: remove the unused end parameter from calc_index()
0e196fd9ff22 drm/i915/gvt: use proper i915_reg_t for calc_index() parameters
-:70: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#70: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1013:
+	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))

total: 0 errors, 1 warnings, 0 checks, 53 lines checked
885bb125a4fc drm/i915/gvt: rename range variable to stride
b0aea21a9558 drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE()
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1012:
+#define DSPSURF_TO_PIPE(dev_priv, offset) \
 	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))

total: 0 errors, 0 warnings, 1 checks, 16 lines checked
479736242c74 drm/i915: remove unused pipe/plane B register macros
f647ac1c5917 drm/i915: remove unused HSW_STEREO_3D_CTL register macros

✓ Fi.CI.BAT: success for drm/i915: gvt register macro cleanups, unused macro removals

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2980 bytes --]

== Series Details ==

Series: drm/i915: gvt register macro cleanups, unused macro removals
URL   : https://patchwork.freedesktop.org/series/134600/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14898 -> Patchwork_134600v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134600v1/index.html

Participating hosts (41 -> 34)
------------------------------

  Missing    (7): bat-dg1-7 bat-adlp-9 bat-adlp-6 fi-snb-2520m fi-cfl-8109u bat-dg2-14 bat-dg2-11 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_134600v1:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-dp-8:
    - {bat-mtlp-9}:       NOTRUN -> [FAIL][1] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134600v1/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-dp-8.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-6:
    - {bat-mtlp-9}:       [DMESG-FAIL][2] ([i915#11009]) -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14898/bat-mtlp-9/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-6.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134600v1/bat-mtlp-9/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-6.html

  
Known issues
------------

  Here are the changes found in Patchwork_134600v1 that come from known issues:

### IGT changes ###

  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
  [i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
  [i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
  [i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
  [i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159


Build changes
-------------

  * Linux: CI_DRM_14898 -> Patchwork_134600v1

  CI-20190529: 20190529
  CI_DRM_14898: d9550a18e990d5709c4bc33073842a3c0a8bcaea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7880: 73618605b4370cf902267aaf1d25666ff5e26112 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_134600v1: d9550a18e990d5709c4bc33073842a3c0a8bcaea @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134600v1/index.html

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