From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Michel Thierry <michel.thierry@intel.com>
Subject: Re: [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12
Date: Thu, 22 Aug 2019 16:31:53 +0300 [thread overview]
Message-ID: <87tva92unq.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20190817093902.2171-24-lucas.demarchi@intel.com>
Lucas De Marchi <lucas.demarchi@intel.com> writes:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Gen12 has subtle changes in the reg state context offsets (some fields
> are gone, some are in a different location), compared to previous Gens.
>
> The simplest approach seems to be keeping Gen12 (and future platform)
> changes apart from the previous gens, while keeping the registers that
> are contiguous in functions we can reuse.
>
> Bspec: 20202
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +++++++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 30 ++++-
> 3 files changed, 143 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e30d2a892f29..1fe83736f064 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3068,28 +3068,12 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> return indirect_ctx_offset;
> }
>
> -static void execlists_init_reg_state(u32 *regs,
> - struct intel_context *ce,
> - struct intel_engine_cs *engine,
> - struct intel_ring *ring)
> +static void init_common_reg_state(u32 *regs,
> + struct intel_engine_cs *engine,
> + struct intel_ring *ring)
> {
> - struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
> - bool rcs = engine->class == RENDER_CLASS;
> u32 base = engine->mmio_base;
>
> - /*
> - * A context is actually a big batch buffer with several
> - * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
> - * values we are setting here are only for the first context restore:
> - * on a subsequent save, the GPU will recreate this batchbuffer with new
> - * values (including all the missing MI_LOAD_REGISTER_IMM commands that
> - * we are not initializing here).
> - *
> - * Must keep consistent with virtual_update_register_offsets().
> - */
> - regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
> - MI_LRI_FORCE_POSTED;
> -
> CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
> _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
> _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
> @@ -3106,38 +3090,44 @@ static void execlists_init_reg_state(u32 *regs,
> CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
> CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
> CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
> - CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
> - CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
> - CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
> - if (rcs) {
> - struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
> -
> - CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
> - CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
> - RING_INDIRECT_CTX_OFFSET(base), 0);
> - if (wa_ctx->indirect_ctx.size) {
> - u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
> +}
>
> - regs[CTX_RCS_INDIRECT_CTX + 1] =
> - (ggtt_offset + wa_ctx->indirect_ctx.offset) |
> - (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
> +static void init_wa_bb_reg_state(u32 *regs,
> + struct intel_engine_cs *engine,
> + u32 pos_bb_per_ctx)
> +{
> + struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
> + u32 base = engine->mmio_base;
> + u32 pos_indirect_ctx = pos_bb_per_ctx + 2;
> + u32 pos_indirect_ctx_offset = pos_indirect_ctx + 2;
>
> - regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
> - intel_lr_indirect_ctx_offset(engine) << 6;
> - }
> + GEM_BUG_ON(engine->id != RCS0);
> + CTX_REG(regs, pos_indirect_ctx, RING_INDIRECT_CTX(base), 0);
> + CTX_REG(regs, pos_indirect_ctx_offset,
> + RING_INDIRECT_CTX_OFFSET(base), 0);
> + if (wa_ctx->indirect_ctx.size) {
> + u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
>
> - CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
> - if (wa_ctx->per_ctx.size) {
> - u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
> + regs[pos_indirect_ctx + 1] =
> + (ggtt_offset + wa_ctx->indirect_ctx.offset) |
> + (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
>
> - regs[CTX_BB_PER_CTX_PTR + 1] =
> - (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
> - }
> + regs[pos_indirect_ctx_offset + 1] =
> + intel_lr_indirect_ctx_offset(engine) << 6;
> }
>
> - regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
> + CTX_REG(regs, pos_bb_per_ctx, RING_BB_PER_CTX_PTR(base), 0);
> + if (wa_ctx->per_ctx.size) {
> + u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
>
> - CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
> + regs[pos_bb_per_ctx + 1] =
> + (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
> + }
> +}
> +
> +static void init_ppgtt_reg_state(u32 *regs, u32 base,
> + struct i915_ppgtt *ppgtt)
> +{
> /* PDP values well be assigned later if needed */
> CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
> CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
> @@ -3160,6 +3150,32 @@ static void execlists_init_reg_state(u32 *regs,
> ASSIGN_CTX_PDP(ppgtt, regs, 1);
> ASSIGN_CTX_PDP(ppgtt, regs, 0);
> }
> +}
> +
> +static void gen8_init_reg_state(u32 *regs,
> + struct intel_context *ce,
> + struct intel_engine_cs *engine,
> + struct intel_ring *ring)
> +{
> + struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
> + bool rcs = engine->class == RENDER_CLASS;
> + u32 base = engine->mmio_base;
> +
> + regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
> + MI_LRI_FORCE_POSTED;
It could be better that the imm batch size would be contained
in the actual helper which does it. But as this would change
the imm sizes, let's not go there, atleast not yet until
everything is green on CI.
But the confusion I have is with the virtual engines.
According to comments the virtual engine reg state setup
has to mimic the execlist one exactly. With this
gen12/gen8 split, we break the symmetry. Do we
need same split in there?
-Mika
> +
> + init_common_reg_state(regs, engine, ring);
> + CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
> + CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
> + CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
> + if (rcs)
> + init_wa_bb_reg_state(regs, engine, CTX_BB_PER_CTX_PTR);
> +
> + regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
> +
> + CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
> +
> + init_ppgtt_reg_state(regs, base, ppgtt);
>
> if (rcs) {
> regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> @@ -3171,6 +3187,58 @@ static void execlists_init_reg_state(u32 *regs,
> regs[CTX_END] |= BIT(0);
> }
>
> +static void gen12_init_reg_state(u32 *regs,
> + struct intel_context *ce,
> + struct intel_engine_cs *engine,
> + struct intel_ring *ring)
> +{
> + struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
> + bool rcs = engine->class == RENDER_CLASS;
> + u32 base = engine->mmio_base;
> +
> + GEM_DEBUG_EXEC(DRM_INFO_ONCE("Using GEN12 Register State Context\n"));
> +
> + regs[GEN12_CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(13) |
> + MI_LRI_FORCE_POSTED;
> +
> + init_common_reg_state(regs, engine, ring);
> + if (rcs)
> + init_wa_bb_reg_state(regs, engine, GEN12_CTX_BB_PER_CTX_PTR);
> +
> + regs[GEN12_CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) |
> + MI_LRI_FORCE_POSTED;
> +
> + CTX_REG(regs, GEN12_CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
> +
> + init_ppgtt_reg_state(regs, base, ppgtt);
> +
> + if (rcs) {
> + regs[GEN12_CTX_LRI_HEADER_3] = MI_LOAD_REGISTER_IMM(1);
> + CTX_REG(regs, GEN12_CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
> + 0);
> +
> + /* TODO: oa_init_reg_state ? */
> + }
> +}
> +
> +static void execlists_init_reg_state(u32 *regs,
> + struct intel_context *ce,
> + struct intel_engine_cs *engine,
> + struct intel_ring *ring)
> +{
> + /* A context is actually a big batch buffer with several
> + * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
> + * values we are setting here are only for the first context restore:
> + * on a subsequent save, the GPU will recreate this batchbuffer with new
> + * values (including all the missing MI_LOAD_REGISTER_IMM commands that
> + * we are not initializing here).
> + */
> + if (INTEL_GEN(engine->i915) >= 12)
> + gen12_init_reg_state(regs, ce, engine, ring);
> + else
> + gen8_init_reg_state(regs, ce, engine, ring);
> +}
> +
> static int
> populate_lr_context(struct intel_context *ce,
> struct drm_i915_gem_object *ctx_obj,
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index c2bba82bcc16..69285d354d9b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -49,6 +49,8 @@ struct intel_engine_cs;
>
> #define EL_CTRL_LOAD (1 << 0)
>
> +#define GEN12_ENGINE_SEMAPHORE_TOKEN(engine) _MMIO((engine)->mmio_base + 0x2b4)
> +
> /* The docs specify that the write pointer wraps around after 5h, "After status
> * is written out to the last available status QW at offset 5h, this pointer
> * wraps to 0."
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> index 6bf34738b4e5..915824ebaf17 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> @@ -9,7 +9,7 @@
>
> #include <linux/types.h>
>
> -/* GEN8+ Reg State Context */
> +/* GEN8 to GEN11 Reg State Context */
> #define CTX_LRI_HEADER_0 0x01
> #define CTX_CONTEXT_CONTROL 0x02
> #define CTX_RING_HEAD 0x04
> @@ -39,6 +39,34 @@
> #define CTX_R_PWR_CLK_STATE 0x42
> #define CTX_END 0x44
>
> +/* GEN12+ Reg State Context */
> +#define GEN12_CTX_LRI_HEADER_0 CTX_LRI_HEADER_0
> +#define GEN12_CTX_CONTEXT_CONTROL CTX_CONTEXT_CONTROL
> +#define GEN12_CTX_RING_HEAD CTX_RING_HEAD
> +#define GEN12_CTX_RING_TAIL CTX_RING_TAIL
> +#define GEN12_CTX_RING_BUFFER_START CTX_RING_BUFFER_START
> +#define GEN12_CTX_RING_BUFFER_CONTROL CTX_RING_BUFFER_CONTROL
> +#define GEN12_CTX_BB_HEAD_U CTX_BB_HEAD_U
> +#define GEN12_CTX_BB_HEAD_L CTX_BB_HEAD_L
> +#define GEN12_CTX_BB_STATE CTX_BB_STATE
> +#define GEN12_CTX_BB_PER_CTX_PTR 0x12
> +#define GEN12_CTX_RCS_INDIRECT_CTX 0x14
> +#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET 0x16
> +#define GEN12_CTX_LRI_HEADER_1 CTX_LRI_HEADER_1
> +#define GEN12_CTX_CTX_TIMESTAMP CTX_CTX_TIMESTAMP
> +#define GEN12_CTX_PDP3_UDW CTX_PDP3_UDW
> +#define GEN12_CTX_PDP3_LDW CTX_PDP3_LDW
> +#define GEN12_CTX_PDP2_UDW CTX_PDP2_UDW
> +#define GEN12_CTX_PDP2_LDW CTX_PDP2_LDW
> +#define GEN12_CTX_PDP1_UDW CTX_PDP1_UDW
> +#define GEN12_CTX_PDP1_LDW CTX_PDP1_LDW
> +#define GEN12_CTX_PDP0_UDW CTX_PDP0_UDW
> +#define GEN12_CTX_PDP0_LDW CTX_PDP0_LDW
> +#define GEN12_CTX_LRI_HEADER_2 0x34
> +#define GEN12_CTX_LRI_HEADER_3 0x41
> +#define GEN12_CTX_R_PWR_CLK_STATE 0x42
> +#define GEN12_CTX_GPGPU_CSR_BASE_ADDRESS 0x44
> +
> #define CTX_REG(reg_state, pos, reg, val) do { \
> u32 *reg_state__ = (reg_state); \
> const u32 pos__ = (pos); \
> --
> 2.21.0
>
> _______________________________________________
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next prev parent reply other threads:[~2019-08-22 14:31 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 9:38 [PATCH v2 00/40] Tiger Lake batch 3 Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 01/40] drm/i915/tgl: disable DDIC Lucas De Marchi
2019-08-19 17:16 ` Matt Roper
2019-08-17 9:38 ` [PATCH v2 02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi
2019-08-19 11:59 ` Imre Deak
2019-08-17 9:38 ` [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi
2019-08-19 17:55 ` Srivatsa, Anusha
2019-08-19 18:03 ` Lucas De Marchi
2019-08-19 18:07 ` Srivatsa, Anusha
2019-08-17 9:38 ` [PATCH v2 05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-20 20:16 ` Lucas De Marchi
2019-08-20 21:15 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-20 20:19 ` Lucas De Marchi
2019-08-21 14:50 ` Ville Syrjälä
2019-08-17 9:38 ` [PATCH v2 07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-20 20:29 ` Lucas De Marchi
2019-08-20 22:20 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-21 13:13 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-21 11:22 ` Kahola, Mika
2019-08-21 13:32 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-21 11:29 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-22 12:43 ` Jani Nikula
2019-08-22 16:44 ` Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-20 20:54 ` Lucas De Marchi
2019-08-21 9:16 ` Ye, Tony
2019-08-17 9:38 ` [PATCH v2 22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-20 23:29 ` Summers, Stuart
2019-08-22 0:25 ` Summers, Stuart
2019-08-17 9:38 ` [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-21 21:12 ` Daniele Ceraolo Spurio
2019-08-22 13:31 ` Mika Kuoppala [this message]
2019-08-22 14:51 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 24/40] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-20 22:01 ` [PATCH v2] " José Roberto de Souza
2019-08-20 23:07 ` Manasi Navare
2019-08-21 20:22 ` Souza, Jose
[not found] ` <20190821213233.1067-1-jose.souza@intel.com>
2019-08-22 11:00 ` [PATCH v3] " Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-20 10:36 ` Chris Wilson
2019-08-22 13:42 ` Mika Kuoppala
2019-08-22 13:48 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-21 14:43 ` Lisovskiy, Stanislav
2019-08-17 9:38 ` [PATCH v2 29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-20 20:43 ` Lucas De Marchi
2019-08-22 13:28 ` Mika Kuoppala
2019-08-23 0:44 ` Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-20 10:33 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-21 12:36 ` Lionel Landwerlin
2019-08-17 9:38 ` [PATCH v2 34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-21 14:34 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-17 9:39 ` [PATCH v2 39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-21 14:40 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 40/40] drm/i915/tgl: " Lucas De Marchi
2019-08-21 14:36 ` Lisovskiy, Stanislav
2019-08-17 9:49 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev2) Patchwork
2019-08-17 10:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-17 10:12 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 10:28 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev3) Patchwork
2019-08-20 10:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-20 12:15 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 12:36 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-20 17:59 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-20 22:30 ` ✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev4) Patchwork
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