[PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Nemesa Garg]

Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL
on plane disable") started clearing SEL_FETCH_PLANE_CTL and
SEL_FETCH_CUR_CTL on every plane and cursor disable.

Not all pipes implement these registers. Clearing them on a pipe
that does not have them leads to an unclaimed register access.

Skip the clear on pipes that do not implement the registers.

Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable")
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876
Assisted-by: GitHub-Copilot:claude-opus-4.6
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cursor.c        | 4 ++++
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 86bb96ac449b..3c06d5482691 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -544,6 +544,10 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
 	if (!HAS_PSR2_SEL_FETCH(display))
 		return;
 
+	/* Display ver 12 only instantiates these registers for pipe A */
+	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
+		return;
+
 	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 5cda1ab90e40..252df30debc9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
 	if (!HAS_PSR2_SEL_FETCH(display))
 		return;
 
+	/* Display ver 12 only instantiates these registers for pipe A */
+	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
+		return;
+
 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
 }
 
-- 
2.25.1

Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch adds a check to prevent unclaimed register accesses for uninstantiated SEL_FETCH registers, but incorrectly limits this check strictly to Display Ver 12, leaving Ver 13+ platforms vulnerable.
--

commit 5a2a4e5321d7248032644f135d53b64d20ede511
Author: Nemesa Garg <nemesa.garg@intel.com>

drm/i915/display: Limit SEL_FETCH clear to supported pipes

This patch adds checks to skip clearing SEL_FETCH_PLANE_CTL and
SEL_FETCH_CUR_CTL on pipes that do not implement these registers,
preventing unclaimed register accesses when disabling planes and cursors.

> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index cce041e1da51d..de4359cbe306d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -545,6 +545,10 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +

[Severity: Medium]
Does this check leave Display Ver 13+ platforms vulnerable to the same issue?

Because PSR2 is only supported on transcoders A and B on newer platforms
(like Alderlake P), the SEL_FETCH registers for pipes C and D are not
instantiated. 

With this check strictly limited to DISPLAY_VER(display) == 12, disabling a
cursor on pipe C or D on Ver 13+ will evaluate to false, bypass this
protection, and still cause an unclaimed register access.

>  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 5cda1ab90e40f..252df30debc9b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +

[Severity: Medium]
Similarly for planes, does limiting this check to exactly Ver 12 allow
unclaimed register accesses on Ver 13+?

Disabling a plane on pipe C or D on a Display Ver 13+ platform will also bypass
this check and attempt to write to uninstantiated SEL_FETCH registers.

>  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
>  }
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904062744.3010375-1-nemesa.garg@intel.com?part=1

Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Jani Nikula]

On Fri, 04 Sep 2026, Nemesa Garg <nemesa.garg@intel.com> wrote:
> Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL
> on plane disable") started clearing SEL_FETCH_PLANE_CTL and
> SEL_FETCH_CUR_CTL on every plane and cursor disable.
>
> Not all pipes implement these registers. Clearing them on a pipe
> that does not have them leads to an unclaimed register access.

Where are the corresponding checks on the enable side, and what
prevented this before 7f1172a2ac0d?

BR,
Jani.

>
> Skip the clear on pipes that do not implement the registers.
>
> Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable")
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876
> Assisted-by: GitHub-Copilot:claude-opus-4.6
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cursor.c        | 4 ++++
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 86bb96ac449b..3c06d5482691 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -544,6 +544,10 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +
>  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 5cda1ab90e40..252df30debc9 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +
>  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
>  }

-- 
Jani Nikula, Intel

RE: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Garg, Nemesa]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, September 4, 2026 12:41 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported
> pipes
> 
> On Fri, 04 Sep 2026, Nemesa Garg <nemesa.garg@intel.com> wrote:
> > Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on
> > plane disable") started clearing SEL_FETCH_PLANE_CTL and
> > SEL_FETCH_CUR_CTL on every plane and cursor disable.
> >
> > Not all pipes implement these registers. Clearing them on a pipe that
> > does not have them leads to an unclaimed register access.
> 
> Where are the corresponding checks on the enable side, and what prevented
> this before 7f1172a2ac0d?
> 
I will send a new patch where I am checking if its enabled then only we should disable it otherwise
no action needed.

Thanks and Regards,
Nemesa

> BR,
> Jani.
> 
> >
> > Skip the clear on pipes that do not implement the registers.
> >
> > Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on
> > plane disable")
> > Closes:
> > https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876
> > Assisted-by: GitHub-Copilot:claude-opus-4.6
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cursor.c        | 4 ++++
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index 86bb96ac449b..3c06d5482691 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -544,6 +544,10 @@ static void
> i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
> >  	if (!HAS_PSR2_SEL_FETCH(display))
> >  		return;
> >
> > +	/* Display ver 12 only instantiates these registers for pipe A */
> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> > +		return;
> > +
> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);  }
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 5cda1ab90e40..252df30debc9 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct
> intel_dsb *dsb,
> >  	if (!HAS_PSR2_SEL_FETCH(display))
> >  		return;
> >
> > +	/* Display ver 12 only instantiates these registers for pipe A */
> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> > +		return;
> > +
> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
> > plane->id), 0);  }
> 
> --
> Jani Nikula, Intel

RE: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Jani Nikula]

On Mon, 07 Sep 2026, "Garg, Nemesa" <nemesa.garg@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Friday, September 4, 2026 12:41 PM
>> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org;
>> intel-xe@lists.freedesktop.org
>> Cc: Garg, Nemesa <nemesa.garg@intel.com>
>> Subject: Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported
>> pipes
>> 
>> On Fri, 04 Sep 2026, Nemesa Garg <nemesa.garg@intel.com> wrote:
>> > Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on
>> > plane disable") started clearing SEL_FETCH_PLANE_CTL and
>> > SEL_FETCH_CUR_CTL on every plane and cursor disable.
>> >
>> > Not all pipes implement these registers. Clearing them on a pipe that
>> > does not have them leads to an unclaimed register access.
>> 
>> Where are the corresponding checks on the enable side, and what prevented
>> this before 7f1172a2ac0d?
>> 
> I will send a new patch where I am checking if its enabled then only we should disable it otherwise
> no action needed.

That doesn't really answer my question, does it?

BR,
Jani.


>
> Thanks and Regards,
> Nemesa
>
>> BR,
>> Jani.
>> 
>> >
>> > Skip the clear on pipes that do not implement the registers.
>> >
>> > Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on
>> > plane disable")
>> > Closes:
>> > https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876
>> > Assisted-by: GitHub-Copilot:claude-opus-4.6
>> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_cursor.c        | 4 ++++
>> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++
>> >  2 files changed, 8 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
>> > b/drivers/gpu/drm/i915/display/intel_cursor.c
>> > index 86bb96ac449b..3c06d5482691 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
>> > @@ -544,6 +544,10 @@ static void
>> i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
>> >  	if (!HAS_PSR2_SEL_FETCH(display))
>> >  		return;
>> >
>> > +	/* Display ver 12 only instantiates these registers for pipe A */
>> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
>> > +		return;
>> > +
>> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);  }
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > index 5cda1ab90e40..252df30debc9 100644
>> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct
>> intel_dsb *dsb,
>> >  	if (!HAS_PSR2_SEL_FETCH(display))
>> >  		return;
>> >
>> > +	/* Display ver 12 only instantiates these registers for pipe A */
>> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
>> > +		return;
>> > +
>> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
>> > plane->id), 0);  }
>> 
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Garg, Nemesa]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, September 7, 2026 3:27 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported
> pipes
> 
> On Mon, 07 Sep 2026, "Garg, Nemesa" <nemesa.garg@intel.com> wrote:
> >> -----Original Message-----
> >> From: Jani Nikula <jani.nikula@linux.intel.com>
> >> Sent: Friday, September 4, 2026 12:41 PM
> >> To: Garg, Nemesa <nemesa.garg@intel.com>;
> >> intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> >> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> >> Subject: Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to
> >> supported pipes
> >>
> >> On Fri, 04 Sep 2026, Nemesa Garg <nemesa.garg@intel.com> wrote:
> >> > Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL
> >> > on plane disable") started clearing SEL_FETCH_PLANE_CTL and
> >> > SEL_FETCH_CUR_CTL on every plane and cursor disable.
> >> >
> >> > Not all pipes implement these registers. Clearing them on a pipe
> >> > that does not have them leads to an unclaimed register access.
> >>
> >> Where are the corresponding checks on the enable side, and what
> >> prevented this before 7f1172a2ac0d?
> >>
> > I will send a new patch where I am checking if its enabled then only
> > we should disable it otherwise no action needed.
> 
> That doesn't really answer my question, does it?
> 
On enable side it is icl_plane_update_sel_fetch_arm() and i9xx_cursor_update_sel_fetch_arm() where we are checking crtc_state->enable_psr2_sel_fetch and it  is true  on a pipe that actually drives selective fetch.
 
The same flag is what prevented this before 7f1172a2ac0d: the disable
 helpers checked it too, so enable and disable were symmetric.

The problem with this the was, whenever there is a internal commit from test of enabling crc this flag was setting to false as crc and enable_psr2_sel_fetch  cannot be true at same time. So during plane disable phase SEL_FETCH bit was not setting to 0 because the flag is false and it returns early. So to handle this added HAS_PSR2_SEL_FETCH check was added.

And with this commit 7f1172a2ac0d the unclaimed read access issue started coming as this check was  getting called unconditionally and so the disable path now writes the registers on
every pipe of a display 12+ platform, including pipes that do not implement them.

So to avoid all this , came up with new approach where adding a new function for clearing the bit for the inactive planes of the pipe as selective fetch is turned on

Thanks and Regards,
Nemesa

> BR,
> Jani.
> 
> 
> >
> > Thanks and Regards,
> > Nemesa
> >
> >> BR,
> >> Jani.
> >>
> >> >
> >> > Skip the clear on pipes that do not implement the registers.
> >> >
> >> > Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL
> >> > on plane disable")
> >> > Closes:
> >> > https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876
> >> > Assisted-by: GitHub-Copilot:claude-opus-4.6
> >> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_cursor.c        | 4 ++++
> >> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++
> >> >  2 files changed, 8 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> >> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> >> > index 86bb96ac449b..3c06d5482691 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> >> > @@ -544,6 +544,10 @@ static void
> >> i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
> >> >  	if (!HAS_PSR2_SEL_FETCH(display))
> >> >  		return;
> >> >
> >> > +	/* Display ver 12 only instantiates these registers for pipe A */
> >> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> >> > +		return;
> >> > +
> >> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);  }
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> > index 5cda1ab90e40..252df30debc9 100644
> >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> > @@ -893,6 +893,10 @@ static void
> >> > icl_plane_disable_sel_fetch_arm(struct
> >> intel_dsb *dsb,
> >> >  	if (!HAS_PSR2_SEL_FETCH(display))
> >> >  		return;
> >> >
> >> > +	/* Display ver 12 only instantiates these registers for pipe A */
> >> > +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> >> > +		return;
> >> > +
> >> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
> >> > plane->id), 0);  }
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

✗ i915.CI.BAT: failure for drm/i915/display: Limit SEL_FETCH clear to supported pipes

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5517 bytes --]

== Series Details ==

Series: drm/i915/display: Limit SEL_FETCH clear to supported pipes
URL   : https://patchwork.freedesktop.org/series/173351/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19090 -> Patchwork_173351v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_173351v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_173351v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/index.html

Participating hosts (39 -> 38)
------------------------------

  Additional (1): bat-adls-6 
  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_173351v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@client:
    - bat-arlh-2:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19090/bat-arlh-2/igt@i915_selftest@live@client.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-arlh-2/igt@i915_selftest@live@client.html

  
Known issues
------------

  Here are the changes found in Patchwork_173351v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adls-6:         NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic@basic:
    - bat-adls-6:         NOTRUN -> [SKIP][4] ([i915#15656])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@gem_tiled_pread_basic@basic.html

  * igt@i915_selftest@live:
    - bat-arlh-2:         [PASS][5] -> [INCOMPLETE][6] ([i915#16547])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19090/bat-arlh-2/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-arlh-2/igt@i915_selftest@live.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adls-6:         NOTRUN -> [SKIP][7] ([i915#7707]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adls-6:         NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#16361])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adls-6:         NOTRUN -> [SKIP][10]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#5354])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-adls-6:         NOTRUN -> [SKIP][12] ([i915#1072] / [i915#9732]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adls-6:         NOTRUN -> [SKIP][13] ([i915#3555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adls-6:         NOTRUN -> [SKIP][14] ([i915#3291]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/bat-adls-6/igt@prime_vgem@basic-fence-read.html

  
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#15656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15656
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#16547]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16547
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_19090 -> Patchwork_173351v1

  CI-20190529: 20190529
  CI_DRM_19090: 6db9bc26b0177aed554e3c57d8c30dad5da11a1a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9084: 9084
  Patchwork_173351v1: 6db9bc26b0177aed554e3c57d8c30dad5da11a1a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173351v1/index.html

[-- Attachment #2: Type: text/html, Size: 6426 bytes --]