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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Manna, Animesh" <animesh.manna@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command buffer when DSB fails
Date: Fri, 3 Feb 2023 13:51:57 +0200	[thread overview]
Message-ID: <Y9z1XZPaC1V9rFyy@intel.com> (raw)
In-Reply-To: <PH7PR11MB59814E671E2CB6628C3AF8A2F9D69@PH7PR11MB5981.namprd11.prod.outlook.com>

On Thu, Feb 02, 2023 at 05:09:05PM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, January 18, 2023 10:01 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command
> > buffer when DSB fails
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Dump the full DSB command buffers and head/tail pointers if the the DSB
> > hasn't completed its job in time.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dsb.c | 33 +++++++++++++++++++++---
> >  1 file changed, 30 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 9e25b1345927..f454329b6901 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -92,6 +92,22 @@ static bool assert_dsb_has_room(struct intel_dsb
> > *dsb)
> >  			 crtc->base.base.id, crtc->base.name, dsb->id);  }
> > 
> > +static void intel_dsb_dump(struct intel_dsb *dsb) {
> > +	struct intel_crtc *crtc = dsb->crtc;
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +	const u32 *buf = dsb->cmd_buf;
> > +	int i;
> > +
> > +	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
> > +		    crtc->base.base.id, crtc->base.name, dsb->id);
> > +	for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
> > +		drm_dbg_kms(&i915->drm,
> > +			    " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
> > +			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
> > +	drm_dbg_kms(&i915->drm, "}\n");
> > +}
> > +
> >  static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
> >  			enum dsb_id id)
> >  {
> > @@ -260,10 +276,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	enum pipe pipe = crtc->pipe;
> > 
> > -	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
> > +	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
> > +		u32 offset = i915_ggtt_offset(dsb->vma);
> > +
> > +		intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
> > +			       DSB_ENABLE | DSB_HALT);
> 
> One doubt - Why DSB_ENABLE bit is set here? Is setting DSB_HALT not sufficient.
> Other than above the changes look good to me.

Clearing the enable with would reset the DSB, so the halt would
seem superfluous in that case. And I *think* a reset does clear
DSB_CURRENT_HEAD so the debugs wouldn't provide any helpful data
in that case. I'll need to double check that I suppose, but at
least right now my DSB_CURRENT_HEAD does read zero while the DSB
isn't actively executing.

Though I suppose we could make do without the halt entirely and
just read the registers while the DSB might still be making
progress. Admittedly I suppose it still might be even with the
halt as I don't think the halt is instantaneous.

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-02-03 11:52 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-18 16:30 [Intel-gfx] [PATCH 00/13] drm/i915: Load LUTs with DSB Ville Syrjala
2023-01-18 16:30 ` [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Define more DSB registers Ville Syrjala
2023-02-03  9:49   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Pimp debug/error prints Ville Syrjala
2023-02-03  9:49   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit() Ville Syrjala
2023-02-02 15:22   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Introduce intel_dsb_finish() Ville Syrjala
2023-02-02 15:26   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command buffer when DSB fails Ville Syrjala
2023-02-02 17:09   ` Manna, Animesh
2023-02-03 11:51     ` Ville Syrjälä [this message]
2023-01-18 16:30 ` [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Allow vblank synchronized DSB execution Ville Syrjala
2023-02-02 17:17   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Nuke the DSB debug Ville Syrjala
2023-02-02 17:19   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs Ville Syrjala
2023-02-03 10:01   ` Manna, Animesh
2023-01-18 16:30 ` [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset Ville Syrjala
2023-02-03 10:04   ` Manna, Animesh
2023-02-03 10:46     ` Ville Syrjälä
2023-01-18 16:30 ` [Intel-gfx] [PATCH 10/13] drm/i915/dsb: Load LUTs using the DSB during vblank Ville Syrjala
2023-01-18 16:30 ` [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry twice with DSB Ville Syrjala
2023-02-02 19:05   ` Manna, Animesh
2023-02-03 10:50     ` Ville Syrjälä
2023-01-18 16:30 ` [Intel-gfx] [PATCH 12/13] drm/i915/dsb: Load LUTs with the DSB Ville Syrjala
2023-01-18 16:30 ` [Intel-gfx] [PATCH 13/13] drm/i915: Do state check for color management changes Ville Syrjala
2023-01-19  0:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB Patchwork
2023-01-19  0:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-19 22:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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