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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles
Date: Fri, 12 May 2023 11:53:32 -0700	[thread overview]
Message-ID: <ZF6LLIIpV4QPYAV5@orsosgc001.jf.intel.com> (raw)
In-Reply-To: <87mt29eatx.wl-ashutosh.dixit@intel.com>

On Fri, May 12, 2023 at 10:08:58AM -0700, Dixit, Ashutosh wrote:
>On Fri, 12 May 2023 03:57:35 -0700, Tvrtko Ursulin wrote:
>>
>>
>> On 11/05/2023 19:57, Dixit, Ashutosh wrote:
>> > On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
>> >>
>> >
>> > One drive-by comment:
>> >
>> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>> >> index 12b2f3169abf..284e5c5b97bb 100644
>> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> >> @@ -546,8 +546,9 @@ config_status(struct drm_i915_private *i915, u64 config)
>> >>	struct intel_gt *gt = to_gt(i915);
>> >>
>> >>	unsigned int gt_id = config_gt_id(config);
>> >> +	unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
>> >
>> > But in Patch 5 we have:
>> >
>> > #define I915_PMU_MAX_GTS (4)
>>
>> AFAIR that one is just to size the internal arrays, while max_gt_id is to
>> report to userspace which events are present.
>
>Hmm, apart from the #defines's in i915_drm.h in Patch 5, not seeing
>anything else reported to userspace about which events are present.

Ex: We have only gt0 and gt1 on MTL. When user configures an event (sets 
event id, tile id etc on the config parameter) and calls the 
perf_event_open, it results in i915_pmu_event_init() -> config_status() 
which will return an ENOENT if the event was for say gt2 or gt3. This is 
for runtime check only.

>
>Also, we already have I915_MAX_GT, we shouldn't need I915_PMU_MAX_GTS, or
>at least:
>
>	#define I915_PMU_MAX_GTS I915_MAX_GT
>
>Better to use things uniformly. If we want I915_PMU_MAX_GTS to be 2 instead
>of I915_MAX_GT (but why?, below is just a check) let's do
>
>	#define I915_PMU_MAX_GTS 2
>
>And use that in the code above. But I think we should just use I915_MAX_GT.

Agree,

Thanks,
Umesh
>
>Thanks.
>--
>Ashutosh
>
>
>> >
>> >>
>> >> -	if (gt_id)
>> >> +	if (gt_id > max_gt_id)
>> >>		return -ENOENT;
>> >>
>> >>	switch (config_counter(config)) {
>> >> @@ -561,6 +562,8 @@ config_status(struct drm_i915_private *i915, u64 config)
>> >>			return -ENODEV;
>> >>		break;
>> >>	case I915_PMU_INTERRUPTS:
>> >> +		if (gt_id)
>> >> +			return -ENOENT;
>> >>		break;
>> >>	case I915_PMU_RC6_RESIDENCY:
>> >>		if (!gt->rc6.supported)

  reply	other threads:[~2023-05-12 18:54 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-06  0:58 [Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-06  0:58 ` [Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines Umesh Nerlige Ramappa
2023-05-08 17:52   ` Umesh Nerlige Ramappa
2023-05-09 12:26     ` Tvrtko Ursulin
2023-05-06  0:58 ` [Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters Umesh Nerlige Ramappa
2023-05-08 17:53   ` Umesh Nerlige Ramappa
2023-05-06  0:58 ` [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based Umesh Nerlige Ramappa
2023-05-08 17:55   ` Umesh Nerlige Ramappa
2023-05-09 15:10     ` Umesh Nerlige Ramappa
2023-05-06  0:58 ` [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer Umesh Nerlige Ramappa
2023-05-08 17:58   ` Umesh Nerlige Ramappa
2023-05-09 17:25   ` Dixit, Ashutosh
2023-05-10  6:02     ` Dixit, Ashutosh
2023-05-12 22:29   ` Dixit, Ashutosh
2023-05-12 22:44     ` Umesh Nerlige Ramappa
2023-05-12 23:20       ` Dixit, Ashutosh
2023-05-12 23:44         ` Umesh Nerlige Ramappa
2023-05-15  9:52           ` Tvrtko Ursulin
2023-05-15 21:24             ` Dixit, Ashutosh
2023-05-16  7:12               ` Tvrtko Ursulin
2023-05-16 16:29                 ` Dixit, Ashutosh
2023-05-06  0:58 ` [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters Umesh Nerlige Ramappa
2023-05-08 18:07   ` Umesh Nerlige Ramappa
2023-05-12  1:08   ` Dixit, Ashutosh
2023-05-12 10:56     ` Tvrtko Ursulin
2023-05-12 20:57       ` Umesh Nerlige Ramappa
2023-05-12 22:37         ` Umesh Nerlige Ramappa
2023-05-13  1:09         ` Dixit, Ashutosh
2023-05-15 10:10         ` Tvrtko Ursulin
2023-05-15 22:07           ` Dixit, Ashutosh
2023-05-16  8:35             ` Tvrtko Ursulin
2023-05-06  0:58 ` [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa
2023-05-08 18:08   ` Umesh Nerlige Ramappa
2023-05-09 12:38   ` Tvrtko Ursulin
2023-05-11 18:57   ` Dixit, Ashutosh
2023-05-12 10:57     ` Tvrtko Ursulin
2023-05-12 17:08       ` Dixit, Ashutosh
2023-05-12 18:53         ` Umesh Nerlige Ramappa [this message]
2023-05-12 20:10           ` Dixit, Ashutosh
2023-05-06  2:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt (rev2) Patchwork
2023-05-06  2:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-06  2:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-05-13  1:55 [Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-13  1:55 ` [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa
2023-05-15  6:44 [Intel-gfx] [PATCH v4 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-15  6:44 ` [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa

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