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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: <intel-gfx@lists.freedesktop.org>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Ashutosh Dixit <ashutosh.dixit@intel.com>
Subject: Re: [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based
Date: Tue, 9 May 2023 08:10:03 -0700	[thread overview]
Message-ID: <ZFpiS5ulz0xLgrT7@orsosgc001.jf.intel.com> (raw)
In-Reply-To: <ZFk3dT/vODwE5ata@orsosgc001.jf.intel.com>

On Mon, May 08, 2023 at 10:55:01AM -0700, Umesh Nerlige Ramappa wrote:
>On Fri, May 05, 2023 at 05:58:13PM -0700, Umesh Nerlige Ramappa wrote:
>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>>Trivial prep work for full multi-tile enablement later.
>
>Some more description on what this does OR how park/unpark affects pmu 
>counters would help.

Described later, so

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>
>Thanks,
>Umesh
>
>>
>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>drivers/gpu/drm/i915/gt/intel_gt_pm.c |  4 ++--
>>drivers/gpu/drm/i915/i915_pmu.c       | 16 ++++++++--------
>>drivers/gpu/drm/i915/i915_pmu.h       |  9 +++++----
>>3 files changed, 15 insertions(+), 14 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>index e02cb90723ae..c2e69bafd02b 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
>>
>>	intel_rc6_unpark(&gt->rc6);
>>	intel_rps_unpark(&gt->rps);
>>-	i915_pmu_gt_unparked(i915);
>>+	i915_pmu_gt_unparked(gt);
>>	intel_guc_busyness_unpark(gt);
>>
>>	intel_gt_unpark_requests(gt);
>>@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
>>
>>	intel_guc_busyness_park(gt);
>>	i915_vma_parked(gt);
>>-	i915_pmu_gt_parked(i915);
>>+	i915_pmu_gt_parked(gt);
>>	intel_rps_park(&gt->rps);
>>	intel_rc6_park(&gt->rc6);
>>
>>diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>>index ba769f7fc385..2b63ee31e1b3 100644
>>--- a/drivers/gpu/drm/i915/i915_pmu.c
>>+++ b/drivers/gpu/drm/i915/i915_pmu.c
>>@@ -217,11 +217,11 @@ static void init_rc6(struct i915_pmu *pmu)
>>	}
>>}
>>
>>-static void park_rc6(struct drm_i915_private *i915)
>>+static void park_rc6(struct intel_gt *gt)
>>{
>>-	struct i915_pmu *pmu = &i915->pmu;
>>+	struct i915_pmu *pmu = &gt->i915->pmu;
>>
>>-	pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
>>+	pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
>>	pmu->sleep_last = ktime_get_raw();
>>}
>>
>>@@ -236,16 +236,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
>>	}
>>}
>>
>>-void i915_pmu_gt_parked(struct drm_i915_private *i915)
>>+void i915_pmu_gt_parked(struct intel_gt *gt)
>>{
>>-	struct i915_pmu *pmu = &i915->pmu;
>>+	struct i915_pmu *pmu = &gt->i915->pmu;
>>
>>	if (!pmu->base.event_init)
>>		return;
>>
>>	spin_lock_irq(&pmu->lock);
>>
>>-	park_rc6(i915);
>>+	park_rc6(gt);
>>
>>	/*
>>	 * Signal sampling timer to stop if only engine events are enabled and
>>@@ -256,9 +256,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
>>	spin_unlock_irq(&pmu->lock);
>>}
>>
>>-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
>>+void i915_pmu_gt_unparked(struct intel_gt *gt)
>>{
>>-	struct i915_pmu *pmu = &i915->pmu;
>>+	struct i915_pmu *pmu = &gt->i915->pmu;
>>
>>	if (!pmu->base.event_init)
>>		return;
>>diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
>>index c30f43319a78..a686fd7ccedf 100644
>>--- a/drivers/gpu/drm/i915/i915_pmu.h
>>+++ b/drivers/gpu/drm/i915/i915_pmu.h
>>@@ -13,6 +13,7 @@
>>#include <uapi/drm/i915_drm.h>
>>
>>struct drm_i915_private;
>>+struct intel_gt;
>>
>>/*
>> * Non-engine events that we need to track enabled-disabled transition and
>>@@ -151,15 +152,15 @@ int i915_pmu_init(void);
>>void i915_pmu_exit(void);
>>void i915_pmu_register(struct drm_i915_private *i915);
>>void i915_pmu_unregister(struct drm_i915_private *i915);
>>-void i915_pmu_gt_parked(struct drm_i915_private *i915);
>>-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
>>+void i915_pmu_gt_parked(struct intel_gt *gt);
>>+void i915_pmu_gt_unparked(struct intel_gt *gt);
>>#else
>>static inline int i915_pmu_init(void) { return 0; }
>>static inline void i915_pmu_exit(void) {}
>>static inline void i915_pmu_register(struct drm_i915_private *i915) {}
>>static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
>>-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
>>-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
>>+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
>>+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
>>#endif
>>
>>#endif
>>-- 
>>2.36.1
>>

  reply	other threads:[~2023-05-09 15:10 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-06  0:58 [Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-06  0:58 ` [Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines Umesh Nerlige Ramappa
2023-05-08 17:52   ` Umesh Nerlige Ramappa
2023-05-09 12:26     ` Tvrtko Ursulin
2023-05-06  0:58 ` [Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters Umesh Nerlige Ramappa
2023-05-08 17:53   ` Umesh Nerlige Ramappa
2023-05-06  0:58 ` [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based Umesh Nerlige Ramappa
2023-05-08 17:55   ` Umesh Nerlige Ramappa
2023-05-09 15:10     ` Umesh Nerlige Ramappa [this message]
2023-05-06  0:58 ` [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer Umesh Nerlige Ramappa
2023-05-08 17:58   ` Umesh Nerlige Ramappa
2023-05-09 17:25   ` Dixit, Ashutosh
2023-05-10  6:02     ` Dixit, Ashutosh
2023-05-12 22:29   ` Dixit, Ashutosh
2023-05-12 22:44     ` Umesh Nerlige Ramappa
2023-05-12 23:20       ` Dixit, Ashutosh
2023-05-12 23:44         ` Umesh Nerlige Ramappa
2023-05-15  9:52           ` Tvrtko Ursulin
2023-05-15 21:24             ` Dixit, Ashutosh
2023-05-16  7:12               ` Tvrtko Ursulin
2023-05-16 16:29                 ` Dixit, Ashutosh
2023-05-06  0:58 ` [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters Umesh Nerlige Ramappa
2023-05-08 18:07   ` Umesh Nerlige Ramappa
2023-05-12  1:08   ` Dixit, Ashutosh
2023-05-12 10:56     ` Tvrtko Ursulin
2023-05-12 20:57       ` Umesh Nerlige Ramappa
2023-05-12 22:37         ` Umesh Nerlige Ramappa
2023-05-13  1:09         ` Dixit, Ashutosh
2023-05-15 10:10         ` Tvrtko Ursulin
2023-05-15 22:07           ` Dixit, Ashutosh
2023-05-16  8:35             ` Tvrtko Ursulin
2023-05-06  0:58 ` [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa
2023-05-08 18:08   ` Umesh Nerlige Ramappa
2023-05-09 12:38   ` Tvrtko Ursulin
2023-05-11 18:57   ` Dixit, Ashutosh
2023-05-12 10:57     ` Tvrtko Ursulin
2023-05-12 17:08       ` Dixit, Ashutosh
2023-05-12 18:53         ` Umesh Nerlige Ramappa
2023-05-12 20:10           ` Dixit, Ashutosh
2023-05-06  2:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt (rev2) Patchwork
2023-05-06  2:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-06  2:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-05-13  1:55 [Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-13  1:55 ` [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based Umesh Nerlige Ramappa
2023-05-15  6:44 [Intel-gfx] [PATCH v4 0/6] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-15  6:44 ` [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based Umesh Nerlige Ramappa

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