From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 06/25] drm/i915: Add helper to modeset a set of pipes
Date: Fri, 15 Sep 2023 21:34:26 +0300 [thread overview]
Message-ID: <ZQSjsnMzbusYgfSt@intel.com> (raw)
In-Reply-To: <20230914192659.757475-7-imre.deak@intel.com>
On Thu, Sep 14, 2023 at 10:26:40PM +0300, Imre Deak wrote:
> Add intel_modeset_pipes_in_mask_early() to modeset a provided set of
> pipes, used in a follow-up patch.
>
> While at it add _late suffix to intel_modeset_all_pipes() for clarity
> and add DocBook descriptions for the two exported functions.
>
> v2:
> - Add a flag controlling if active planes are force updated as well.
> - Add DockBook descriptions.
> v3:
> - For clarity use _early/_late suffixes for the exported functions
> instead of the update_active_planes parameter. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.h | 6 ++-
> drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> 4 files changed, 47 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad5251ba6fe13..a2e20b25d6361 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3139,7 +3139,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> /* All pipes must be switched off while we change the cdclk. */
> - ret = intel_modeset_all_pipes(state, "CDCLK change");
> + ret = intel_modeset_all_pipes_late(state, "CDCLK change");
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6bbc9069754c4..27e6ea21e0a91 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5407,8 +5407,9 @@ intel_verify_planes(struct intel_atomic_state *state)
> plane_state->uapi.visible);
> }
>
> -int intel_modeset_all_pipes(struct intel_atomic_state *state,
> - const char *reason)
> +static int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
> + const char *reason, u8 mask,
> + bool update_active_planes)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -5417,7 +5418,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> * Add all pipes to the state, and force
> * a modeset on all the active ones.
> */
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, mask) {
> struct intel_crtc_state *crtc_state;
> int ret;
>
> @@ -5448,7 +5449,9 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - crtc_state->update_planes |= crtc_state->active_planes;
> + if (update_active_planes)
> + crtc_state->update_planes |= crtc_state->active_planes;
This thing still confuses me. We have a bunch of other "late modeset"
stuff in there (async flip handling and clearing of fastset flag at
least). I still think a clean split would be better than a confusing
parameter.
> +
> crtc_state->async_flip_planes = 0;
> crtc_state->do_async_flip = false;
> }
> @@ -5456,6 +5459,40 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> return 0;
> }
>
> +/**
> + * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
> + * @state: intel atomic state
> + * @reason: the reason for the full modeset
> + * @mask: mask of pipes to modeset
> + *
> + * Force a full modeset on pipes in @mask due to the description in @reason.
> + * This function can be called only before new plane states are computed.
> + *
> + * Returns 0 in case of success, negative error code otherwise.
> + */
> +int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
> + const char *reason, u8 mask)
> +{
> + return intel_modeset_pipes_in_mask(state, reason, mask, false);
> +}
> +
> +/**
> + * intel_modeset_all_pipes_late - force a full modeset on all pipes
> + * @state: intel atomic state
> + * @reason: the reason for the full modeset
> + *
> + * Force a full modeset on all pipes due to the description in @reason.
> + * This function can be called only after new plane states are computed
> + * already.
> + *
> + * Returns 0 in case of success, negative error code otherwise.
> + */
> +int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
> + const char *reason)
> +{
> + return intel_modeset_pipes_in_mask(state, reason, -1, true);
> +}
> +
> /*
> * This implements the workaround described in the "notes" section of the mode
> * set sequence documentation. When going from no pipes or single pipe to
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988b..64a5be7859331 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -513,8 +513,10 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
> void intel_update_watermarks(struct drm_i915_private *i915);
>
> /* modesetting */
> -int intel_modeset_all_pipes(struct intel_atomic_state *state,
> - const char *reason);
> +int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
> + const char *reason, u8 pipe_mask);
> +int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
> + const char *reason);
> void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> struct intel_power_domain_mask *old_domains);
> void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 063929a42a42f..a29d9b717deed 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2616,7 +2616,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
>
> if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> /* TODO: Implement vblank synchronized MBUS joining changes */
> - ret = intel_modeset_all_pipes(state, "MBUS joining change");
> + ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> if (ret)
> return ret;
> }
> --
> 2.37.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-09-15 18:34 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 19:26 [Intel-gfx] [PATCH v3 00/25] drm/i915: Improve BW management on shared display links Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 01/25] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 02/25] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 03/25] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 04/25] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
2023-09-19 14:48 ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 05/25] drm/i915/dp: Limit the output link bpp in " Imre Deak
2023-09-19 14:49 ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 06/25] drm/i915: Add helper to modeset a set of pipes Imre Deak
2023-09-15 18:34 ` Ville Syrjälä [this message]
2023-09-15 20:03 ` Imre Deak
2023-09-18 18:25 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-19 14:25 ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 07/25] drm/i915: During modeset forcing handle inactive but enabled pipes Imre Deak
2023-09-18 18:25 ` [Intel-gfx] [PATCH v5 07/25] drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late() Imre Deak
2023-09-19 14:26 ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 08/25] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 09/25] drm/i915: Add helpers for BW management on shared display links Imre Deak
2023-09-15 0:33 ` [Intel-gfx] [PATCH v4 " Imre Deak
2023-09-15 19:11 ` Ville Syrjälä
2023-09-15 21:01 ` Imre Deak
2023-09-18 18:25 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-19 15:21 ` Ville Syrjälä
2023-09-19 17:40 ` Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 10/25] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
2023-09-15 19:31 ` Ville Syrjälä
2023-09-15 23:13 ` Imre Deak
2023-09-19 15:35 ` Ville Syrjälä
2023-09-19 17:45 ` Imre Deak
2023-09-18 18:25 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 11/25] drm/i915/fdi: Recompute state for affected CRTCs on FDI links Imre Deak
2023-09-19 15:44 ` Ville Syrjälä
2023-09-19 18:14 ` Imre Deak
2023-09-19 18:28 ` Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 12/25] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 13/25] drm/dp_mst: Add a way to calculate PBN values with FEC overhead Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 14/25] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 15/25] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 16/25] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
2023-09-20 9:09 ` Lisovskiy, Stanislav
2023-09-20 10:58 ` Ville Syrjälä
2023-09-20 11:35 ` Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-09-20 9:11 ` Lisovskiy, Stanislav
2023-09-20 10:59 ` Ville Syrjälä
2023-09-20 11:25 ` Lisovskiy, Stanislav
2023-09-20 12:38 ` Imre Deak
2023-09-20 13:56 ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 19/25] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-09-25 8:00 ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 20/25] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-09-25 7:56 ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 21/25] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 22/25] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 23/25] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device Imre Deak
2023-09-25 7:44 ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 24/25] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-09-19 10:52 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-25 7:42 ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 25/25] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-09-25 7:54 ` Lisovskiy, Stanislav
2023-09-14 23:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev4) Patchwork
2023-09-15 4:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev5) Patchwork
2023-09-15 4:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-15 4:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-09-15 12:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-19 1:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev9) Patchwork
2023-09-19 11:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev10) Patchwork
2023-09-19 11:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-19 11:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-19 13:29 ` Imre Deak
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