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From: Imre Deak <imre.deak@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 11/25] drm/i915/fdi: Recompute state for affected CRTCs on FDI links
Date: Tue, 19 Sep 2023 21:28:08 +0300	[thread overview]
Message-ID: <ZQnoOM1QLx6oJvzI@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <ZQnlA/g4jzYxSPhU@ideak-desk.fi.intel.com>

On Tue, Sep 19, 2023 at 09:14:27PM +0300, Imre Deak wrote:
> On Tue, Sep 19, 2023 at 06:44:00PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 14, 2023 at 10:26:45PM +0300, Imre Deak wrote:
> > > Recompute the state of all CRTCs on an FDI link during a modeset that
> > > may be affected by the modeset of other CRTCs on the same link. This
> > > ensures that each CRTC on the link maximizes its BW use (after another
> > > CRTC is disabled).
> > > 
> > > In practice this means recomputing pipe B's config on IVB if pipe C gets
> > > disabled.
> > > 
> > > v2:
> > > - Add the change recomputing affected CRTC states in a separate patch.
> > >   (Ville)
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c |  4 ++
> > >  drivers/gpu/drm/i915/display/intel_fdi.c     | 53 ++++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_fdi.h     |  1 +
> > >  3 files changed, 58 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index aad16dcceb788..31297a333f50e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6210,6 +6210,10 @@ int intel_atomic_check_config(struct intel_atomic_state *state,
> > >  	if (ret)
> > >  		return ret;
> > >  
> > > +	ret = intel_fdi_add_affected_crtcs(state);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > >  		if (!intel_crtc_needs_modeset(new_crtc_state)) {
> > >  			if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> > > index ad01915a4a39b..d723ae7e10d71 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > > @@ -120,6 +120,59 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
> > >  	dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
> > >  }
> > >  
> > > +/**
> > > + * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
> > > + * @state: intel atomic state
> > > + *
> > > + * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
> > > + * known to affect the available FDI BW for the former CRTC. In practice this
> > > + * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
> > > + * CRTC C) and CRTC C is getting disabled.
> > > + *
> > > + * Returns 0 in case of success, or a negative error code otherwise.
> > > + */
> > > +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
> > > +{
> > > +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > +	struct intel_crtc_state *old_crtc_state;
> > > +	struct intel_crtc_state *new_crtc_state;
> > 
> > Both look like they can be const.
> 
> Ok.
> 
> > > +	struct intel_crtc *crtc;
> > > +
> > > +	if (!IS_IVYBRIDGE(i915))
> > 
> > Should also check num_pipes==3 since pipe C can (at least in theory)
> > be fused off.
> 
> Yes, but thought that pipe C's new_crtc_state would be NULL then.

Ah, crtc itself would be NULL then :/

> Can make the check more explicit in any case.
> 
> > > +		return 0;
> > > +
> > > +	crtc = intel_crtc_for_pipe(i915, PIPE_C);
> > > +	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > > +
> > > +	if (!new_crtc_state)
> > > +		return 0;
> > > +
> > > +	old_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > 
> > old vs. new mixup
> 
> Err, yes thanks for catching it.
> 
> > > +
> > > +	if (!old_crtc_state->fdi_lanes)
> > > +		return 0;
> > > +
> > > +	if (!intel_crtc_needs_modeset(new_crtc_state))
> > > +		return 0;
> > > +
> > > +	if (new_crtc_state->uapi.enable)
> > > +		return 0;
> > 
> > We could be switching pipe C from driving a PCH port to driving
> > the CPU eDP port. So this check seems a bit wrong.
> 
> Yes, didn't think of that case. I'll change it to:
> 
> 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> 	if (new_crtc_state->uapi.enable && encoder->port != PORT_A)
> 		return 0;
> 
> > > +
> > > +	crtc = intel_crtc_for_pipe(i915, PIPE_B);
> > > +	new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> > > +
> > > +	if (IS_ERR(new_crtc_state))
> > > +		return PTR_ERR(old_crtc_state);
> > > +
> > > +	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> > > +	if (!old_crtc_state->fdi_lanes)
> > > +		return 0;
> > > +
> > > +	return intel_modeset_pipes_in_mask_early(state,
> > > +						 "FDI link BW decrease on pipe C",
> > > +						 BIT(PIPE_B));
> > > +}
> > > +
> > >  /* units of 100MHz */
> > >  static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> > >  {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> > > index 129444c580f27..eb02b967bb440 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> > > @@ -14,6 +14,7 @@ struct intel_crtc_state;
> > >  struct intel_encoder;
> > >  struct intel_link_bw_limits;
> > >  
> > > +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
> > >  int intel_fdi_link_freq(struct drm_i915_private *i915,
> > >  			const struct intel_crtc_state *pipe_config);
> > >  int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
> > > -- 
> > > 2.37.2
> > 
> > -- 
> > Ville Syrjälä
> > Intel

  reply	other threads:[~2023-09-19 18:28 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-14 19:26 [Intel-gfx] [PATCH v3 00/25] drm/i915: Improve BW management on shared display links Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 01/25] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 02/25] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 03/25] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 04/25] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
2023-09-19 14:48   ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 05/25] drm/i915/dp: Limit the output link bpp in " Imre Deak
2023-09-19 14:49   ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 06/25] drm/i915: Add helper to modeset a set of pipes Imre Deak
2023-09-15 18:34   ` Ville Syrjälä
2023-09-15 20:03     ` Imre Deak
2023-09-18 18:25   ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-19 14:25     ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 07/25] drm/i915: During modeset forcing handle inactive but enabled pipes Imre Deak
2023-09-18 18:25   ` [Intel-gfx] [PATCH v5 07/25] drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late() Imre Deak
2023-09-19 14:26     ` Ville Syrjälä
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 08/25] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 09/25] drm/i915: Add helpers for BW management on shared display links Imre Deak
2023-09-15  0:33   ` [Intel-gfx] [PATCH v4 " Imre Deak
2023-09-15 19:11     ` Ville Syrjälä
2023-09-15 21:01       ` Imre Deak
2023-09-18 18:25     ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-19 15:21       ` Ville Syrjälä
2023-09-19 17:40         ` Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 10/25] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
2023-09-15 19:31   ` Ville Syrjälä
2023-09-15 23:13     ` Imre Deak
2023-09-19 15:35       ` Ville Syrjälä
2023-09-19 17:45         ` Imre Deak
2023-09-18 18:25   ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 11/25] drm/i915/fdi: Recompute state for affected CRTCs on FDI links Imre Deak
2023-09-19 15:44   ` Ville Syrjälä
2023-09-19 18:14     ` Imre Deak
2023-09-19 18:28       ` Imre Deak [this message]
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 12/25] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 13/25] drm/dp_mst: Add a way to calculate PBN values with FEC overhead Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 14/25] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 15/25] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 16/25] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
2023-09-20  9:09   ` Lisovskiy, Stanislav
2023-09-20 10:58   ` Ville Syrjälä
2023-09-20 11:35     ` Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-09-20  9:11   ` Lisovskiy, Stanislav
2023-09-20 10:59     ` Ville Syrjälä
2023-09-20 11:25       ` Lisovskiy, Stanislav
2023-09-20 12:38         ` Imre Deak
2023-09-20 13:56           ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 19/25] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-09-25  8:00   ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 20/25] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-09-25  7:56   ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 21/25] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 22/25] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 23/25] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device Imre Deak
2023-09-25  7:44   ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 24/25] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-09-19 10:52   ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-09-25  7:42     ` Lisovskiy, Stanislav
2023-09-14 19:26 ` [Intel-gfx] [PATCH v3 25/25] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-09-25  7:54   ` Lisovskiy, Stanislav
2023-09-14 23:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev4) Patchwork
2023-09-15  4:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev5) Patchwork
2023-09-15  4:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-15  4:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-09-15 12:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-19  1:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev9) Patchwork
2023-09-19 11:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev10) Patchwork
2023-09-19 11:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-19 11:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-19 13:29   ` Imre Deak

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