From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 19/29] drm/i915/dp: Disable FEC ready flag in the sink
Date: Wed, 25 Oct 2023 11:01:04 +0300 [thread overview]
Message-ID: <ZTjLQKb4cJtSnVbZ@intel.com> (raw)
In-Reply-To: <20231024010925.3949910-20-imre.deak@intel.com>
On Tue, Oct 24, 2023 at 04:09:15AM +0300, Imre Deak wrote:
> Disable the FEC ready flag in the sink during a disabling modeset.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6f9d0f2ff3d9a..99d96762fa29c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2211,18 +2211,21 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
> }
>
> static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> + const struct intel_crtc_state *crtc_state,
> + bool enable)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> if (!crtc_state->fec_enable)
> return;
>
> - if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
> - drm_dbg_kms(&i915->drm,
> - "Failed to set FEC_READY in the sink\n");
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
> + enable ? DP_FEC_READY : 0) <= 0)
> + drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n",
> + enable ? "enabled" : "disabled");
>
> - if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
> + if (enable &&
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
> DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
> drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n");
> }
> @@ -2541,7 +2544,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * in the FEC_CONFIGURATION register to 1 before initiating link
> * training
> */
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
>
> intel_dp_check_frl_training(intel_dp);
> intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> @@ -2692,7 +2695,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * in the FEC_CONFIGURATION register to 1 before initiating link
> * training
> */
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
>
> intel_dp_check_frl_training(intel_dp);
> intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> @@ -2768,7 +2771,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> true);
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
> intel_dp_start_link_train(intel_dp, crtc_state);
> if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
> !is_trans_port_sync_mode(crtc_state))
> @@ -2997,6 +3000,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>
> intel_disable_ddi_buf(encoder, old_crtc_state);
>
> + intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
> +
> /*
> * From TGL spec: "If single stream or multi-stream master transcoder:
> * Configure Transcoder Clock select to direct no clock to the
> --
> 2.39.2
>
next prev parent reply other threads:[~2023-10-25 8:08 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 1:08 [Intel-gfx] [PATCH 00/29] drm/i915: Improve BW management on MST links Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 01/29] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 02/29] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 03/29] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 04/29] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 05/29] drm/dp_mst: Allow DSC in any Synaptics last branch device Imre Deak
2023-10-27 9:21 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 06/29] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags Imre Deak
2023-10-27 9:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 07/29] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 9:23 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 08/29] drm/dp: Add helpers to calculate the link BW overhead Imre Deak
2023-10-24 2:47 ` kernel test robot
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:21 ` Lisovskiy, Stanislav
2023-10-24 12:34 ` [Intel-gfx] [PATCH " kernel test robot
2023-10-25 15:47 ` kernel test robot
2023-10-24 1:09 ` [Intel-gfx] [PATCH 09/29] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed Imre Deak
2023-10-24 17:27 ` Lisovskiy, Stanislav
2023-10-30 8:38 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 10/29] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder Imre Deak
2023-10-25 15:27 ` Ville Syrjälä
2023-10-25 15:37 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 11/29] drm/i915/dp: Pass actual BW overhead to m_n calculation Imre Deak
2023-10-24 17:28 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 12/29] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 13/29] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 14/29] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 15/29] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 16/29] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 17/29] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec() Imre Deak
2023-10-25 7:58 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 18/29] drm/i915/dp: Wait for FEC detected status in the sink Imre Deak
2023-10-24 17:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 19/29] drm/i915/dp: Disable FEC ready flag " Imre Deak
2023-10-25 8:01 ` Lisovskiy, Stanislav [this message]
2023-10-24 1:09 ` [Intel-gfx] [PATCH 20/29] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
2023-10-27 7:59 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 21/29] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
2023-10-27 12:24 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 22/29] drm/i915/dp: Enable DSC via the connector decompression AUX Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:27 ` Lisovskiy, Stanislav
2023-10-25 8:30 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 23/29] drm/i915/dp_mst: Enable DSC passthrough Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:26 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 24/29] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
[not found] ` <ZTvNCgO9NF/rl1t+@intel.com>
[not found] ` <ZTvO3VK+sMksD69l@ideak-desk.fi.intel.com>
2023-10-30 7:29 ` Lisovskiy, Stanislav
2023-10-30 8:09 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 25/29] drm/i915: Factor out function to clear pipe update flags Imre Deak
[not found] ` <ZTvaXNT3C3VZGOel@intel.com>
2023-10-27 16:39 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 26/29] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
2023-10-27 9:08 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 27/29] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 28/29] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 29/29] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info Imre Deak
2023-10-30 4:17 ` Nautiyal, Ankit K
2023-10-30 5:29 ` Murthy, Arun R
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev5) Patchwork
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-24 22:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-25 7:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-26 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev7) Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-27 23:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-30 21:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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