From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 22/29] drm/i915/dp: Enable DSC via the connector decompression AUX
Date: Fri, 27 Oct 2023 15:27:01 +0300 [thread overview]
Message-ID: <ZTuslUaoujxkZbPz@intel.com> (raw)
In-Reply-To: <20231024102219.4035939-3-imre.deak@intel.com>
On Tue, Oct 24, 2023 at 01:22:18PM +0300, Imre Deak wrote:
> Enable DSC using the DSC AUX device stored for this purpose in the
> connector. This prepares for a follow-up patch which toggles DSC for
> each stream as needed, but for now keeps the current behavior, as DSC is
> still only enabled for the first MST stream.
>
> While at it set/clear only the DP_DECOMPRESSION_EN flag in the
> DP_DSC_ENABLE DPCD register, preserving the reserved register bits.
>
> v2:
> - Add a helper function setting/clearing the decompression flag,
> preserving the reserved register bits.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++---
> drivers/gpu/drm/i915/display/intel_dp.c | 46 +++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +-
> 4 files changed, 49 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bc438272d6d1a..79e36939d92d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2539,7 +2539,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> if (!is_mst)
> - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector),
> + crtc_state, true);
>
> /*
> * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> @@ -2692,7 +2693,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> if (!is_mst)
> - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector),
> + crtc_state, true);
> /*
> * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> * in the FEC_CONFIGURATION register to 1 before initiating link
> @@ -2773,8 +2775,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> if (!is_mst)
> - intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> - true);
> + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector),
> + crtc_state, true);
> intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
> intel_dp_start_link_train(intel_dp, crtc_state);
> if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
> @@ -3354,6 +3356,8 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
> const struct drm_connector_state *old_conn_state)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_connector *connector =
> + to_intel_connector(old_conn_state->connector);
>
> intel_dp->link_trained = false;
>
> @@ -3362,7 +3366,7 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
> intel_psr_disable(intel_dp, old_crtc_state);
> intel_edp_backlight_off(old_conn_state);
> /* Disable the decompression in DP Sink */
> - intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
> + intel_dp_sink_set_decompression_state(connector, old_crtc_state,
> false);
> /* Disable Ignore_MSA bit in DP Sink */
> intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7d185d6b2fe9d..0101e17515b33 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2937,22 +2937,50 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
> intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
> }
>
> -void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> +static int
> +write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
> +{
> + int err;
> + u8 val;
> +
> + err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
> + if (err < 0)
> + return err;
> +
> + if (set)
> + val |= flag;
> + else
> + val &= ~flag;
> +
> + return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
> +}
> +
> +static void
> +intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +
> + if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
> + DP_DECOMPRESSION_EN, enable) < 0)
> + drm_dbg_kms(&i915->drm,
> + "Failed to %s sink decompression state\n",
> + str_enable_disable(enable));
> +}
> +
> +void intel_dp_sink_set_decompression_state(struct intel_connector *connector,
> const struct intel_crtc_state *crtc_state,
> bool enable)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
>
> if (!crtc_state->dsc.compression_enable)
> return;
>
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
> - enable ? DP_DECOMPRESSION_EN : 0);
> - if (ret < 0)
> - drm_dbg_kms(&i915->drm,
> - "Failed to %s sink decompression state\n",
> - str_enable_disable(enable));
> + if (drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux))
> + return;
> +
> + intel_dp_sink_set_dsc_decompression(connector, enable);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 2080575fef69a..a231d234f6e9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -57,7 +57,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
> void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
> void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> -void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> +void intel_dp_sink_set_decompression_state(struct intel_connector *connector,
> const struct intel_crtc_state *crtc_state,
> bool enable);
> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b0310f464c1cd..8ef3a2611207c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -735,7 +735,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
> * TODO: disable decompression for all streams/in any MST ports, not
> * only in the first downstream branch device.
> */
> - intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false);
> + intel_dp_sink_set_decompression_state(connector, old_crtc_state, false);
> }
>
> static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> @@ -895,7 +895,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
> * TODO: enable decompression for all streams/in any MST ports, not
> * only in the first downstream branch device.
> */
> - intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true);
> + intel_dp_sink_set_decompression_state(connector, pipe_config, true);
> dig_port->base.pre_enable(state, &dig_port->base,
> pipe_config, NULL);
> }
> --
> 2.39.2
>
next prev parent reply other threads:[~2023-10-27 12:27 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 1:08 [Intel-gfx] [PATCH 00/29] drm/i915: Improve BW management on MST links Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 01/29] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 02/29] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 03/29] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 04/29] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 05/29] drm/dp_mst: Allow DSC in any Synaptics last branch device Imre Deak
2023-10-27 9:21 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 06/29] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags Imre Deak
2023-10-27 9:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 07/29] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 9:23 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 08/29] drm/dp: Add helpers to calculate the link BW overhead Imre Deak
2023-10-24 2:47 ` kernel test robot
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:21 ` Lisovskiy, Stanislav
2023-10-24 12:34 ` [Intel-gfx] [PATCH " kernel test robot
2023-10-25 15:47 ` kernel test robot
2023-10-24 1:09 ` [Intel-gfx] [PATCH 09/29] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed Imre Deak
2023-10-24 17:27 ` Lisovskiy, Stanislav
2023-10-30 8:38 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 10/29] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder Imre Deak
2023-10-25 15:27 ` Ville Syrjälä
2023-10-25 15:37 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 11/29] drm/i915/dp: Pass actual BW overhead to m_n calculation Imre Deak
2023-10-24 17:28 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 12/29] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 13/29] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 14/29] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 15/29] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 16/29] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 17/29] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec() Imre Deak
2023-10-25 7:58 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 18/29] drm/i915/dp: Wait for FEC detected status in the sink Imre Deak
2023-10-24 17:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 19/29] drm/i915/dp: Disable FEC ready flag " Imre Deak
2023-10-25 8:01 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 20/29] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
2023-10-27 7:59 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 21/29] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
2023-10-27 12:24 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 22/29] drm/i915/dp: Enable DSC via the connector decompression AUX Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:27 ` Lisovskiy, Stanislav [this message]
2023-10-25 8:30 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 23/29] drm/i915/dp_mst: Enable DSC passthrough Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:26 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 24/29] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
[not found] ` <ZTvNCgO9NF/rl1t+@intel.com>
[not found] ` <ZTvO3VK+sMksD69l@ideak-desk.fi.intel.com>
2023-10-30 7:29 ` Lisovskiy, Stanislav
2023-10-30 8:09 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 25/29] drm/i915: Factor out function to clear pipe update flags Imre Deak
[not found] ` <ZTvaXNT3C3VZGOel@intel.com>
2023-10-27 16:39 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 26/29] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
2023-10-27 9:08 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 27/29] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 28/29] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 29/29] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info Imre Deak
2023-10-30 4:17 ` Nautiyal, Ankit K
2023-10-30 5:29 ` Murthy, Arun R
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev5) Patchwork
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-24 22:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-25 7:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-26 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev7) Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-27 23:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-30 21:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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