From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 20/29] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
Date: Fri, 27 Oct 2023 10:59:14 +0300 [thread overview]
Message-ID: <ZTtt0ijtvmRNjsA0@intel.com> (raw)
In-Reply-To: <20231024010925.3949910-21-imre.deak@intel.com>
On Tue, Oct 24, 2023 at 04:09:16AM +0300, Imre Deak wrote:
> The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK
> period, presumedly to save BW, which the hub expands before forwarding
> the stream to the sink. In particular a 4k mode with a standard CVT
> HBLANK period is exposed with either a CVT reduced blank RBv1 (80 pixel)
> or a non-CVT 56 pixel HBLANK period. The DP standard describes the above
> HBLANK expansion functionality, but it requires enabling this explicitly,
> whereas these hubs apply the expansion transparently.
>
> Such modes will work okay until DSC decompression is enabled in the hub
> for the given sink, but after this the same mode will not work reliably
> in decompressed mode. As a workaround force enable DSC for such modes.
> OTOH DSC for these modes will only work above a certain compressed bpp
> threshold which depends on the link rate, so apply this limit as well
> in the workaround.
>
> Apply the workaround only for Synaptics hubs which support the HBLANK
> expansion.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 109 +++++++++++++++++-
> 2 files changed, 107 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 65ea37fe8cff3..409dbf8a2a1cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -624,6 +624,8 @@ struct intel_connector {
> struct drm_dp_aux *dsc_decompression_aux;
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> u8 fec_capability;
> +
> + u8 dsc_hblank_expansion_quirk:1;
> } dp;
>
> /* Work struct to schedule a uevent on link train failure */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index a1ea75cd5ea84..9124e9cdf4c79 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -345,8 +345,69 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> return 0;
> }
>
> +static bool
> +hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
> + const struct intel_crtc_state *crtc_state)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> +
> + if (!connector->dp.dsc_hblank_expansion_quirk)
> + return false;
> +
> + if (adjusted_mode->htotal - adjusted_mode->hdisplay > 80)
> + return false;
> +
> + return true;
> +}
> +
> +static bool
> +adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
> + const struct intel_crtc_state *crtc_state,
> + struct link_config_limits *limits,
> + bool dsc)
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + int min_bpp_x16 = limits->link.min_bpp_x16;
> +
> + if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
> + return true;
> +
> + if (!dsc) {
> + drm_dbg_kms(&i915->drm,
> + "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC required by hblank expansion quirk\n",
> + crtc->base.base.id, crtc->base.name,
> + connector->base.base.id, connector->base.name);
> + return false;
> + }
> +
> + drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
> +
> + if (limits->max_rate < 540000)
> + min_bpp_x16 = to_bpp_x16(13);
> + else if (limits->max_rate < 810000)
> + min_bpp_x16 = to_bpp_x16(10);
> +
> + if (limits->link.min_bpp_x16 < min_bpp_x16) {
> + drm_dbg_kms(&i915->drm,
> + "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " due to hblank expansion quirk\n",
> + crtc->base.base.id, crtc->base.name,
> + connector->base.base.id, connector->base.name,
> + BPP_X16_ARGS(min_bpp_x16));
> +
> + if (limits->link.max_bpp_x16 < min_bpp_x16)
> + return false;
> +
> + limits->link.min_bpp_x16 = min_bpp_x16;
> + }
> +
> + return true;
> +}
> +
> static bool
> intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> + const struct intel_connector *connector,
> struct intel_crtc_state *crtc_state,
> bool dsc,
> struct link_config_limits *limits)
> @@ -374,10 +435,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
>
> - return intel_dp_compute_config_link_bpp_limits(intel_dp,
> - crtc_state,
> - dsc,
> - limits);
> + if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
> + crtc_state,
> + dsc,
> + limits))
> + return false;
> +
> + return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
> + crtc_state,
> + limits,
> + dsc);
> }
>
> static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> @@ -404,6 +471,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> dsc_needed = intel_dp->force_dsc_en ||
> !intel_dp_mst_compute_config_limits(intel_dp,
> + connector,
> pipe_config,
> false,
> &limits);
> @@ -426,6 +494,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> str_yes_no(intel_dp->force_dsc_en));
>
> if (!intel_dp_mst_compute_config_limits(intel_dp,
> + connector,
> pipe_config,
> true,
> &limits))
> @@ -1205,6 +1274,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
> intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
> }
>
> +static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct drm_dp_desc desc;
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> +
> + if (!connector->dp.dsc_decompression_aux)
> + return false;
> +
> + if (drm_dp_read_desc(connector->dp.dsc_decompression_aux,
> + &desc, true) < 0)
> + return false;
> +
> + if (!drm_dp_has_quirk(&desc,
> + DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
> + return false;
> +
> + if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0)
> + return false;
> +
> + if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
> + return false;
> +
> + drm_dbg_kms(&i915->drm,
> + "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
> + connector->base.base.id, connector->base.name);
> +
> + return true;
> +}
> +
> static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
> struct drm_dp_mst_port *port,
> const char *pathprop)
> @@ -1245,6 +1344,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> */
> intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> + intel_connector->dp.dsc_hblank_expansion_quirk =
> + detect_dsc_hblank_expansion_quirk(intel_connector);
>
> for_each_pipe(dev_priv, pipe) {
> struct drm_encoder *enc =
> --
> 2.39.2
>
next prev parent reply other threads:[~2023-10-27 7:59 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 1:08 [Intel-gfx] [PATCH 00/29] drm/i915: Improve BW management on MST links Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 01/29] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 02/29] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-10-24 1:08 ` [Intel-gfx] [PATCH 03/29] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 04/29] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 05/29] drm/dp_mst: Allow DSC in any Synaptics last branch device Imre Deak
2023-10-27 9:21 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 06/29] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags Imre Deak
2023-10-27 9:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 07/29] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 9:23 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:22 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 08/29] drm/dp: Add helpers to calculate the link BW overhead Imre Deak
2023-10-24 2:47 ` kernel test robot
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:21 ` Lisovskiy, Stanislav
2023-10-24 12:34 ` [Intel-gfx] [PATCH " kernel test robot
2023-10-25 15:47 ` kernel test robot
2023-10-24 1:09 ` [Intel-gfx] [PATCH 09/29] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed Imre Deak
2023-10-24 17:27 ` Lisovskiy, Stanislav
2023-10-30 8:38 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 10/29] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder Imre Deak
2023-10-25 15:27 ` Ville Syrjälä
2023-10-25 15:37 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 11/29] drm/i915/dp: Pass actual BW overhead to m_n calculation Imre Deak
2023-10-24 17:28 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 12/29] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 13/29] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 14/29] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 15/29] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 16/29] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 17/29] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec() Imre Deak
2023-10-25 7:58 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 18/29] drm/i915/dp: Wait for FEC detected status in the sink Imre Deak
2023-10-24 17:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 19/29] drm/i915/dp: Disable FEC ready flag " Imre Deak
2023-10-25 8:01 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 20/29] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
2023-10-27 7:59 ` Lisovskiy, Stanislav [this message]
2023-10-24 1:09 ` [Intel-gfx] [PATCH 21/29] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
2023-10-27 12:24 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 22/29] drm/i915/dp: Enable DSC via the connector decompression AUX Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:27 ` Lisovskiy, Stanislav
2023-10-25 8:30 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2023-10-27 12:25 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 23/29] drm/i915/dp_mst: Enable DSC passthrough Imre Deak
2023-10-24 10:22 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-10-27 12:26 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 24/29] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
[not found] ` <ZTvNCgO9NF/rl1t+@intel.com>
[not found] ` <ZTvO3VK+sMksD69l@ideak-desk.fi.intel.com>
2023-10-30 7:29 ` Lisovskiy, Stanislav
2023-10-30 8:09 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 25/29] drm/i915: Factor out function to clear pipe update flags Imre Deak
[not found] ` <ZTvaXNT3C3VZGOel@intel.com>
2023-10-27 16:39 ` Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 26/29] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
2023-10-27 9:08 ` Lisovskiy, Stanislav
2023-10-24 1:09 ` [Intel-gfx] [PATCH 27/29] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 28/29] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-10-24 1:09 ` [Intel-gfx] [PATCH 29/29] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info Imre Deak
2023-10-30 4:17 ` Nautiyal, Ankit K
2023-10-30 5:29 ` Murthy, Arun R
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev5) Patchwork
2023-10-24 22:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-24 22:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-25 7:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-26 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev7) Patchwork
2023-10-27 22:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-27 23:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-30 21:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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