[Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes

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* [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes
@ 2023-11-28  8:37 Stanislav Lisovskiy
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling Stanislav Lisovskiy
                   ` (10 more replies)
  0 siblings, 11 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-11-28  8:37 UTC (permalink / raw)
  To: intel-gfx

We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.

Stanislav Lisovskiy (3):
  drm/i915: Add meaningful traces for QGV point info error handling
  drm/i915: Extract code required to calculate max qgv/psf gv point
  drm/i915: Disable SAGV on bw init, to force QGV point recalculation

 drivers/gpu/drm/i915/display/intel_bw.c | 104 ++++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_bw.h |   1 +
 drivers/gpu/drm/i915/soc/intel_dram.c   |   2 +
 3 files changed, 89 insertions(+), 18 deletions(-)

-- 
2.37.3


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
@ 2023-11-28  8:37 ` Stanislav Lisovskiy
  2023-11-28 12:53   ` Gustavo Sousa
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
                   ` (9 subsequent siblings)
  10 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-11-28  8:37 UTC (permalink / raw)
  To: intel-gfx

For debug purposes we need those - error path won't flood the log,
however there has been already numerous cases, when due to lack
of debugs, we couldn't immediately tell what was the problem on
customer machine, which slowed down the investigation, requiring
to get access to target device and adding those traces manually.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
 drivers/gpu/drm/i915/soc/intel_dram.c   | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bef96db62c80..583cd2ebdf89 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -289,8 +289,10 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 		struct intel_qgv_point *sp = &qi->points[i];
 
 		ret = intel_read_qgv_point_info(dev_priv, sp, i);
-		if (ret)
+		if (ret) {
+			drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i);
 			return ret;
+		}
 
 		drm_dbg_kms(&dev_priv->drm,
 			    "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 15492b69f698..37d61dff50a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -647,6 +647,8 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
 
 	dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
 	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
+	drm_dbg_kms(&i915->drm, "Num qgv points from MTL_N_OF_ENABLED_QGV_POINTS_MASK reg: %d\n",
+		    dram_info->num_qgv_points);
 	/* PSF GV points not supported in D14+ */
 
 	return 0;
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling Stanislav Lisovskiy
@ 2023-11-28 12:53   ` Gustavo Sousa
  0 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2023-11-28 12:53 UTC (permalink / raw)
  To: Stanislav Lisovskiy, intel-gfx

Quoting Stanislav Lisovskiy (2023-11-28 05:37:52-03:00)
>For debug purposes we need those - error path won't flood the log,
>however there has been already numerous cases, when due to lack
>of debugs, we couldn't immediately tell what was the problem on
>customer machine, which slowed down the investigation, requiring
>to get access to target device and adding those traces manually.
>
>Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
> drivers/gpu/drm/i915/soc/intel_dram.c   | 2 ++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>index bef96db62c80..583cd2ebdf89 100644
>--- a/drivers/gpu/drm/i915/display/intel_bw.c
>+++ b/drivers/gpu/drm/i915/display/intel_bw.c
>@@ -289,8 +289,10 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>                 struct intel_qgv_point *sp = &qi->points[i];
> 
>                 ret = intel_read_qgv_point_info(dev_priv, sp, i);
>-                if (ret)
>+                if (ret) {
>+                        drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i);
>                         return ret;
>+                }
> 
>                 drm_dbg_kms(&dev_priv->drm,
>                             "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
>diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>index 15492b69f698..37d61dff50a8 100644
>--- a/drivers/gpu/drm/i915/soc/intel_dram.c
>+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>@@ -647,6 +647,8 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
> 
>         dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
>         dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
>+        drm_dbg_kms(&i915->drm, "Num qgv points from MTL_N_OF_ENABLED_QGV_POINTS_MASK reg: %d\n",
>+                    dram_info->num_qgv_points);

Maybe use a more general message (not specific to MTL) and do this in
intel_dram_detect() instead?

--
Gustavo Sousa

>         /* PSF GV points not supported in D14+ */
> 
>         return 0;
>-- 
>2.37.3
>

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling Stanislav Lisovskiy
@ 2023-11-28  8:37 ` Stanislav Lisovskiy
  2024-01-12 17:35   ` Ville Syrjälä
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation Stanislav Lisovskiy
                   ` (8 subsequent siblings)
  10 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-11-28  8:37 UTC (permalink / raw)
  To: intel-gfx

We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we don't do that when we disable SAGV, which might be
actually causing some issues in that case.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
 1 file changed, 65 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 583cd2ebdf89..efd408e96e8a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
+					 int num_active_planes)
+{
+	unsigned int max_bw_point = 0;
+	unsigned int max_bw = 0;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	int i;
+
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int idx;
+		unsigned int max_data_rate;
+
+		if (DISPLAY_VER(i915) > 11)
+			idx = tgl_max_bw_index(i915, num_active_planes, i);
+		else
+			idx = icl_max_bw_index(i915, num_active_planes, i);
+
+		if (idx >= ARRAY_SIZE(i915->display.bw.max))
+			continue;
+
+		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+	}
+
+	return max_bw_point;
+}
+
+unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
+{
+	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
+	unsigned int max_bw = 0;
+	unsigned int max_bw_point = 0;
+	int i;
+
+	for (i = 0; i < num_psf_gv_points; i++) {
+		unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+	}
+
+	return max_bw_point;
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 			       const struct intel_bw_state *old_bw_state,
 			       struct intel_bw_state *new_bw_state)
 {
-	unsigned int max_bw_point = 0;
-	unsigned int max_bw = 0;
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
 	u16 psf_points = 0;
@@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 
 		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
 
-		/*
-		 * We need to know which qgv point gives us
-		 * maximum bandwidth in order to disable SAGV
-		 * if we find that we exceed SAGV block time
-		 * with watermarks. By that moment we already
-		 * have those, as it is calculated earlier in
-		 * intel_atomic_check,
-		 */
-		if (max_data_rate > max_bw) {
-			max_bw_point = i;
-			max_bw = max_data_rate;
-		}
 		if (max_data_rate >= data_rate)
 			qgv_points |= BIT(i);
 
@@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
-		qgv_points = BIT(max_bw_point);
-		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
-			    max_bw_point);
+		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
+		unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
+
+		qgv_points = BIT(max_bw_qgv_point);
+		psf_points = BIT(max_bw_psf_gv_point);
+		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d PSF GV point %d\n",
+			    max_bw_qgv_point, max_bw_psf_gv_point);
 	}
 
 	/*
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
@ 2024-01-12 17:35   ` Ville Syrjälä
  2024-01-17 10:12     ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2024-01-12 17:35 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Tue, Nov 28, 2023 at 10:37:53AM +0200, Stanislav Lisovskiy wrote:
> We need that in order to force disable SAGV in next patch.
> Also it is beneficial to separate that code, as in majority cases,
> when SAGV is enabled, we don't even need those calculations.
> Also we probably need to determine max PSF GV point as well, however
> currently we don't do that when we disable SAGV, which might be
> actually causing some issues in that case.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
>  1 file changed, 65 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 583cd2ebdf89..efd408e96e8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
>  	return to_intel_bw_state(bw_state);
>  }
>  
> +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> +					 int num_active_planes)
> +{
> +	unsigned int max_bw_point = 0;
> +	unsigned int max_bw = 0;
> +	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> +	int i;
> +
> +	for (i = 0; i < num_qgv_points; i++) {
> +		unsigned int idx;
> +		unsigned int max_data_rate;
> +
> +		if (DISPLAY_VER(i915) > 11)
> +			idx = tgl_max_bw_index(i915, num_active_planes, i);
> +		else
> +			idx = icl_max_bw_index(i915, num_active_planes, i);
> +
> +		if (idx >= ARRAY_SIZE(i915->display.bw.max))
> +			continue;
> +
> +		max_data_rate = i915->display.bw.max[idx].deratedbw[i];

Looks like that that part could be extracted to a helper
to be used by both codepaths (would be a natural counterpart
to adl_psf_bw()).

> +
> +		/*
> +		 * We need to know which qgv point gives us
> +		 * maximum bandwidth in order to disable SAGV
> +		 * if we find that we exceed SAGV block time
> +		 * with watermarks. By that moment we already
> +		 * have those, as it is calculated earlier in
> +		 * intel_atomic_check,
> +		 */
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +	}
> +
> +	return max_bw_point;
> +}
> +
> +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
> +{
> +	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> +	unsigned int max_bw = 0;
> +	unsigned int max_bw_point = 0;
> +	int i;
> +
> +	for (i = 0; i < num_psf_gv_points; i++) {
> +		unsigned int max_data_rate = adl_psf_bw(i915, i);
> +
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +	}
> +
> +	return max_bw_point;
> +}
> +
>  static int mtl_find_qgv_points(struct drm_i915_private *i915,
>  			       unsigned int data_rate,
>  			       unsigned int num_active_planes,
> @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  			       const struct intel_bw_state *old_bw_state,
>  			       struct intel_bw_state *new_bw_state)
>  {
> -	unsigned int max_bw_point = 0;
> -	unsigned int max_bw = 0;
>  	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
>  	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
>  	u16 psf_points = 0;
> @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  
>  		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
>  
> -		/*
> -		 * We need to know which qgv point gives us
> -		 * maximum bandwidth in order to disable SAGV
> -		 * if we find that we exceed SAGV block time
> -		 * with watermarks. By that moment we already
> -		 * have those, as it is calculated earlier in
> -		 * intel_atomic_check,
> -		 */
> -		if (max_data_rate > max_bw) {
> -			max_bw_point = i;
> -			max_bw = max_data_rate;
> -		}
>  		if (max_data_rate >= data_rate)
>  			qgv_points |= BIT(i);
>  
> @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  	 * cause.
>  	 */
>  	if (!intel_can_enable_sagv(i915, new_bw_state)) {
> -		qgv_points = BIT(max_bw_point);
> -		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> -			    max_bw_point);
> +		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> +		unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
> +
> +		qgv_points = BIT(max_bw_qgv_point);
> +		psf_points = BIT(max_bw_psf_gv_point);

We didn't restrict the PSF here previously.

> +		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d PSF GV point %d\n",
> +			    max_bw_qgv_point, max_bw_psf_gv_point);
>  	}
>  
>  	/*
> -- 
> 2.37.3

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-01-12 17:35   ` Ville Syrjälä
@ 2024-01-17 10:12     ` Lisovskiy, Stanislav
  2024-01-17 11:12       ` Ville Syrjälä
  0 siblings, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2024-01-17 10:12 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, Jan 12, 2024 at 07:35:24PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:37:53AM +0200, Stanislav Lisovskiy wrote:
> > We need that in order to force disable SAGV in next patch.
> > Also it is beneficial to separate that code, as in majority cases,
> > when SAGV is enabled, we don't even need those calculations.
> > Also we probably need to determine max PSF GV point as well, however
> > currently we don't do that when we disable SAGV, which might be
> > actually causing some issues in that case.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
> >  1 file changed, 65 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 583cd2ebdf89..efd408e96e8a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
> >  	return to_intel_bw_state(bw_state);
> >  }
> >  
> > +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> > +					 int num_active_planes)
> > +{
> > +	unsigned int max_bw_point = 0;
> > +	unsigned int max_bw = 0;
> > +	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > +	int i;
> > +
> > +	for (i = 0; i < num_qgv_points; i++) {
> > +		unsigned int idx;
> > +		unsigned int max_data_rate;
> > +
> > +		if (DISPLAY_VER(i915) > 11)
> > +			idx = tgl_max_bw_index(i915, num_active_planes, i);
> > +		else
> > +			idx = icl_max_bw_index(i915, num_active_planes, i);
> > +
> > +		if (idx >= ARRAY_SIZE(i915->display.bw.max))
> > +			continue;
> > +
> > +		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> 
> Looks like that that part could be extracted to a helper
> to be used by both codepaths (would be a natural counterpart
> to adl_psf_bw()).
> 
> > +
> > +		/*
> > +		 * We need to know which qgv point gives us
> > +		 * maximum bandwidth in order to disable SAGV
> > +		 * if we find that we exceed SAGV block time
> > +		 * with watermarks. By that moment we already
> > +		 * have those, as it is calculated earlier in
> > +		 * intel_atomic_check,
> > +		 */
> > +		if (max_data_rate > max_bw) {
> > +			max_bw_point = i;
> > +			max_bw = max_data_rate;
> > +		}
> > +	}
> > +
> > +	return max_bw_point;
> > +}
> > +
> > +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
> > +{
> > +	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> > +	unsigned int max_bw = 0;
> > +	unsigned int max_bw_point = 0;
> > +	int i;
> > +
> > +	for (i = 0; i < num_psf_gv_points; i++) {
> > +		unsigned int max_data_rate = adl_psf_bw(i915, i);
> > +
> > +		if (max_data_rate > max_bw) {
> > +			max_bw_point = i;
> > +			max_bw = max_data_rate;
> > +		}
> > +	}
> > +
> > +	return max_bw_point;
> > +}
> > +
> >  static int mtl_find_qgv_points(struct drm_i915_private *i915,
> >  			       unsigned int data_rate,
> >  			       unsigned int num_active_planes,
> > @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> >  			       const struct intel_bw_state *old_bw_state,
> >  			       struct intel_bw_state *new_bw_state)
> >  {
> > -	unsigned int max_bw_point = 0;
> > -	unsigned int max_bw = 0;
> >  	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> >  	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> >  	u16 psf_points = 0;
> > @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> >  
> >  		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> >  
> > -		/*
> > -		 * We need to know which qgv point gives us
> > -		 * maximum bandwidth in order to disable SAGV
> > -		 * if we find that we exceed SAGV block time
> > -		 * with watermarks. By that moment we already
> > -		 * have those, as it is calculated earlier in
> > -		 * intel_atomic_check,
> > -		 */
> > -		if (max_data_rate > max_bw) {
> > -			max_bw_point = i;
> > -			max_bw = max_data_rate;
> > -		}
> >  		if (max_data_rate >= data_rate)
> >  			qgv_points |= BIT(i);
> >  
> > @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> >  	 * cause.
> >  	 */
> >  	if (!intel_can_enable_sagv(i915, new_bw_state)) {
> > -		qgv_points = BIT(max_bw_point);
> > -		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> > -			    max_bw_point);
> > +		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> > +		unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
> > +
> > +		qgv_points = BIT(max_bw_qgv_point);
> > +		psf_points = BIT(max_bw_psf_gv_point);
> 
> We didn't restrict the PSF here previously.

Yep, but I really suspect we should. BSpec states that we should restrict all the GV points
except highest one, also that some PSF GV points aren't same or usable, depending on BW reqs.
So I would restrict that as well, in case if SAGV is off, just to be on safe side.

Stan

> 
> > +		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d PSF GV point %d\n",
> > +			    max_bw_qgv_point, max_bw_psf_gv_point);
> >  	}
> >  
> >  	/*
> > -- 
> > 2.37.3
> 
> -- 
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-01-17 10:12     ` Lisovskiy, Stanislav
@ 2024-01-17 11:12       ` Ville Syrjälä
  2024-01-17 11:23         ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2024-01-17 11:12 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

On Wed, Jan 17, 2024 at 12:12:18PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Jan 12, 2024 at 07:35:24PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 28, 2023 at 10:37:53AM +0200, Stanislav Lisovskiy wrote:
> > > We need that in order to force disable SAGV in next patch.
> > > Also it is beneficial to separate that code, as in majority cases,
> > > when SAGV is enabled, we don't even need those calculations.
> > > Also we probably need to determine max PSF GV point as well, however
> > > currently we don't do that when we disable SAGV, which might be
> > > actually causing some issues in that case.
> > > 
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
> > >  1 file changed, 65 insertions(+), 17 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index 583cd2ebdf89..efd408e96e8a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
> > >  	return to_intel_bw_state(bw_state);
> > >  }
> > >  
> > > +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> > > +					 int num_active_planes)
> > > +{
> > > +	unsigned int max_bw_point = 0;
> > > +	unsigned int max_bw = 0;
> > > +	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > > +	int i;
> > > +
> > > +	for (i = 0; i < num_qgv_points; i++) {
> > > +		unsigned int idx;
> > > +		unsigned int max_data_rate;
> > > +
> > > +		if (DISPLAY_VER(i915) > 11)
> > > +			idx = tgl_max_bw_index(i915, num_active_planes, i);
> > > +		else
> > > +			idx = icl_max_bw_index(i915, num_active_planes, i);
> > > +
> > > +		if (idx >= ARRAY_SIZE(i915->display.bw.max))
> > > +			continue;
> > > +
> > > +		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > 
> > Looks like that that part could be extracted to a helper
> > to be used by both codepaths (would be a natural counterpart
> > to adl_psf_bw()).
> > 
> > > +
> > > +		/*
> > > +		 * We need to know which qgv point gives us
> > > +		 * maximum bandwidth in order to disable SAGV
> > > +		 * if we find that we exceed SAGV block time
> > > +		 * with watermarks. By that moment we already
> > > +		 * have those, as it is calculated earlier in
> > > +		 * intel_atomic_check,
> > > +		 */
> > > +		if (max_data_rate > max_bw) {
> > > +			max_bw_point = i;
> > > +			max_bw = max_data_rate;
> > > +		}
> > > +	}
> > > +
> > > +	return max_bw_point;
> > > +}
> > > +
> > > +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
> > > +{
> > > +	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> > > +	unsigned int max_bw = 0;
> > > +	unsigned int max_bw_point = 0;
> > > +	int i;
> > > +
> > > +	for (i = 0; i < num_psf_gv_points; i++) {
> > > +		unsigned int max_data_rate = adl_psf_bw(i915, i);
> > > +
> > > +		if (max_data_rate > max_bw) {
> > > +			max_bw_point = i;
> > > +			max_bw = max_data_rate;
> > > +		}
> > > +	}
> > > +
> > > +	return max_bw_point;
> > > +}
> > > +
> > >  static int mtl_find_qgv_points(struct drm_i915_private *i915,
> > >  			       unsigned int data_rate,
> > >  			       unsigned int num_active_planes,
> > > @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > >  			       const struct intel_bw_state *old_bw_state,
> > >  			       struct intel_bw_state *new_bw_state)
> > >  {
> > > -	unsigned int max_bw_point = 0;
> > > -	unsigned int max_bw = 0;
> > >  	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> > >  	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > >  	u16 psf_points = 0;
> > > @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > >  
> > >  		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > >  
> > > -		/*
> > > -		 * We need to know which qgv point gives us
> > > -		 * maximum bandwidth in order to disable SAGV
> > > -		 * if we find that we exceed SAGV block time
> > > -		 * with watermarks. By that moment we already
> > > -		 * have those, as it is calculated earlier in
> > > -		 * intel_atomic_check,
> > > -		 */
> > > -		if (max_data_rate > max_bw) {
> > > -			max_bw_point = i;
> > > -			max_bw = max_data_rate;
> > > -		}
> > >  		if (max_data_rate >= data_rate)
> > >  			qgv_points |= BIT(i);
> > >  
> > > @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > >  	 * cause.
> > >  	 */
> > >  	if (!intel_can_enable_sagv(i915, new_bw_state)) {
> > > -		qgv_points = BIT(max_bw_point);
> > > -		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> > > -			    max_bw_point);
> > > +		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> > > +		unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
> > > +
> > > +		qgv_points = BIT(max_bw_qgv_point);
> > > +		psf_points = BIT(max_bw_psf_gv_point);
> > 
> > We didn't restrict the PSF here previously.
> 
> Yep, but I really suspect we should. BSpec states that we should restrict all the GV points
> except highest one, also that some PSF GV points aren't same or usable, depending on BW reqs.
> So I would restrict that as well, in case if SAGV is off, just to be on safe side.

Pretty sure it's explicitly noted that PSF doesn't cause issues with
latency and hence doesn't need this.

In any case, a change like this has no business being in a patch
that's just supposed to refactor code.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-01-17 11:12       ` Ville Syrjälä
@ 2024-01-17 11:23         ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2024-01-17 11:23 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Wed, Jan 17, 2024 at 01:12:49PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 17, 2024 at 12:12:18PM +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Jan 12, 2024 at 07:35:24PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 28, 2023 at 10:37:53AM +0200, Stanislav Lisovskiy wrote:
> > > > We need that in order to force disable SAGV in next patch.
> > > > Also it is beneficial to separate that code, as in majority cases,
> > > > when SAGV is enabled, we don't even need those calculations.
> > > > Also we probably need to determine max PSF GV point as well, however
> > > > currently we don't do that when we disable SAGV, which might be
> > > > actually causing some issues in that case.
> > > > 
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
> > > >  1 file changed, 65 insertions(+), 17 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > index 583cd2ebdf89..efd408e96e8a 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
> > > >  	return to_intel_bw_state(bw_state);
> > > >  }
> > > >  
> > > > +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> > > > +					 int num_active_planes)
> > > > +{
> > > > +	unsigned int max_bw_point = 0;
> > > > +	unsigned int max_bw = 0;
> > > > +	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > > > +	int i;
> > > > +
> > > > +	for (i = 0; i < num_qgv_points; i++) {
> > > > +		unsigned int idx;
> > > > +		unsigned int max_data_rate;
> > > > +
> > > > +		if (DISPLAY_VER(i915) > 11)
> > > > +			idx = tgl_max_bw_index(i915, num_active_planes, i);
> > > > +		else
> > > > +			idx = icl_max_bw_index(i915, num_active_planes, i);
> > > > +
> > > > +		if (idx >= ARRAY_SIZE(i915->display.bw.max))
> > > > +			continue;
> > > > +
> > > > +		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > > 
> > > Looks like that that part could be extracted to a helper
> > > to be used by both codepaths (would be a natural counterpart
> > > to adl_psf_bw()).
> > > 
> > > > +
> > > > +		/*
> > > > +		 * We need to know which qgv point gives us
> > > > +		 * maximum bandwidth in order to disable SAGV
> > > > +		 * if we find that we exceed SAGV block time
> > > > +		 * with watermarks. By that moment we already
> > > > +		 * have those, as it is calculated earlier in
> > > > +		 * intel_atomic_check,
> > > > +		 */
> > > > +		if (max_data_rate > max_bw) {
> > > > +			max_bw_point = i;
> > > > +			max_bw = max_data_rate;
> > > > +		}
> > > > +	}
> > > > +
> > > > +	return max_bw_point;
> > > > +}
> > > > +
> > > > +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
> > > > +{
> > > > +	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> > > > +	unsigned int max_bw = 0;
> > > > +	unsigned int max_bw_point = 0;
> > > > +	int i;
> > > > +
> > > > +	for (i = 0; i < num_psf_gv_points; i++) {
> > > > +		unsigned int max_data_rate = adl_psf_bw(i915, i);
> > > > +
> > > > +		if (max_data_rate > max_bw) {
> > > > +			max_bw_point = i;
> > > > +			max_bw = max_data_rate;
> > > > +		}
> > > > +	}
> > > > +
> > > > +	return max_bw_point;
> > > > +}
> > > > +
> > > >  static int mtl_find_qgv_points(struct drm_i915_private *i915,
> > > >  			       unsigned int data_rate,
> > > >  			       unsigned int num_active_planes,
> > > > @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > > >  			       const struct intel_bw_state *old_bw_state,
> > > >  			       struct intel_bw_state *new_bw_state)
> > > >  {
> > > > -	unsigned int max_bw_point = 0;
> > > > -	unsigned int max_bw = 0;
> > > >  	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
> > > >  	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > > >  	u16 psf_points = 0;
> > > > @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > > >  
> > > >  		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > > >  
> > > > -		/*
> > > > -		 * We need to know which qgv point gives us
> > > > -		 * maximum bandwidth in order to disable SAGV
> > > > -		 * if we find that we exceed SAGV block time
> > > > -		 * with watermarks. By that moment we already
> > > > -		 * have those, as it is calculated earlier in
> > > > -		 * intel_atomic_check,
> > > > -		 */
> > > > -		if (max_data_rate > max_bw) {
> > > > -			max_bw_point = i;
> > > > -			max_bw = max_data_rate;
> > > > -		}
> > > >  		if (max_data_rate >= data_rate)
> > > >  			qgv_points |= BIT(i);
> > > >  
> > > > @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
> > > >  	 * cause.
> > > >  	 */
> > > >  	if (!intel_can_enable_sagv(i915, new_bw_state)) {
> > > > -		qgv_points = BIT(max_bw_point);
> > > > -		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> > > > -			    max_bw_point);
> > > > +		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> > > > +		unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
> > > > +
> > > > +		qgv_points = BIT(max_bw_qgv_point);
> > > > +		psf_points = BIT(max_bw_psf_gv_point);
> > > 
> > > We didn't restrict the PSF here previously.
> > 
> > Yep, but I really suspect we should. BSpec states that we should restrict all the GV points
> > except highest one, also that some PSF GV points aren't same or usable, depending on BW reqs.
> > So I would restrict that as well, in case if SAGV is off, just to be on safe side.
> 
> Pretty sure it's explicitly noted that PSF doesn't cause issues with
> latency and hence doesn't need this.
> 
> In any case, a change like this has no business being in a patch
> that's just supposed to refactor code.

Ok, lets drop this, until clarified.

Stan

> 
> -- 
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling Stanislav Lisovskiy
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
@ 2023-11-28  8:37 ` Stanislav Lisovskiy
  2023-11-29  9:21   ` Stanislav Lisovskiy
  2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes Patchwork
                   ` (7 subsequent siblings)
  10 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-11-28  8:37 UTC (permalink / raw)
  To: intel-gfx

Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h |  1 +
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index efd408e96e8a..f23f9f952de3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -679,6 +679,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		tgl_get_bw_info(dev_priv, &tgl_sa_info);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
+
+	if (DISPLAY_VER(dev_priv) < 14)
+		icl_force_disable_sagv(dev_priv);
 }
 
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
@@ -844,7 +847,7 @@ static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
 	return max_bw_point;
 }
 
-unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
+static unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 {
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int max_bw = 0;
@@ -863,6 +866,21 @@ unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 	return max_bw_point;
 }
 
+int icl_force_disable_sagv(struct drm_i915_private *i915)
+{
+	unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
+	unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
+	unsigned int qgv_points;
+	unsigned int psf_points;
+
+	qgv_points = BIT(max_bw_qgv_point);
+	psf_points = BIT(max_bw_psf_gv_point);
+
+	return icl_pcode_restrict_qgv_points(i915, ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+					     ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+					     icl_qgv_points_mask(i915));
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 59cb4fc5db76..74acce1ef107 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -74,5 +74,6 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 			    bool *need_cdclk_calc);
 int intel_bw_min_cdclk(struct drm_i915_private *i915,
 		       const struct intel_bw_state *bw_state);
+int icl_force_disable_sagv(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_BW_H__ */
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation Stanislav Lisovskiy
@ 2023-11-29  9:21   ` Stanislav Lisovskiy
  2023-12-01 14:35     ` Stanislav Lisovskiy
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-11-29  9:21 UTC (permalink / raw)
  To: intel-gfx

Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.

v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
      disabled.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 23 ++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h |  1 +
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index efd408e96e8a..abb72207894d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -679,6 +679,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		tgl_get_bw_info(dev_priv, &tgl_sa_info);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
+
+	if (DISPLAY_VER(dev_priv) < 14)
+		icl_force_disable_sagv(dev_priv);
 }
 
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
@@ -844,7 +847,7 @@ static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
 	return max_bw_point;
 }
 
-unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
+static unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 {
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int max_bw = 0;
@@ -863,6 +866,24 @@ unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 	return max_bw_point;
 }
 
+int icl_force_disable_sagv(struct drm_i915_private *i915)
+{
+	unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
+	unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
+	unsigned int qgv_points;
+	unsigned int psf_points;
+
+	qgv_points = BIT(max_bw_qgv_point);
+	psf_points = BIT(max_bw_psf_gv_point);
+
+	drm_dbg_kms(&i915->drm, "Forcing SAGV disable: leaving QGV point %d, PSF GV %d\n",
+				max_bw_qgv_point, max_bw_psf_gv_point);
+
+	return icl_pcode_restrict_qgv_points(i915, ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+					     ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+					     icl_qgv_points_mask(i915));
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 59cb4fc5db76..74acce1ef107 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -74,5 +74,6 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 			    bool *need_cdclk_calc);
 int intel_bw_min_cdclk(struct drm_i915_private *i915,
 		       const struct intel_bw_state *bw_state);
+int icl_force_disable_sagv(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_BW_H__ */
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation
  2023-11-29  9:21   ` Stanislav Lisovskiy
@ 2023-12-01 14:35     ` Stanislav Lisovskiy
  0 siblings, 0 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2023-12-01 14:35 UTC (permalink / raw)
  To: intel-gfx

Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.

v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
      disabled.
v3: - Move force disable function to intel_bw_init in order to initialize
      bw state as well, so that hw/sw are immediately in sync after init.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 25 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h |  2 ++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index efd408e96e8a..7db28c6631fc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -844,7 +844,7 @@ static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
 	return max_bw_point;
 }
 
-unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
+static unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 {
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int max_bw = 0;
@@ -863,6 +863,26 @@ unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
 	return max_bw_point;
 }
 
+int icl_force_disable_sagv(struct drm_i915_private *i915, struct intel_bw_state *bw_state)
+{
+	unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
+	unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
+	unsigned int qgv_points;
+	unsigned int psf_points;
+
+	qgv_points = BIT(max_bw_qgv_point);
+	psf_points = BIT(max_bw_psf_gv_point);
+
+	bw_state->qgv_points_mask = ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+				      ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+				      icl_qgv_points_mask(i915);
+
+	drm_dbg_kms(&i915->drm, "Forcing SAGV disable: leaving QGV point %d, PSF GV %d\n",
+				max_bw_qgv_point, max_bw_psf_gv_point);
+
+	return icl_pcode_restrict_qgv_points(i915, bw_state->qgv_points_mask);
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -1373,5 +1393,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
 	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
 				     &state->base, &intel_bw_funcs);
 
+	if (DISPLAY_VER(dev_priv) < 14)
+		icl_force_disable_sagv(dev_priv, state);
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 59cb4fc5db76..d6eb771baea1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -74,5 +74,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 			    bool *need_cdclk_calc);
 int intel_bw_min_cdclk(struct drm_i915_private *i915,
 		       const struct intel_bw_state *bw_state);
+int icl_force_disable_sagv(struct drm_i915_private *dev_priv,
+			   struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (2 preceding siblings ...)
  2023-11-28  8:37 ` [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation Stanislav Lisovskiy
@ 2023-11-28  9:20 ` Patchwork
  2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-28  9:20 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

== Series Details ==

Series: QGV/SAGV related fixes
URL   : https://patchwork.freedesktop.org/series/126962/
State : warning

== Summary ==

Error: dim checkpatch failed
e47332e38255 drm/i915: Add meaningful traces for QGV point info error handling
0ae02a74f8db drm/i915: Extract code required to calculate max qgv/psf gv point
c7ba67f6833b drm/i915: Disable SAGV on bw init, to force QGV point recalculation
-:9: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#9: 
(i.e all points allowed), however in reality we might get them all restricted,

total: 0 errors, 1 warnings, 0 checks, 44 lines checked



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for QGV/SAGV related fixes
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (3 preceding siblings ...)
  2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes Patchwork
@ 2023-11-28  9:20 ` Patchwork
  2023-11-28  9:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-28  9:20 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

== Series Details ==

Series: QGV/SAGV related fixes
URL   : https://patchwork.freedesktop.org/series/126962/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for QGV/SAGV related fixes
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (4 preceding siblings ...)
  2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-11-28  9:41 ` Patchwork
  2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev2) Patchwork
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-28  9:41 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 19728 bytes --]

== Series Details ==

Series: QGV/SAGV related fixes
URL   : https://patchwork.freedesktop.org/series/126962/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13931 -> Patchwork_126962v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_126962v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_126962v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/index.html

Participating hosts (36 -> 33)
------------------------------

  Additional (1): bat-rpls-1 
  Missing    (4): bat-dg2-14 bat-adlm-1 fi-snb-2520m bat-mtlp-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_126962v1:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-elk-e7500:       [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-elk-e7500/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-elk-e7500/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_module_load@load:
    - bat-adlp-6:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-6/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-6/igt@i915_module_load@load.html
    - fi-elk-e7500:       [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-elk-e7500/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-elk-e7500/igt@i915_module_load@load.html
    - bat-adlp-11:        [PASS][7] -> [DMESG-WARN][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-11/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-11/igt@i915_module_load@load.html

  * igt@i915_module_load@reload:
    - fi-pnv-d510:        [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-pnv-d510/igt@i915_module_load@reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-pnv-d510/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - bat-kbl-2:          [PASS][11] -> [DMESG-WARN][12] +42 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-kbl-2/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-kbl-2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@client:
    - fi-kbl-guc:         [PASS][13] -> [DMESG-WARN][14] +42 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-kbl-guc/igt@i915_selftest@live@client.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-kbl-guc/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@coherency:
    - bat-dg2-9:          [PASS][15] -> [DMESG-WARN][16] +39 other tests dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-9/igt@i915_selftest@live@coherency.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-9/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@gem:
    - fi-rkl-11600:       [PASS][17] -> [DMESG-WARN][18] +42 other tests dmesg-warn
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-rkl-11600/igt@i915_selftest@live@gem.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-rkl-11600/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cfl-guc:         [PASS][19] -> [DMESG-WARN][20] +42 other tests dmesg-warn
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
    - fi-skl-6600u:       [PASS][21] -> [DMESG-WARN][22] +38 other tests dmesg-warn
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_contexts:
    - fi-ilk-650:         [PASS][23] -> [DMESG-WARN][24] +41 other tests dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html

  * igt@i915_selftest@live@gt_mocs:
    - fi-glk-j4005:       [PASS][25] -> [DMESG-WARN][26] +42 other tests dmesg-warn
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
    - fi-tgl-1115g4:      [PASS][27] -> [DMESG-WARN][28] +41 other tests dmesg-warn
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@gt_tlb:
    - bat-adlp-9:         [PASS][29] -> [DMESG-WARN][30] +39 other tests dmesg-warn
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html

  * igt@i915_selftest@live@perf:
    - bat-dg2-11:         [PASS][31] -> [DMESG-WARN][32] +40 other tests dmesg-warn
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-11/igt@i915_selftest@live@perf.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-11/igt@i915_selftest@live@perf.html
    - fi-kbl-x1275:       [PASS][33] -> [DMESG-WARN][34] +41 other tests dmesg-warn
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-kbl-x1275/igt@i915_selftest@live@perf.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-kbl-x1275/igt@i915_selftest@live@perf.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][35] -> [DMESG-WARN][36] +41 other tests dmesg-warn
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-apl-guc/igt@i915_selftest@live@reset.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-apl-guc/igt@i915_selftest@live@reset.html
    - bat-dg1-5:          [PASS][37] -> [DMESG-WARN][38] +42 other tests dmesg-warn
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg1-5/igt@i915_selftest@live@reset.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg1-5/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [PASS][39] -> [DMESG-WARN][40] +41 other tests dmesg-warn
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7567u:       [PASS][41] -> [DMESG-WARN][42] +42 other tests dmesg-warn
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
    - fi-cfl-8700k:       [PASS][43] -> [DMESG-WARN][44] +42 other tests dmesg-warn
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@uncore:
    - bat-dg1-7:          [PASS][45] -> [DMESG-WARN][46] +42 other tests dmesg-warn
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg1-7/igt@i915_selftest@live@uncore.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg1-7/igt@i915_selftest@live@uncore.html

  * igt@i915_selftest@live@vma:
    - fi-skl-guc:         [PASS][47] -> [DMESG-WARN][48] +42 other tests dmesg-warn
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-skl-guc/igt@i915_selftest@live@vma.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-skl-guc/igt@i915_selftest@live@vma.html

  * igt@i915_selftest@live@workarounds:
    - bat-rpls-1:         NOTRUN -> [DMESG-WARN][49] +40 other tests dmesg-warn
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@i915_selftest@live@workarounds.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@load:
    - {bat-dg2-13}:       [PASS][50] -> [DMESG-WARN][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-13/igt@i915_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-13/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_126962v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rpls-1:         NOTRUN -> [SKIP][52] ([i915#9318])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@info:
    - bat-rpls-1:         NOTRUN -> [SKIP][53] ([i915#1849] / [i915#2582])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@fbdev@info.html

  * igt@fbdev@write:
    - bat-rpls-1:         NOTRUN -> [SKIP][54] ([i915#2582]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@fbdev@write.html

  * igt@gem_lmem_swapping@random-engines:
    - bat-rpls-1:         NOTRUN -> [SKIP][55] ([i915#4613]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_tiled_pread_basic:
    - bat-rpls-1:         NOTRUN -> [SKIP][56] ([i915#3282])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [PASS][57] -> [DMESG-WARN][58] ([i915#1982])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-apl-guc/igt@i915_module_load@reload.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-apl-guc/igt@i915_module_load@reload.html
    - bat-adlp-9:         [PASS][59] -> [DMESG-WARN][60] ([i915#1982])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-9/igt@i915_module_load@reload.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-9/igt@i915_module_load@reload.html
    - bat-dg2-9:          [PASS][61] -> [DMESG-WARN][62] ([i915#1982])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-9/igt@i915_module_load@reload.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-9/igt@i915_module_load@reload.html
    - fi-cfl-8109u:       [PASS][63] -> [DMESG-WARN][64] ([i915#1982])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-cfl-8109u/igt@i915_module_load@reload.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-cfl-8109u/igt@i915_module_load@reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-rpls-1:         NOTRUN -> [SKIP][65] ([i915#6621])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-dg2-9:          [PASS][66] -> [DMESG-WARN][67] ([i915#7699]) +1 other test dmesg-warn
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-9/igt@i915_selftest@live@gt_heartbeat.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-9/igt@i915_selftest@live@gt_heartbeat.html
    - bat-rpls-1:         NOTRUN -> [DMESG-WARN][68] ([i915#7699]) +1 other test dmesg-warn
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-9:         [PASS][69] -> [DMESG-WARN][70] ([i915#7699]) +1 other test dmesg-warn
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-9/igt@i915_selftest@live@migrate.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-9/igt@i915_selftest@live@migrate.html
    - bat-dg2-11:         [PASS][71] -> [DMESG-WARN][72] ([i915#7699]) +1 other test dmesg-warn
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-skl-6600u:       [PASS][73] -> [DMESG-WARN][74] ([i915#1982]) +3 other tests dmesg-warn
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-rpls-1:         NOTRUN -> [SKIP][75] ([i915#1845]) +17 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - bat-rpls-1:         NOTRUN -> [SKIP][76] ([i915#3637]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-rpls-1:         NOTRUN -> [SKIP][77] ([fdo#109285])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-rpls-1:         NOTRUN -> [SKIP][78] ([i915#1849] / [i915#5354])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [PASS][79] -> [ABORT][80] ([i915#8668])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rpls-1:         NOTRUN -> [SKIP][81] ([i915#3555])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-rpls-1:         NOTRUN -> [SKIP][82] ([fdo#109295] / [i915#1845] / [i915#3708])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-write:
    - bat-rpls-1:         NOTRUN -> [SKIP][83] ([fdo#109295] / [i915#3708]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-rpls-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-dg2-9:          [INCOMPLETE][84] ([i915#9275]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-5:
    - bat-adlp-11:        [DMESG-FAIL][86] ([i915#6868]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-5.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-5.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-5:
    - bat-adlp-11:        [FAIL][88] ([i915#9666]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13931/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-5.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-5.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9666]: https://gitlab.freedesktop.org/drm/intel/issues/9666
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736


Build changes
-------------

  * Linux: CI_DRM_13931 -> Patchwork_126962v1

  CI-20190529: 20190529
  CI_DRM_13931: 78b2fab242c3badfa58865875274e8992de56370 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7605: 7605
  Patchwork_126962v1: 78b2fab242c3badfa58865875274e8992de56370 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

a9c9a0ff0cc6 drm/i915: Disable SAGV on bw init, to force QGV point recalculation
6e050232d077 drm/i915: Extract code required to calculate max qgv/psf gv point
0a28fc5327b1 drm/i915: Add meaningful traces for QGV point info error handling

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v1/index.html

[-- Attachment #2: Type: text/html, Size: 22274 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev2)
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (5 preceding siblings ...)
  2023-11-28  9:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-11-29 14:00 ` Patchwork
  2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-29 14:00 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: QGV/SAGV related fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/126962/
State : warning

== Summary ==

Error: dim checkpatch failed
6deb00a50791 drm/i915: Add meaningful traces for QGV point info error handling
9d4a009f4cbe drm/i915: Extract code required to calculate max qgv/psf gv point
8bada644db44 drm/i915: Disable SAGV on bw init, to force QGV point recalculation
-:9: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#9: 
(i.e all points allowed), however in reality we might get them all restricted,

-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/display/intel_bw.c:880:
+	drm_dbg_kms(&i915->drm, "Forcing SAGV disable: leaving QGV point %d, PSF GV %d\n",
+				max_bw_qgv_point, max_bw_psf_gv_point);

total: 0 errors, 1 warnings, 1 checks, 47 lines checked



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for QGV/SAGV related fixes (rev2)
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (6 preceding siblings ...)
  2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev2) Patchwork
@ 2023-11-29 14:00 ` Patchwork
  2023-11-29 14:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-29 14:00 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: QGV/SAGV related fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/126962/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for QGV/SAGV related fixes (rev2)
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (7 preceding siblings ...)
  2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-11-29 14:21 ` Patchwork
  2023-12-02  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev3) Patchwork
  2023-12-02  1:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-11-29 14:21 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 32021 bytes --]

== Series Details ==

Series: QGV/SAGV related fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/126962/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13945 -> Patchwork_126962v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_126962v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_126962v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/index.html

Participating hosts (37 -> 38)
------------------------------

  Additional (2): bat-mtlp-8 fi-pnv-d510 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_126962v2:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-pnv-d510:        NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-pnv-d510/igt@core_hotunplug@unbind-rebind.html
    - fi-elk-e7500:       [PASS][2] -> [ABORT][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-elk-e7500/igt@core_hotunplug@unbind-rebind.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-elk-e7500/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - fi-skl-6600u:       [PASS][4] -> [INCOMPLETE][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-skl-6600u/igt@gem_exec_suspend@basic-s0@smem.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-skl-6600u/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_module_load@load:
    - fi-elk-e7500:       [PASS][6] -> [DMESG-WARN][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-elk-e7500/igt@i915_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-elk-e7500/igt@i915_module_load@load.html
    - bat-adlp-11:        [PASS][8] -> [DMESG-WARN][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-adlp-11/igt@i915_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-adlp-11/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@module-reload:
    - bat-kbl-2:          [PASS][10] -> [DMESG-WARN][11] +42 other tests dmesg-warn
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-kbl-2/igt@i915_pm_rpm@module-reload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-kbl-2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@client:
    - fi-kbl-guc:         [PASS][12] -> [DMESG-WARN][13] +42 other tests dmesg-warn
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-kbl-guc/igt@i915_selftest@live@client.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-kbl-guc/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@coherency:
    - bat-dg2-9:          [PASS][14] -> [DMESG-WARN][15] +40 other tests dmesg-warn
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-9/igt@i915_selftest@live@coherency.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-9/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@gem:
    - fi-rkl-11600:       [PASS][16] -> [DMESG-WARN][17] +42 other tests dmesg-warn
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-rkl-11600/igt@i915_selftest@live@gem.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-rkl-11600/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cfl-guc:         [PASS][18] -> [DMESG-WARN][19] +42 other tests dmesg-warn
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
    - fi-skl-6600u:       [PASS][20] -> [DMESG-WARN][21] +38 other tests dmesg-warn
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_contexts:
    - fi-ilk-650:         [PASS][22] -> [DMESG-WARN][23] +41 other tests dmesg-warn
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html

  * igt@i915_selftest@live@gt_mocs:
    - fi-glk-j4005:       [PASS][24] -> [DMESG-WARN][25] +42 other tests dmesg-warn
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
    - fi-tgl-1115g4:      [PASS][26] -> [DMESG-WARN][27] +41 other tests dmesg-warn
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@gt_tlb:
    - bat-adlp-9:         [PASS][28] -> [DMESG-WARN][29] +40 other tests dmesg-warn
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html

  * igt@i915_selftest@live@perf:
    - bat-dg2-11:         [PASS][30] -> [DMESG-WARN][31] +39 other tests dmesg-warn
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-11/igt@i915_selftest@live@perf.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-11/igt@i915_selftest@live@perf.html
    - fi-kbl-x1275:       [PASS][32] -> [DMESG-WARN][33] +41 other tests dmesg-warn
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-kbl-x1275/igt@i915_selftest@live@perf.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-kbl-x1275/igt@i915_selftest@live@perf.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][34] -> [DMESG-WARN][35] +40 other tests dmesg-warn
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-apl-guc/igt@i915_selftest@live@reset.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-apl-guc/igt@i915_selftest@live@reset.html
    - bat-dg1-5:          [PASS][36] -> [DMESG-WARN][37] +42 other tests dmesg-warn
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg1-5/igt@i915_selftest@live@reset.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg1-5/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [PASS][38] -> [DMESG-WARN][39] +41 other tests dmesg-warn
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7567u:       [PASS][40] -> [DMESG-WARN][41] +40 other tests dmesg-warn
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
    - fi-cfl-8700k:       [PASS][42] -> [DMESG-WARN][43] +42 other tests dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@uncore:
    - bat-dg1-7:          [PASS][44] -> [DMESG-WARN][45] +42 other tests dmesg-warn
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg1-7/igt@i915_selftest@live@uncore.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg1-7/igt@i915_selftest@live@uncore.html

  * igt@i915_selftest@live@vma:
    - fi-skl-guc:         [PASS][46] -> [DMESG-WARN][47] +42 other tests dmesg-warn
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-skl-guc/igt@i915_selftest@live@vma.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-skl-guc/igt@i915_selftest@live@vma.html

  * igt@i915_selftest@live@workarounds:
    - bat-rpls-1:         [PASS][48] -> [DMESG-WARN][49] +40 other tests dmesg-warn
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-rpls-1/igt@i915_selftest@live@workarounds.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-rpls-1/igt@i915_selftest@live@workarounds.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@load:
    - {bat-dg2-13}:       [PASS][50] -> [DMESG-WARN][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-13/igt@i915_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-13/igt@i915_module_load@load.html
    - {bat-dg2-14}:       [PASS][52] -> [DMESG-WARN][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-14/igt@i915_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-14/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_126962v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][54] ([i915#9318])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-8:         NOTRUN -> [SKIP][55] ([i915#4613]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][56] ([i915#4083])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][57] ([i915#4077]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][58] ([i915#4079]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@i915_module_load@load:
    - bat-adlp-6:         [PASS][59] -> [DMESG-WARN][60] ([i915#1982])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-adlp-6/igt@i915_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-adlp-6/igt@i915_module_load@load.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [PASS][61] -> [DMESG-WARN][62] ([i915#1982]) +1 other test dmesg-warn
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-apl-guc/igt@i915_module_load@reload.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-apl-guc/igt@i915_module_load@reload.html
    - bat-dg2-11:         [PASS][63] -> [DMESG-WARN][64] ([i915#1982])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-11/igt@i915_module_load@reload.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-11/igt@i915_module_load@reload.html
    - fi-cfl-8109u:       [PASS][65] -> [DMESG-WARN][66] ([i915#1982])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-cfl-8109u/igt@i915_module_load@reload.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-cfl-8109u/igt@i915_module_load@reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-8:         NOTRUN -> [SKIP][67] ([i915#6621])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-dg2-9:          [PASS][68] -> [DMESG-WARN][69] ([i915#7699]) +1 other test dmesg-warn
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-9/igt@i915_selftest@live@gt_heartbeat.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-9/igt@i915_selftest@live@gt_heartbeat.html
    - bat-rpls-1:         [PASS][70] -> [DMESG-WARN][71] ([i915#7699]) +1 other test dmesg-warn
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-rpls-1/igt@i915_selftest@live@gt_heartbeat.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-rpls-1/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - bat-adls-5:         [PASS][72] -> [DMESG-WARN][73] ([i915#5591])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-adls-5/igt@i915_selftest@live@hangcheck.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-adls-5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-9:         [PASS][74] -> [DMESG-WARN][75] ([i915#7699]) +1 other test dmesg-warn
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-adlp-9/igt@i915_selftest@live@migrate.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-adlp-9/igt@i915_selftest@live@migrate.html
    - bat-dg2-11:         [PASS][76] -> [DMESG-WARN][77] ([i915#7699]) +1 other test dmesg-warn
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-kbl-7567u:       [PASS][78] -> [DMESG-WARN][79] ([i915#1982]) +1 other test dmesg-warn
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-kbl-7567u/igt@i915_suspend@basic-s2idle-without-i915.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-kbl-7567u/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-skl-6600u:       [PASS][80] -> [DMESG-WARN][81] ([i915#1982]) +3 other tests dmesg-warn
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][82] ([i915#6645])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][83] ([i915#5190])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][84] ([i915#4212]) +8 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][85] ([i915#4213]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][86] ([i915#3555] / [i915#3840] / [i915#4098] / [i915#9159])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-8:         NOTRUN -> [SKIP][87] ([fdo#109285])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][88] ([i915#5274])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-pnv-d510:        NOTRUN -> [SKIP][89] ([fdo#109271]) +20 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-pnv-d510/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [PASS][90] -> [ABORT][91] ([i915#8668])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-8:         NOTRUN -> [SKIP][92] ([i915#3555] / [i915#8809])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-8:         NOTRUN -> [SKIP][93] ([i915#3708] / [i915#4077]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][94] ([i915#3708]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-mtlp-6:         [SKIP][95] ([i915#9741]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@core_hotunplug@unbind-rebind.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_ctx_create@basic-files:
    - bat-mtlp-6:         [SKIP][97] ([i915#2575]) -> [PASS][98] +68 other tests pass
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@gem_ctx_create@basic-files.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@gem_ctx_create@basic-files.html

  * igt@i915_pm_rpm@module-reload:
    - bat-mtlp-6:         [SKIP][99] ([i915#9641]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_pm_rpm@module-reload.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gem_contexts:
    - bat-mtlp-6:         [DMESG-FAIL][101] ([i915#9579]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_selftest@live@gem_contexts.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-mtlp-6:         [DMESG-FAIL][103] ([i915#7699]) -> [PASS][104] +1 other test pass
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_selftest@live@gt_heartbeat.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@slpc:
    - bat-mtlp-6:         [DMESG-FAIL][105] ([i915#9748]) -> [PASS][106] +35 other tests pass
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_selftest@live@slpc.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-mtlp-6:         [DMESG-WARN][107] ([i915#9748]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_suspend@basic-s2idle-without-i915.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-guc:         [FAIL][109] ([IGT#3]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html

  * {igt@kms_pm_rpm@basic-pci-d3-state}:
    - bat-mtlp-6:         [SKIP][111] ([i915#9710]) -> [PASS][112] +1 other test pass
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_pm_rpm@basic-pci-d3-state.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_pm_rpm@basic-pci-d3-state.html

  
#### Warnings ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-6:         [SKIP][113] ([i915#2575]) -> [SKIP][114] ([i915#9318])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-6:         [SKIP][115] ([i915#9643]) -> [SKIP][116] ([i915#4613]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-6:         [SKIP][117] ([i915#2575]) -> [SKIP][118] ([i915#4083])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@gem_mmap@basic.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@gem_mmap@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-mtlp-6:         [SKIP][119] ([i915#2575]) -> [SKIP][120] ([i915#4077]) +2 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@gem_tiled_blits@basic.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-mtlp-6:         [SKIP][121] ([i915#2575]) -> [SKIP][122] ([i915#4079]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@gem_tiled_pread_basic.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-6:         [SKIP][123] ([i915#2575]) -> [SKIP][124] ([i915#6621])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-mtlp-6:         [SKIP][125] ([i915#2575]) -> [SKIP][126] ([i915#4212]) +8 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-6:         [SKIP][127] ([i915#2575]) -> [SKIP][128] ([i915#5190])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-mtlp-6:         [SKIP][129] ([i915#2575]) -> [SKIP][130] ([i915#1845]) +12 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-mtlp-6:         [SKIP][131] ([i915#2575]) -> [SKIP][132] ([i915#3637]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-6:         [SKIP][133] ([i915#2575]) -> [SKIP][134] ([fdo#109285])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-6:         [SKIP][135] ([i915#2575]) -> [SKIP][136] ([i915#5274])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-mtlp-6:         [SKIP][137] ([i915#2575]) -> [SKIP][138] ([i915#4342] / [i915#5354])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-mtlp-6:         [SKIP][139] ([i915#2575]) -> [SKIP][140] ([i915#1845] / [i915#4078]) +4 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-6:         [SKIP][141] ([i915#2575]) -> [SKIP][142] ([i915#3555] / [i915#8809])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-mtlp-6:         [SKIP][143] ([i915#2575]) -> [SKIP][144] ([i915#1845] / [i915#3708])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-6:         [SKIP][145] ([i915#2575]) -> [SKIP][146] ([i915#3708] / [i915#4077]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-mtlp-6:         [SKIP][147] ([i915#2575]) -> [SKIP][148] ([i915#3708]) +2 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13945/bat-mtlp-6/igt@prime_vgem@basic-write.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/bat-mtlp-6/igt@prime_vgem@basic-write.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9579]: https://gitlab.freedesktop.org/drm/intel/issues/9579
  [i915#9641]: https://gitlab.freedesktop.org/drm/intel/issues/9641
  [i915#9643]: https://gitlab.freedesktop.org/drm/intel/issues/9643
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9710]: https://gitlab.freedesktop.org/drm/intel/issues/9710
  [i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736
  [i915#9741]: https://gitlab.freedesktop.org/drm/intel/issues/9741
  [i915#9748]: https://gitlab.freedesktop.org/drm/intel/issues/9748


Build changes
-------------

  * Linux: CI_DRM_13945 -> Patchwork_126962v2

  CI-20190529: 20190529
  CI_DRM_13945: bd217b949594a93bbb922958e0c26cfe6884cc7b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7609: 72a759595100b8d167ca78cd2d62e9acd97e36bf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_126962v2: bd217b949594a93bbb922958e0c26cfe6884cc7b @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

6b0ecf9113ce drm/i915: Disable SAGV on bw init, to force QGV point recalculation
3e1ef29a194b drm/i915: Extract code required to calculate max qgv/psf gv point
218b2b1baa7c drm/i915: Add meaningful traces for QGV point info error handling

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v2/index.html

[-- Attachment #2: Type: text/html, Size: 37524 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev3)
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (8 preceding siblings ...)
  2023-11-29 14:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-12-02  1:26 ` Patchwork
  2023-12-02  1:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-12-02  1:26 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: QGV/SAGV related fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/126962/
State : warning

== Summary ==

Error: dim checkpatch failed
f1e1dd9cee4b drm/i915: Add meaningful traces for QGV point info error handling
e838d5faf383 drm/i915: Extract code required to calculate max qgv/psf gv point
7bb73fc2d67a drm/i915: Disable SAGV on bw init, to force QGV point recalculation
-:9: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#9: 
(i.e all points allowed), however in reality we might get them all restricted,

-:54: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#54: FILE: drivers/gpu/drm/i915/display/intel_bw.c:882:
+	drm_dbg_kms(&i915->drm, "Forcing SAGV disable: leaving QGV point %d, PSF GV %d\n",
+				max_bw_qgv_point, max_bw_psf_gv_point);

total: 0 errors, 1 warnings, 1 checks, 49 lines checked



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for QGV/SAGV related fixes (rev3)
  2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
                   ` (9 preceding siblings ...)
  2023-12-02  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev3) Patchwork
@ 2023-12-02  1:47 ` Patchwork
  10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2023-12-02  1:47 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 23962 bytes --]

== Series Details ==

Series: QGV/SAGV related fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/126962/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13962 -> Patchwork_126962v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_126962v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_126962v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/index.html

Participating hosts (33 -> 37)
------------------------------

  Additional (5): bat-kbl-2 fi-bsw-n3050 bat-dg1-5 fi-tgl-1115g4 bat-mtlp-8 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_126962v3:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-blb-e6850:       [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_module_load@load:
    - bat-adlp-6:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-adlp-6/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-adlp-6/igt@i915_module_load@load.html
    - fi-pnv-d510:        [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-pnv-d510/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-pnv-d510/igt@i915_module_load@load.html
    - fi-elk-e7500:       [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-elk-e7500/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-elk-e7500/igt@i915_module_load@load.html
    - bat-adlp-11:        [PASS][9] -> [DMESG-WARN][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-adlp-11/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-adlp-11/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@module-reload:
    - bat-kbl-2:          NOTRUN -> [DMESG-WARN][11] +42 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-kbl-2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@client:
    - fi-kbl-guc:         [PASS][12] -> [DMESG-WARN][13] +42 other tests dmesg-warn
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-kbl-guc/igt@i915_selftest@live@client.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-kbl-guc/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@gem:
    - fi-rkl-11600:       [PASS][14] -> [DMESG-WARN][15] +40 other tests dmesg-warn
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-rkl-11600/igt@i915_selftest@live@gem.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-rkl-11600/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cfl-guc:         [PASS][16] -> [DMESG-WARN][17] +42 other tests dmesg-warn
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_contexts:
    - fi-ilk-650:         [PASS][18] -> [DMESG-WARN][19] +41 other tests dmesg-warn
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html

  * igt@i915_selftest@live@gt_mocs:
    - fi-glk-j4005:       [PASS][20] -> [DMESG-WARN][21] +40 other tests dmesg-warn
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-glk-j4005/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
    - fi-tgl-1115g4:      NOTRUN -> [DMESG-WARN][22] +41 other tests dmesg-warn
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@gt_tlb:
    - bat-adlp-9:         [PASS][23] -> [DMESG-WARN][24] +40 other tests dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-adlp-9/igt@i915_selftest@live@gt_tlb.html

  * igt@i915_selftest@live@perf:
    - bat-dg2-11:         [PASS][25] -> [DMESG-WARN][26] +40 other tests dmesg-warn
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-dg2-11/igt@i915_selftest@live@perf.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg2-11/igt@i915_selftest@live@perf.html
    - fi-kbl-x1275:       [PASS][27] -> [DMESG-WARN][28] +41 other tests dmesg-warn
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-kbl-x1275/igt@i915_selftest@live@perf.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-kbl-x1275/igt@i915_selftest@live@perf.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][29] -> [DMESG-WARN][30] +41 other tests dmesg-warn
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-apl-guc/igt@i915_selftest@live@reset.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-apl-guc/igt@i915_selftest@live@reset.html
    - bat-dg1-5:          NOTRUN -> [DMESG-WARN][31] +42 other tests dmesg-warn
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [PASS][32] -> [DMESG-WARN][33] +42 other tests dmesg-warn
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7567u:       [PASS][34] -> [DMESG-WARN][35] +42 other tests dmesg-warn
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
    - fi-cfl-8700k:       [PASS][36] -> [DMESG-WARN][37] +42 other tests dmesg-warn
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-cfl-8700k/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@uncore:
    - bat-dg1-7:          [PASS][38] -> [DMESG-WARN][39] +42 other tests dmesg-warn
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-dg1-7/igt@i915_selftest@live@uncore.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-7/igt@i915_selftest@live@uncore.html

  * igt@i915_selftest@live@vma:
    - fi-skl-guc:         [PASS][40] -> [DMESG-WARN][41] +42 other tests dmesg-warn
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-skl-guc/igt@i915_selftest@live@vma.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-skl-guc/igt@i915_selftest@live@vma.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       NOTRUN -> [DMESG-WARN][42] +1 other test dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
    - fi-skl-6600u:       [PASS][43] -> [DMESG-WARN][44] +39 other tests dmesg-warn
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-skl-6600u/igt@i915_suspend@basic-s3-without-i915.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@load:
    - {bat-dg2-13}:       [PASS][45] -> [DMESG-WARN][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-dg2-13/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg2-13/igt@i915_module_load@load.html
    - {bat-dg2-14}:       [PASS][47] -> [DMESG-WARN][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-dg2-14/igt@i915_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg2-14/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_126962v3 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - bat-jsl-1:          [PASS][49] -> [FAIL][50] ([i915#8293])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-jsl-1/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-jsl-1/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][51] ([i915#9318])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][52] ([i915#9318])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@info:
    - bat-kbl-2:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#1849])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-kbl-2/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][54] ([i915#2190])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-kbl-2:          NOTRUN -> [SKIP][55] ([fdo#109271]) +20 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][56] ([i915#4613]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][57] ([fdo#109271]) +14 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-8:         NOTRUN -> [SKIP][58] ([i915#4613]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][59] ([i915#4083])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@gem_mmap@basic.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][60] ([i915#4083])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][61] ([i915#4077]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][62] ([i915#4079]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][63] ([i915#4077]) +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][64] ([i915#4079]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@reload:
    - fi-skl-6600u:       [PASS][65] -> [DMESG-WARN][66] ([i915#1982]) +2 other tests dmesg-warn
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-skl-6600u/igt@i915_module_load@reload.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-skl-6600u/igt@i915_module_load@reload.html
    - fi-apl-guc:         [PASS][67] -> [DMESG-WARN][68] ([i915#1982])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-apl-guc/igt@i915_module_load@reload.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-apl-guc/igt@i915_module_load@reload.html
    - fi-glk-j4005:       [PASS][69] -> [DMESG-WARN][70] ([i915#1982]) +1 other test dmesg-warn
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/fi-glk-j4005/igt@i915_module_load@reload.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-glk-j4005/igt@i915_module_load@reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-5:          NOTRUN -> [SKIP][71] ([i915#6621])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@i915_pm_rps@basic-api.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][72] ([i915#6621])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-9:         [PASS][73] -> [DMESG-WARN][74] ([i915#7699]) +1 other test dmesg-warn
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-adlp-9/igt@i915_selftest@live@migrate.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-adlp-9/igt@i915_selftest@live@migrate.html
    - bat-dg2-11:         [PASS][75] -> [DMESG-WARN][76] ([i915#7699]) +1 other test dmesg-warn
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13962/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-tgl-1115g4:      NOTRUN -> [INCOMPLETE][77] ([i915#7443])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][78] ([i915#6645])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][79] ([i915#5190])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][80] ([i915#4212]) +7 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][81] ([i915#4212]) +8 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg1-5:          NOTRUN -> [SKIP][82] ([i915#4215])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][83] ([i915#4103]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][84] ([i915#4213]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg1-5:          NOTRUN -> [SKIP][85] ([i915#4103] / [i915#4213]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][86] ([i915#3555] / [i915#3840])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@kms_dsc@dsc-basic.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][87] ([i915#3555] / [i915#3840] / [i915#4098] / [i915#9159])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
    - bat-dg1-5:          NOTRUN -> [SKIP][88] ([i915#3555] / [i915#3840])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][89] ([fdo#109285])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][90] ([fdo#109285])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg1-5:          NOTRUN -> [SKIP][91] ([fdo#109285])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][92] ([i915#5274])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-dg1-5:          NOTRUN -> [SKIP][93] ([i915#433])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html
    - fi-bsw-n3050:       NOTRUN -> [FAIL][94] ([IGT#152])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-bsw-n3050/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
    - bat-kbl-2:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#1845]) +14 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-kbl-2/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg1-5:          NOTRUN -> [SKIP][96] ([i915#3555])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][97] ([i915#3555] / [i915#8809])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][98] ([i915#3555])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-8:         NOTRUN -> [SKIP][99] ([i915#3708] / [i915#4077]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][100] ([i915#3708]) +2 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
    - bat-dg1-5:          NOTRUN -> [SKIP][101] ([i915#3708]) +3 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg1-5:          NOTRUN -> [SKIP][102] ([i915#3708] / [i915#4077]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/bat-dg1-5/igt@prime_vgem@basic-gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#152]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/152
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732


Build changes
-------------

  * Linux: CI_DRM_13962 -> Patchwork_126962v3

  CI-20190529: 20190529
  CI_DRM_13962: 6915556fe478277b884730a627ad8ae1f4ab9efa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7614: c7298ec108dc1c861c9a2593e973648ad9b420b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_126962v3: 6915556fe478277b884730a627ad8ae1f4ab9efa @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

449e0f31bbae drm/i915: Disable SAGV on bw init, to force QGV point recalculation
972d8b501899 drm/i915: Extract code required to calculate max qgv/psf gv point
c56cb39ff901 drm/i915: Add meaningful traces for QGV point info error handling

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v3/index.html

[-- Attachment #2: Type: text/html, Size: 28034 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH 0/3] QGV/SAGV related fixes
@ 2024-01-17 15:57 Stanislav Lisovskiy
  2024-01-17 15:57 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-01-17 15:57 UTC (permalink / raw)
  To: intel-gfx

We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.

Stanislav Lisovskiy (3):
  drm/i915: Add meaningful traces for QGV point info error handling
  drm/i915: Extract code required to calculate max qgv/psf gv point
  drm/i915: Disable SAGV on bw init, to force QGV point recalculation

 drivers/gpu/drm/i915/display/intel_bw.c | 109 +++++++++++++++++-------
 drivers/gpu/drm/i915/display/intel_bw.h |   2 +
 drivers/gpu/drm/i915/soc/intel_dram.c   |   2 +
 3 files changed, 84 insertions(+), 29 deletions(-)

-- 
2.37.3


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-01-17 15:57 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
@ 2024-01-17 15:57 ` Stanislav Lisovskiy
  2024-01-18  8:24   ` Ville Syrjälä
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-01-17 15:57 UTC (permalink / raw)
  To: intel-gfx

We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we don't do that when we disable SAGV, which might be
actually causing some issues in that case.

v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
      (Ville Syrjälä)
    - Don't restrict psf gv points for SAGV disable case
      (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 81 ++++++++++++++++---------
 1 file changed, 53 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 77886cc21211..7baa1c13eccd 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
+static unsigned int adl_psf_bw(struct drm_i915_private *i915,
 			       int psf_gv_point)
 {
 	const struct intel_bw_info *bi =
-			&dev_priv->display.bw.max[0];
+			&i915->display.bw.max[0];
 
 	return bi->psf_bw[psf_gv_point];
 }
 
+static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
+			       int qgv_point, int num_active_planes)
+{
+	unsigned int idx;
+
+	if (DISPLAY_VER(i915) > 11)
+		idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
+	else
+		idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
+
+	if (idx >= ARRAY_SIZE(i915->display.bw.max))
+		return 0;
+
+	return i915->display.bw.max[idx].deratedbw[qgv_point];
+}
+
 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_DISPLAY(dev_priv))
@@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
+					 int num_active_planes)
+{
+	unsigned int max_bw_point = 0;
+	unsigned int max_bw = 0;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	int i;
+
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
+
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
+
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+	}
+
+	return max_bw_point;
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 			       const struct intel_bw_state *old_bw_state,
 			       struct intel_bw_state *new_bw_state)
 {
-	unsigned int max_bw_point = 0;
-	unsigned int max_bw = 0;
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
 	u16 psf_points = 0;
@@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 		return ret;
 
 	for (i = 0; i < num_qgv_points; i++) {
-		unsigned int idx;
 		unsigned int max_data_rate;
 
-		if (DISPLAY_VER(i915) >= 12)
-			idx = tgl_max_bw_index(i915, num_active_planes, i);
-		else
-			idx = icl_max_bw_index(i915, num_active_planes, i);
-
-		if (idx >= ARRAY_SIZE(i915->display.bw.max))
-			continue;
-
-		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
 
-		/*
-		 * We need to know which qgv point gives us
-		 * maximum bandwidth in order to disable SAGV
-		 * if we find that we exceed SAGV block time
-		 * with watermarks. By that moment we already
-		 * have those, as it is calculated earlier in
-		 * intel_atomic_check,
-		 */
-		if (max_data_rate > max_bw) {
-			max_bw_point = i;
-			max_bw = max_data_rate;
-		}
 		if (max_data_rate >= data_rate)
 			qgv_points |= BIT(i);
 
@@ -965,9 +988,11 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
-		qgv_points = BIT(max_bw_point);
+		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
+
+		qgv_points = BIT(max_bw_qgv_point);
 		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
-			    max_bw_point);
+			    max_bw_qgv_point);
 	}
 
 	/*
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-01-17 15:57 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
@ 2024-01-18  8:24   ` Ville Syrjälä
  0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2024-01-18  8:24 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Wed, Jan 17, 2024 at 05:57:17PM +0200, Stanislav Lisovskiy wrote:
> We need that in order to force disable SAGV in next patch.
> Also it is beneficial to separate that code, as in majority cases,
> when SAGV is enabled, we don't even need those calculations.
> Also we probably need to determine max PSF GV point as well, however
> currently we don't do that when we disable SAGV, which might be
> actually causing some issues in that case.
> 
> v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
>       (Ville Syrjälä)
>     - Don't restrict psf gv points for SAGV disable case
>       (Ville Syrjälä)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 81 ++++++++++++++++---------
>  1 file changed, 53 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 77886cc21211..7baa1c13eccd 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> -static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
> +static unsigned int adl_psf_bw(struct drm_i915_private *i915,
>  			       int psf_gv_point)
>  {
>  	const struct intel_bw_info *bi =
> -			&dev_priv->display.bw.max[0];
> +			&i915->display.bw.max[0];

Unrelated change.

>  
>  	return bi->psf_bw[psf_gv_point];
>  }
>  
> +static unsigned int adl_qgv_bw(struct drm_i915_private *i915,

s/adl/icl/, or s/adl/intel/ perhaps.

> +			       int qgv_point, int num_active_planes)

Please keep the parameters in the same order as elsewhere.
It's hard enough trying to juggle multiple integer parameters
without intentionally confusing matters by swapping the order
randomly.

> +{
> +	unsigned int idx;
> +
> +	if (DISPLAY_VER(i915) > 11)

 >= 12

> +		idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
> +	else
> +		idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
> +
> +	if (idx >= ARRAY_SIZE(i915->display.bw.max))
> +		return 0;
> +
> +	return i915->display.bw.max[idx].deratedbw[qgv_point];
> +}
> +
>  void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  {
>  	if (!HAS_DISPLAY(dev_priv))
> @@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
>  	return to_intel_bw_state(bw_state);
>  }
>  
> +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> +					 int num_active_planes)
> +{
> +	unsigned int max_bw_point = 0;
> +	unsigned int max_bw = 0;
> +	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> +	int i;
> +
> +	for (i = 0; i < num_qgv_points; i++) {
> +		unsigned int max_data_rate;
> +
> +		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
> +
> +		/*
> +		 * We need to know which qgv point gives us
> +		 * maximum bandwidth in order to disable SAGV
> +		 * if we find that we exceed SAGV block time
> +		 * with watermarks. By that moment we already
> +		 * have those, as it is calculated earlier in
> +		 * intel_atomic_check,
> +		 */
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +	}
> +
> +	return max_bw_point;
> +}
> +
>  static int mtl_find_qgv_points(struct drm_i915_private *i915,
>  			       unsigned int data_rate,
>  			       unsigned int num_active_planes,
> @@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  			       const struct intel_bw_state *old_bw_state,
>  			       struct intel_bw_state *new_bw_state)
>  {
> -	unsigned int max_bw_point = 0;
> -	unsigned int max_bw = 0;
>  	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
>  	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
>  	u16 psf_points = 0;
> @@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  		return ret;
>  
>  	for (i = 0; i < num_qgv_points; i++) {
> -		unsigned int idx;
>  		unsigned int max_data_rate;
>  
> -		if (DISPLAY_VER(i915) >= 12)
> -			idx = tgl_max_bw_index(i915, num_active_planes, i);
> -		else
> -			idx = icl_max_bw_index(i915, num_active_planes, i);
> -
> -		if (idx >= ARRAY_SIZE(i915->display.bw.max))
> -			continue;
> -
> -		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> +		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
>  
> -		/*
> -		 * We need to know which qgv point gives us
> -		 * maximum bandwidth in order to disable SAGV
> -		 * if we find that we exceed SAGV block time
> -		 * with watermarks. By that moment we already
> -		 * have those, as it is calculated earlier in
> -		 * intel_atomic_check,
> -		 */
> -		if (max_data_rate > max_bw) {
> -			max_bw_point = i;
> -			max_bw = max_data_rate;
> -		}
>  		if (max_data_rate >= data_rate)
>  			qgv_points |= BIT(i);
>  
> @@ -965,9 +988,11 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>  	 * cause.
>  	 */
>  	if (!intel_can_enable_sagv(i915, new_bw_state)) {
> -		qgv_points = BIT(max_bw_point);
> +		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> +
> +		qgv_points = BIT(max_bw_qgv_point);
>  		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> -			    max_bw_point);
> +			    max_bw_qgv_point);
>  	}
>  
>  	/*
> -- 
> 2.37.3

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH 0/3] QGV/SAGV related fixes
@ 2024-02-19  9:18 Stanislav Lisovskiy
  2024-02-19  9:18 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-19  9:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, ville.syrjala

We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.

Stanislav Lisovskiy (3):
  drm/i915: Add meaningful traces for QGV point info error handling
  drm/i915: Extract code required to calculate max qgv/psf gv point
  drm/i915: Disable SAGV on bw init, to force QGV point recalculation

 drivers/gpu/drm/i915/display/intel_bw.c | 142 +++++++++++++++++++-----
 drivers/gpu/drm/i915/soc/intel_dram.c   |   2 +
 2 files changed, 114 insertions(+), 30 deletions(-)

-- 
2.37.3


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-02-19  9:18 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
@ 2024-02-19  9:18 ` Stanislav Lisovskiy
  0 siblings, 0 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-19  9:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, ville.syrjala

We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we don't do that when we disable SAGV, which might be
actually causing some issues in that case.

v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
      (Ville Syrjälä)
    - Don't restrict psf gv points for SAGV disable case
      (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 81 ++++++++++++++++---------
 1 file changed, 53 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 77886cc21211..7baa1c13eccd 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
+static unsigned int adl_psf_bw(struct drm_i915_private *i915,
 			       int psf_gv_point)
 {
 	const struct intel_bw_info *bi =
-			&dev_priv->display.bw.max[0];
+			&i915->display.bw.max[0];
 
 	return bi->psf_bw[psf_gv_point];
 }
 
+static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
+			       int qgv_point, int num_active_planes)
+{
+	unsigned int idx;
+
+	if (DISPLAY_VER(i915) > 11)
+		idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
+	else
+		idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
+
+	if (idx >= ARRAY_SIZE(i915->display.bw.max))
+		return 0;
+
+	return i915->display.bw.max[idx].deratedbw[qgv_point];
+}
+
 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_DISPLAY(dev_priv))
@@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
+					 int num_active_planes)
+{
+	unsigned int max_bw_point = 0;
+	unsigned int max_bw = 0;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	int i;
+
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
+
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
+
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+	}
+
+	return max_bw_point;
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 			       const struct intel_bw_state *old_bw_state,
 			       struct intel_bw_state *new_bw_state)
 {
-	unsigned int max_bw_point = 0;
-	unsigned int max_bw = 0;
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
 	u16 psf_points = 0;
@@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 		return ret;
 
 	for (i = 0; i < num_qgv_points; i++) {
-		unsigned int idx;
 		unsigned int max_data_rate;
 
-		if (DISPLAY_VER(i915) >= 12)
-			idx = tgl_max_bw_index(i915, num_active_planes, i);
-		else
-			idx = icl_max_bw_index(i915, num_active_planes, i);
-
-		if (idx >= ARRAY_SIZE(i915->display.bw.max))
-			continue;
-
-		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
 
-		/*
-		 * We need to know which qgv point gives us
-		 * maximum bandwidth in order to disable SAGV
-		 * if we find that we exceed SAGV block time
-		 * with watermarks. By that moment we already
-		 * have those, as it is calculated earlier in
-		 * intel_atomic_check,
-		 */
-		if (max_data_rate > max_bw) {
-			max_bw_point = i;
-			max_bw = max_data_rate;
-		}
 		if (max_data_rate >= data_rate)
 			qgv_points |= BIT(i);
 
@@ -965,9 +988,11 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
-		qgv_points = BIT(max_bw_point);
+		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
+
+		qgv_points = BIT(max_bw_qgv_point);
 		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
-			    max_bw_point);
+			    max_bw_qgv_point);
 	}
 
 	/*
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH 0/3] QGV/SAGV related fixes
@ 2024-02-20  9:31 Stanislav Lisovskiy
  2024-02-20  9:31 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-20  9:31 UTC (permalink / raw)
  To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, ville.syrjala

We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.

Stanislav Lisovskiy (3):
  drm/i915: Add meaningful traces for QGV point info error handling
  drm/i915: Extract code required to calculate max qgv/psf gv point
  drm/i915: Disable SAGV on bw init, to force QGV point recalculation

 drivers/gpu/drm/i915/display/intel_bw.c      | 152 +++++++++++++++----
 drivers/gpu/drm/i915/display/skl_watermark.c |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.h |   1 +
 drivers/gpu/drm/i915/soc/intel_dram.c        |   2 +
 4 files changed, 126 insertions(+), 31 deletions(-)

-- 
2.37.3


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-02-20  9:31 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
@ 2024-02-20  9:31 ` Stanislav Lisovskiy
  2024-03-20 22:07   ` Govindapillai, Vinod
  0 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-20  9:31 UTC (permalink / raw)
  To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, ville.syrjala

We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we don't do that when we disable SAGV, which might be
actually causing some issues in that case.

v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
      (Ville Syrjälä)
    - Don't restrict psf gv points for SAGV disable case
      (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 81 ++++++++++++++++---------
 1 file changed, 53 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 77886cc21211..7baa1c13eccd 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
+static unsigned int adl_psf_bw(struct drm_i915_private *i915,
 			       int psf_gv_point)
 {
 	const struct intel_bw_info *bi =
-			&dev_priv->display.bw.max[0];
+			&i915->display.bw.max[0];
 
 	return bi->psf_bw[psf_gv_point];
 }
 
+static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
+			       int qgv_point, int num_active_planes)
+{
+	unsigned int idx;
+
+	if (DISPLAY_VER(i915) > 11)
+		idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
+	else
+		idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
+
+	if (idx >= ARRAY_SIZE(i915->display.bw.max))
+		return 0;
+
+	return i915->display.bw.max[idx].deratedbw[qgv_point];
+}
+
 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_DISPLAY(dev_priv))
@@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
+					 int num_active_planes)
+{
+	unsigned int max_bw_point = 0;
+	unsigned int max_bw = 0;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	int i;
+
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
+
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
+
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+	}
+
+	return max_bw_point;
+}
+
 static int mtl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 			       const struct intel_bw_state *old_bw_state,
 			       struct intel_bw_state *new_bw_state)
 {
-	unsigned int max_bw_point = 0;
-	unsigned int max_bw = 0;
 	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
 	u16 psf_points = 0;
@@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 		return ret;
 
 	for (i = 0; i < num_qgv_points; i++) {
-		unsigned int idx;
 		unsigned int max_data_rate;
 
-		if (DISPLAY_VER(i915) >= 12)
-			idx = tgl_max_bw_index(i915, num_active_planes, i);
-		else
-			idx = icl_max_bw_index(i915, num_active_planes, i);
-
-		if (idx >= ARRAY_SIZE(i915->display.bw.max))
-			continue;
-
-		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+		max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
 
-		/*
-		 * We need to know which qgv point gives us
-		 * maximum bandwidth in order to disable SAGV
-		 * if we find that we exceed SAGV block time
-		 * with watermarks. By that moment we already
-		 * have those, as it is calculated earlier in
-		 * intel_atomic_check,
-		 */
-		if (max_data_rate > max_bw) {
-			max_bw_point = i;
-			max_bw = max_data_rate;
-		}
 		if (max_data_rate >= data_rate)
 			qgv_points |= BIT(i);
 
@@ -965,9 +988,11 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
-		qgv_points = BIT(max_bw_point);
+		unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
+
+		qgv_points = BIT(max_bw_qgv_point);
 		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
-			    max_bw_point);
+			    max_bw_qgv_point);
 	}
 
 	/*
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
  2024-02-20  9:31 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
@ 2024-03-20 22:07   ` Govindapillai, Vinod
  0 siblings, 0 replies; 24+ messages in thread
From: Govindapillai, Vinod @ 2024-03-20 22:07 UTC (permalink / raw)
  To: Lisovskiy, Stanislav, intel-gfx@lists.freedesktop.org
  Cc: Saarinen, Jani, ville.syrjala@linux.intel.com

Hi Stan.


On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> We need that in order to force disable SAGV in next patch.
> Also it is beneficial to separate that code, as in majority cases,
> when SAGV is enabled, we don't even need those calculations.
> Also we probably need to determine max PSF GV point as well, however
> currently we don't do that when we disable SAGV, which might be
> actually causing some issues in that case.
> 
> v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
>       (Ville Syrjälä)
>     - Don't restrict psf gv points for SAGV disable case
>       (Ville Syrjälä)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 81 ++++++++++++++++---------
>  1 file changed, 53 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 77886cc21211..7baa1c13eccd 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
>         return 0;
>  }
>  
> -static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
> +static unsigned int adl_psf_bw(struct drm_i915_private *i915,
>                                int psf_gv_point)
>  {
>         const struct intel_bw_info *bi =
> -                       &dev_priv->display.bw.max[0];
> +                       &i915->display.bw.max[0];
>  
>         return bi->psf_bw[psf_gv_point];
>  }
This is probably not related to this patch..

>  
> +static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
> +                              int qgv_point, int num_active_planes)
In the next patch you are chaging the order of these parameters and calling with adl_qgv_bw(i915,
num_active_planes, i). As you are adding this functions in this patch, I think you should fix the
position of parameters in this patch itself and next patch call this normally

Also about the naming of this function, should this be icl_* as this is called from icl_* functions?
> +{
> +       unsigned int idx;
> +
> +       if (DISPLAY_VER(i915) > 11)
This is just fine.. but just for the sake of easy readability, wonder DISPLAY_VER(i915) >= 12 is
better as TGL is display version 12.

BR
vinod

> +               idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
> +       else
> +               idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
> +
> +       if (idx >= ARRAY_SIZE(i915->display.bw.max))
> +               return 0;
> +
> +       return i915->display.bw.max[idx].deratedbw[qgv_point];
> +}
> +
>  void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  {
>         if (!HAS_DISPLAY(dev_priv))
> @@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
>         return to_intel_bw_state(bw_state);
>  }
>  
> +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> +                                        int num_active_planes)
> +{
> +       unsigned int max_bw_point = 0;
> +       unsigned int max_bw = 0;
> +       unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> +       int i;
> +
> +       for (i = 0; i < num_qgv_points; i++) {
> +               unsigned int max_data_rate;
> +
> +               max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
> +
> +               /*
> +                * We need to know which qgv point gives us
> +                * maximum bandwidth in order to disable SAGV
> +                * if we find that we exceed SAGV block time
> +                * with watermarks. By that moment we already
> +                * have those, as it is calculated earlier in
> +                * intel_atomic_check,
> +                */
> +               if (max_data_rate > max_bw) {
> +                       max_bw_point = i;
> +                       max_bw = max_data_rate;
> +               }
> +       }
> +
> +       return max_bw_point;
> +}
> +
>  static int mtl_find_qgv_points(struct drm_i915_private *i915,
>                                unsigned int data_rate,
>                                unsigned int num_active_planes,
> @@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>                                const struct intel_bw_state *old_bw_state,
>                                struct intel_bw_state *new_bw_state)
>  {
> -       unsigned int max_bw_point = 0;
> -       unsigned int max_bw = 0;
>         unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
>         unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
>         u16 psf_points = 0;
> @@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>                 return ret;
>  
>         for (i = 0; i < num_qgv_points; i++) {
> -               unsigned int idx;
>                 unsigned int max_data_rate;
>  
> -               if (DISPLAY_VER(i915) >= 12)
> -                       idx = tgl_max_bw_index(i915, num_active_planes, i);
> -               else
> -                       idx = icl_max_bw_index(i915, num_active_planes, i);
> -
> -               if (idx >= ARRAY_SIZE(i915->display.bw.max))
> -                       continue;
> -
> -               max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> +               max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
>  
> -               /*
> -                * We need to know which qgv point gives us
> -                * maximum bandwidth in order to disable SAGV
> -                * if we find that we exceed SAGV block time
> -                * with watermarks. By that moment we already
> -                * have those, as it is calculated earlier in
> -                * intel_atomic_check,
> -                */
> -               if (max_data_rate > max_bw) {
> -                       max_bw_point = i;
> -                       max_bw = max_data_rate;
> -               }
>                 if (max_data_rate >= data_rate)
>                         qgv_points |= BIT(i);
>  
> @@ -965,9 +988,11 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
>          * cause.
>          */
>         if (!intel_can_enable_sagv(i915, new_bw_state)) {
> -               qgv_points = BIT(max_bw_point);
> +               unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes);
> +
> +               qgv_points = BIT(max_bw_qgv_point);
>                 drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> -                           max_bw_point);
> +                           max_bw_qgv_point);
>         }
>  
>         /*


^ permalink raw reply	[flat|nested] 24+ messages in thread

end of thread, other threads:[~2024-03-20 22:08 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-28  8:37 [Intel-gfx] [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
2023-11-28  8:37 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling Stanislav Lisovskiy
2023-11-28 12:53   ` Gustavo Sousa
2023-11-28  8:37 ` [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
2024-01-12 17:35   ` Ville Syrjälä
2024-01-17 10:12     ` Lisovskiy, Stanislav
2024-01-17 11:12       ` Ville Syrjälä
2024-01-17 11:23         ` Lisovskiy, Stanislav
2023-11-28  8:37 ` [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation Stanislav Lisovskiy
2023-11-29  9:21   ` Stanislav Lisovskiy
2023-12-01 14:35     ` Stanislav Lisovskiy
2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes Patchwork
2023-11-28  9:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-11-28  9:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev2) Patchwork
2023-11-29 14:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-11-29 14:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-12-02  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev3) Patchwork
2023-12-02  1:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-01-17 15:57 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
2024-01-17 15:57 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
2024-01-18  8:24   ` Ville Syrjälä
2024-02-19  9:18 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
2024-02-19  9:18 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
2024-02-20  9:31 [PATCH 0/3] QGV/SAGV related fixes Stanislav Lisovskiy
2024-02-20  9:31 ` [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point Stanislav Lisovskiy
2024-03-20 22:07   ` Govindapillai, Vinod

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