[PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Jani Nikula]

The rawclk initialization is a bit out of place in
intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
bit of refactoring on intel_read_rawclk().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
 drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
 drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d61aa5b7cbdb..64a1cf4ed45c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
 	return intel_atomic_lock_global_state(&cdclk_state->base);
 }
 
+static void intel_rawclk_init(struct drm_i915_private *dev_priv);
+
 int intel_cdclk_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state *cdclk_state;
@@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
 	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
 				     &cdclk_state->base, &intel_cdclk_funcs);
 
+	intel_rawclk_init(dev_priv);
+
 	return 0;
 }
 
@@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
 	}
 }
 
-/**
- * intel_read_rawclk - Determine the current RAWCLK frequency
- * @dev_priv: i915 device
- *
- * Determine the current RAWCLK frequency. RAWCLK is a fixed
- * frequency clock so this needs to done only once.
+/*
+ * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
+ * this needs to done only once.
  */
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
+static void intel_rawclk_init(struct drm_i915_private *dev_priv)
 {
-	u32 freq;
+	u32 freq = 0;
 
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
 		/*
@@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 		freq = vlv_hrawclk(dev_priv);
 	else if (DISPLAY_VER(dev_priv) >= 3)
 		freq = i9xx_hrawclk(dev_priv);
-	else
-		/* no rawclk on other platforms, or no need to know it */
-		return 0;
 
-	return freq;
+	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
 }
 
 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index cfdcdec07a4d..a3f950d5a366 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b);
 int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a0a43ea07f11..48f0957392f9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			 "Disabling ppGTT for VT-d support\n");
 		runtime->ppgtt_type = INTEL_PPGTT_NONE;
 	}
-
-	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
-	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
-
 }
 
 /*
-- 
2.39.2

[PATCH 2/2] drm/i915: move rawclk from runtime to display runtime info

[Jani Nikula]

It's mostly about display, so move it under display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_backlight.c         | 10 +++++-----
 drivers/gpu/drm/i915/display/intel_cdclk.c             |  2 +-
 drivers/gpu/drm/i915/display/intel_display_device.c    |  2 ++
 drivers/gpu/drm/i915/display/intel_display_device.h    |  2 ++
 .../gpu/drm/i915/display/intel_display_power_well.c    |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp_aux.c            |  4 ++--
 drivers/gpu/drm/i915/display/intel_pps.c               |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c         |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c               |  1 -
 drivers/gpu/drm/i915/intel_device_info.h               |  2 --
 10 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 4d4330410b4d..bbc1da3305be 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
 				 pwm_freq_hz);
 }
 
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
 				 pwm_freq_hz * 128);
 }
 
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 	int clock;
 
 	if (IS_PINEVIEW(i915))
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 	else
 		clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 	int clock;
 
 	if (IS_G4X(i915))
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 	else
 		clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 			clock = MHz(25);
 		mul = 16;
 	} else {
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 		mul = 128;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 64a1cf4ed45c..74515f6bb64e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3608,7 +3608,7 @@ static void intel_rawclk_init(struct drm_i915_private *dev_priv)
 	else if (DISPLAY_VER(dev_priv) >= 3)
 		freq = i9xx_hrawclk(dev_priv);
 
-	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+	DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
 	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index b8903bd0e82a..6fefdd90c600 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1142,6 +1142,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
 	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
 	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
 	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+
+	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 66b51de86e38..969ad95a3e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -110,6 +110,8 @@ struct drm_printer;
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
 struct intel_display_runtime_info {
+	u32 rawclk_freq;
+
 	struct {
 		u16 ver;
 		u16 rel;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e4de40228997..ee18b88dabfd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1168,9 +1168,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 	intel_de_write(dev_priv, CBR1_VLV, 0);
 
-	drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
+	drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
 	intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
-		       DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
+		       DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
 					 1000));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b8a53bb174da..cbc817bb0cc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	 * The clock divider is based off the hrawclk, and would like to run at
 	 * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 	 */
-	return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);
+	return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);
 }
 
 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	if (dig_port->aux_ch == AUX_CH_A)
 		freq = i915->display.cdclk.hw.cdclk;
 	else
-		freq = RUNTIME_INFO(i915)->rawclk_freq;
+		freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;
 	return DIV_ROUND_CLOSEST(freq, 2000);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b5d9920f8341..d02d83d625b0 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1468,7 +1468,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 pp_on, pp_off, port_sel = 0;
-	int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
+	int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
 	struct pps_registers regs;
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 7c9be4fd1c8c..df784603beac 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -151,7 +151,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)
 	 *
 	 * Testing on actual hardware has shown there is no /16.
 	 */
-	return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
+	return DISPLAY_RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
 }
 
 static u32 read_clock_frequency(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 48f0957392f9..d159eb1847ce 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -124,7 +124,6 @@ void intel_device_info_print(const struct intel_device_info *info,
 #undef PRINT_FLAG
 
 	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
-	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 #undef INTEL_VGA_DEVICE
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d1a2abc7e513..fb8a08623eb0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -204,8 +204,6 @@ struct intel_runtime_info {
 
 	u16 device_id;
 
-	u32 rawclk_freq;
-
 	struct intel_step_info step;
 
 	unsigned int page_sizes; /* page sizes supported by the HW */
-- 
2.39.2

Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Ville Syrjälä]

On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
> The rawclk initialization is a bit out of place in
> intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> bit of refactoring on intel_read_rawclk().

rawclk is used outside of display.

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
>  drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
>  3 files changed, 11 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d61aa5b7cbdb..64a1cf4ed45c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
>  	return intel_atomic_lock_global_state(&cdclk_state->base);
>  }
>  
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> +
>  int intel_cdclk_init(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state *cdclk_state;
> @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
>  	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
>  				     &cdclk_state->base, &intel_cdclk_funcs);
>  
> +	intel_rawclk_init(dev_priv);
> +
>  	return 0;
>  }
>  
> @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -/**
> - * intel_read_rawclk - Determine the current RAWCLK frequency
> - * @dev_priv: i915 device
> - *
> - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> - * frequency clock so this needs to done only once.
> +/*
> + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
> + * this needs to done only once.
>   */
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
>  {
> -	u32 freq;
> +	u32 freq = 0;
>  
>  	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
>  		/*
> @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  		freq = vlv_hrawclk(dev_priv);
>  	else if (DISPLAY_VER(dev_priv) >= 3)
>  		freq = i9xx_hrawclk(dev_priv);
> -	else
> -		/* no rawclk on other platforms, or no need to know it */
> -		return 0;
>  
> -	return freq;
> +	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> +	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
>  }
>  
>  static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index cfdcdec07a4d..a3f950d5a366 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
>  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
>  bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b);
>  int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a0a43ea07f11..48f0957392f9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			 "Disabling ppGTT for VT-d support\n");
>  		runtime->ppgtt_type = INTEL_PPGTT_NONE;
>  	}
> -
> -	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> -	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> -
>  }
>  
>  /*
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Ville Syrjälä]

On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
> > The rawclk initialization is a bit out of place in
> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> > bit of refactoring on intel_read_rawclk().
> 
> rawclk is used outside of display.

The correct solution would likely be to extract a 
i9xx_fsb_freq(), and use that to populate both rawclk_freq
and fsb_freq (and switch over to fsb_freq in the
non-display code).

> 
> > 
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
> >  drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
> >  drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
> >  3 files changed, 11 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index d61aa5b7cbdb..64a1cf4ed45c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
> >  	return intel_atomic_lock_global_state(&cdclk_state->base);
> >  }
> >  
> > +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> > +
> >  int intel_cdclk_init(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_cdclk_state *cdclk_state;
> > @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
> >  	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
> >  				     &cdclk_state->base, &intel_cdclk_funcs);
> >  
> > +	intel_rawclk_init(dev_priv);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > -/**
> > - * intel_read_rawclk - Determine the current RAWCLK frequency
> > - * @dev_priv: i915 device
> > - *
> > - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> > - * frequency clock so this needs to done only once.
> > +/*
> > + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
> > + * this needs to done only once.
> >   */
> > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> > +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
> >  {
> > -	u32 freq;
> > +	u32 freq = 0;
> >  
> >  	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
> >  		/*
> > @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> >  		freq = vlv_hrawclk(dev_priv);
> >  	else if (DISPLAY_VER(dev_priv) >= 3)
> >  		freq = i9xx_hrawclk(dev_priv);
> > -	else
> > -		/* no rawclk on other platforms, or no need to know it */
> > -		return 0;
> >  
> > -	return freq;
> > +	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> > +	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
> >  }
> >  
> >  static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > index cfdcdec07a4d..a3f950d5a366 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> >  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> >  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> >  bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> >  			       const struct intel_cdclk_config *b);
> >  int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index a0a43ea07f11..48f0957392f9 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> >  			 "Disabling ppGTT for VT-d support\n");
> >  		runtime->ppgtt_type = INTEL_PPGTT_NONE;
> >  	}
> > -
> > -	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> > -	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> > -
> >  }
> >  
> >  /*
> > -- 
> > 2.39.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Jani Nikula]

On Mon, 08 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
>> > The rawclk initialization is a bit out of place in
>> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
>> > bit of refactoring on intel_read_rawclk().
>> 
>> rawclk is used outside of display.
>
> The correct solution would likely be to extract a 
> i9xx_fsb_freq(), and use that to populate both rawclk_freq
> and fsb_freq (and switch over to fsb_freq in the
> non-display code).

I circled back to this, and PNV seems to be the problem case for making
this happen.

pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in
intel_cdclk.c interpret the CLKCFG register slightly differently.

I'm presuming PNV only supports a subset of the values covered by
i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE()
there's a different value for 400 MHz FSB.

So how should desktop PNV interpret the register, I wonder? I can't find
any specs on that anymore.


BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Jani Nikula]

On Mon, 27 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 08 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
>>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
>>> > The rawclk initialization is a bit out of place in
>>> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
>>> > bit of refactoring on intel_read_rawclk().
>>> 
>>> rawclk is used outside of display.
>>
>> The correct solution would likely be to extract a 
>> i9xx_fsb_freq(), and use that to populate both rawclk_freq
>> and fsb_freq (and switch over to fsb_freq in the
>> non-display code).
>
> I circled back to this, and PNV seems to be the problem case for making
> this happen.
>
> pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in
> intel_cdclk.c interpret the CLKCFG register slightly differently.
>
> I'm presuming PNV only supports a subset of the values covered by
> i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE()
> there's a different value for 400 MHz FSB.
>
> So how should desktop PNV interpret the register, I wonder? I can't find
> any specs on that anymore.

My guess would be this:

index b78154c82a71..19ca3ed5212a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3545,7 +3545,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
 	 */
 	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
 
-	if (IS_MOBILE(dev_priv)) {
+	if (IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv)) {
 		switch (clkcfg) {
 		case CLKCFG_FSB_400:
 			return 100000;



-- 
Jani Nikula, Intel

✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init()
URL   : https://patchwork.freedesktop.org/series/132168/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init()

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7985 bytes --]

== Series Details ==

Series: series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init()
URL   : https://patchwork.freedesktop.org/series/132168/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14545 -> Patchwork_132168v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_132168v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_132168v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/index.html

Participating hosts (40 -> 36)
------------------------------

  Additional (1): bat-dg1-7 
  Missing    (5): fi-bsw-n3050 fi-cfl-8109u fi-elk-e7500 fi-kbl-8809g bat-jsl-1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_132168v1:

### IGT changes ###

#### Possible regressions ####

  * igt@prime_self_import@basic-with_two_bos:
    - bat-arls-2:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14545/bat-arls-2/igt@prime_self_import@basic-with_two_bos.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-arls-2/igt@prime_self_import@basic-with_two_bos.html

  
Known issues
------------

  Here are the changes found in Patchwork_132168v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@load:
    - fi-bsw-nick:        [PASS][6] -> [INCOMPLETE][7] ([i915#10311])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14545/fi-bsw-nick/igt@i915_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/fi-bsw-nick/igt@i915_module_load@load.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-7:          NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@active:
    - bat-dg2-9:          [PASS][9] -> [ABORT][10] ([i915#10366])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14545/bat-dg2-9/igt@i915_selftest@live@active.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg2-9/igt@i915_selftest@live@active.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][11] ([i915#4212]) +7 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][12] ([i915#4215])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg1-7:          NOTRUN -> [SKIP][15]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-dg1-7:          NOTRUN -> [SKIP][16] ([i915#433])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg1-7:          NOTRUN -> [SKIP][17] ([i915#5354])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][18] ([i915#1072] / [i915#9732]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg1-7:          NOTRUN -> [SKIP][19] ([i915#3555])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][20] ([i915#3708]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg1-7:          NOTRUN -> [SKIP][21] ([i915#3708] / [i915#4077]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg1-7/igt@prime_vgem@basic-fence-mmap.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@migrate:
    - bat-dg2-8:          [ABORT][22] ([i915#10366] / [i915#10677]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14545/bat-dg2-8/igt@i915_selftest@live@migrate.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/bat-dg2-8/igt@i915_selftest@live@migrate.html

  
  [i915#10311]: https://gitlab.freedesktop.org/drm/intel/issues/10311
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10677]: https://gitlab.freedesktop.org/drm/intel/issues/10677
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732


Build changes
-------------

  * Linux: CI_DRM_14545 -> Patchwork_132168v1

  CI-20190529: 20190529
  CI_DRM_14545: 9c78ecd17c19a10cdb73b12362d6b9bf914105b2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7801: 7801
  Patchwork_132168v1: 9c78ecd17c19a10cdb73b12362d6b9bf914105b2 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

66ca261d8168 drm/i915: move rawclk from runtime to display runtime info
74b760bd58fc drm/i915: move rawclk init to intel_cdclk_init()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132168v1/index.html

[-- Attachment #2: Type: text/html, Size: 9348 bytes --]

✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init() (rev2)
URL   : https://patchwork.freedesktop.org/series/132168/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/132168/revisions/2/mbox/ not applied
Applying: drm/i915: move rawclk init to intel_cdclk_init()
Applying: drm/i915: move rawclk from runtime to display runtime info
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_cdclk.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915: move rawclk from runtime to display runtime info
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced