* [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable
@ 2024-04-19 10:04 Jani Nikula
2024-04-19 10:04 ` [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Jani Nikula @ 2024-04-19 10:04 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
v2 of [1], using struct intel_display * rather than struct
drm_i915_private *.
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1712766927.git.jani.nikula@intel.com
Jani Nikula (4):
drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
drm/i915/dsi: add VLV_ prefix to VLV only register macros
drm/i915/dsi: unify connector/encoder type and name usage
drm/i915/dsi: pass display to register macros instead of implicit
variable
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 467 +++++++++----------
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 327 +++++++------
4 files changed, 407 insertions(+), 417 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula @ 2024-04-19 10:04 ` Jani Nikula 2024-04-22 20:59 ` Rodrigo Vivi 2024-04-19 10:04 ` [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula ` (7 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2024-04-19 10:04 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula There are other unused registers, but this is also unusable and inadequate. Remove. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h index abbe427e462e..b0cdaad7db9c 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h @@ -93,9 +93,6 @@ #define TEARING_EFFECT_DELAY_SHIFT 0 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) -/* XXX: all bits reserved */ -#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) - /* MIPI DSI Controller and D-PHY registers */ #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) -- 2.39.2 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition 2024-04-19 10:04 ` [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula @ 2024-04-22 20:59 ` Rodrigo Vivi 2024-04-23 14:41 ` Jani Nikula 0 siblings, 1 reply; 18+ messages in thread From: Rodrigo Vivi @ 2024-04-22 20:59 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Fri, Apr 19, 2024 at 01:04:03PM +0300, Jani Nikula wrote: > There are other unused registers, but this is also unusable and > inadequate. Remove. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > index abbe427e462e..b0cdaad7db9c 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > @@ -93,9 +93,6 @@ > #define TEARING_EFFECT_DELAY_SHIFT 0 > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > -/* XXX: all bits reserved */ > -#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) > - > /* MIPI DSI Controller and D-PHY registers */ > > #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) > -- > 2.39.2 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition 2024-04-22 20:59 ` Rodrigo Vivi @ 2024-04-23 14:41 ` Jani Nikula 0 siblings, 0 replies; 18+ messages in thread From: Jani Nikula @ 2024-04-23 14:41 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx On Mon, 22 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Fri, Apr 19, 2024 at 01:04:03PM +0300, Jani Nikula wrote: >> There are other unused registers, but this is also unusable and >> inadequate. Remove. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Thanks for the review, pushed the lot to din. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 --- >> 1 file changed, 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> index abbe427e462e..b0cdaad7db9c 100644 >> --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> @@ -93,9 +93,6 @@ >> #define TEARING_EFFECT_DELAY_SHIFT 0 >> #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) >> >> -/* XXX: all bits reserved */ >> -#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) >> - >> /* MIPI DSI Controller and D-PHY registers */ >> >> #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) >> -- >> 2.39.2 >> -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula 2024-04-19 10:04 ` [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula @ 2024-04-19 10:04 ` Jani Nikula 2024-04-22 21:00 ` Rodrigo Vivi 2024-04-19 10:04 ` [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage Jani Nikula ` (6 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2024-04-19 10:04 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula All the BXT specific macros have BXT_ prefix, do the same for VLV for consistency. This is helpful because the platform specific macros can use the static MIPI MMIO base rather than dynamic. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/vlv_dsi.c | 6 +++--- drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 63f4af601d15..665247a2e834 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -481,7 +481,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) * Common bit for both MIPI Port A & MIPI Port C * No similar bit in MIPI Port C reg */ - intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); + intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); usleep_range(1000, 1500); intel_de_write(dev_priv, MIPI_DEVICE_READY(port), @@ -563,7 +563,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) { return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ? - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); } static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) @@ -576,7 +576,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); intel_de_write(dev_priv, MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h index b0cdaad7db9c..12a608a73720 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h @@ -40,7 +40,7 @@ #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) -#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) /* BXT port control */ #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 @@ -89,7 +89,7 @@ #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) -#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) #define TEARING_EFFECT_DELAY_SHIFT 0 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) -- 2.39.2 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros 2024-04-19 10:04 ` [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula @ 2024-04-22 21:00 ` Rodrigo Vivi 0 siblings, 0 replies; 18+ messages in thread From: Rodrigo Vivi @ 2024-04-22 21:00 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Fri, Apr 19, 2024 at 01:04:04PM +0300, Jani Nikula wrote: > All the BXT specific macros have BXT_ prefix, do the same for VLV for > consistency. This is helpful because the platform specific macros can > use the static MIPI MMIO base rather than dynamic. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi.c | 6 +++--- > drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c > index 63f4af601d15..665247a2e834 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c > @@ -481,7 +481,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > * Common bit for both MIPI Port A & MIPI Port C > * No similar bit in MIPI Port C reg > */ > - intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > + intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > @@ -563,7 +563,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) > static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) > { > return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ? > - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); > + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); > } > > static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > @@ -576,7 +576,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > for_each_dsi_port(port, intel_dsi->ports) { > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ > i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? > - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); > + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); > > intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > DEVICE_READY | ULPS_STATE_ENTER); > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > index b0cdaad7db9c..12a608a73720 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > @@ -40,7 +40,7 @@ > > #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) > #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > -#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > > /* BXT port control */ > #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 > @@ -89,7 +89,7 @@ > > #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) > #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > -#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > #define TEARING_EFFECT_DELAY_SHIFT 0 > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > -- > 2.39.2 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula 2024-04-19 10:04 ` [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula 2024-04-19 10:04 ` [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula @ 2024-04-19 10:04 ` Jani Nikula 2024-04-22 21:07 ` Rodrigo Vivi 2024-04-19 10:04 ` [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable Jani Nikula ` (5 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2024-04-19 10:04 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Stop using struct drm_* local variables and parameters where possible. Drop the intel_ prefix from struct intel_encoder and intel_connector local variable and parameter names. Drop useless intermediate variables. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/vlv_dsi.c | 134 +++++++++++-------------- 1 file changed, 60 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 665247a2e834..9967ef58f1ec 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -85,9 +85,7 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) { - struct drm_encoder *encoder = &intel_dsi->base.base; - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); u32 mask; mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | @@ -132,8 +130,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg) { struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); - struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); enum port port = intel_dsi_host->port; struct mipi_dsi_packet packet; ssize_t ret; @@ -225,9 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port) { - struct drm_encoder *encoder = &intel_dsi->base.base; - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); u32 mask; /* XXX: pipe, hs */ @@ -662,8 +658,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, static void intel_dsi_port_disable(struct intel_encoder *encoder) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -675,7 +670,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) intel_de_posting_read(dev_priv, port_ctrl); } } -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, + +static void intel_dsi_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config); static void intel_dsi_unprepare(struct intel_encoder *encoder); @@ -1009,8 +1005,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_display_mode *adjusted_mode_sw; @@ -1209,12 +1204,11 @@ static u16 txclkesc(u32 divider, unsigned int us) } } -static void set_dsi_timings(struct drm_encoder *encoder, +static void set_dsi_timings(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode) { - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); unsigned int lane_count = intel_dsi->lane_count; @@ -1298,14 +1292,12 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) } } -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, +static void intel_dsi_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { - struct drm_encoder *encoder = &intel_encoder->base; - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; enum port port; unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -1591,8 +1583,7 @@ static void vlv_dsi_add_properties(struct intel_connector *connector) static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) { - struct drm_device *dev = intel_dsi->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); struct intel_connector *connector = intel_dsi->attached_connector; struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; u32 tlpx_ns, extra_byte_count, tlpx_ui; @@ -1878,10 +1869,8 @@ static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { void vlv_dsi_init(struct drm_i915_private *dev_priv) { struct intel_dsi *intel_dsi; - struct intel_encoder *intel_encoder; - struct drm_encoder *encoder; - struct intel_connector *intel_connector; - struct drm_connector *connector; + struct intel_encoder *encoder; + struct intel_connector *connector; struct drm_display_mode *current_mode; const struct dmi_system_id *dmi_id; enum port port; @@ -1902,64 +1891,61 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) if (!intel_dsi) return; - intel_connector = intel_connector_alloc(); - if (!intel_connector) { + connector = intel_connector_alloc(); + if (!connector) { kfree(intel_dsi); return; } - intel_encoder = &intel_dsi->base; - encoder = &intel_encoder->base; - intel_dsi->attached_connector = intel_connector; - - connector = &intel_connector->base; + encoder = &intel_dsi->base; + intel_dsi->attached_connector = connector; - drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, - "DSI %c", port_name(port)); + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs, + DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); - intel_encoder->compute_config = intel_dsi_compute_config; - intel_encoder->pre_enable = intel_dsi_pre_enable; + encoder->compute_config = intel_dsi_compute_config; + encoder->pre_enable = intel_dsi_pre_enable; if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - intel_encoder->enable = bxt_dsi_enable; - intel_encoder->disable = intel_dsi_disable; - intel_encoder->post_disable = intel_dsi_post_disable; - intel_encoder->get_hw_state = intel_dsi_get_hw_state; - intel_encoder->get_config = intel_dsi_get_config; - intel_encoder->update_pipe = intel_backlight_update; - intel_encoder->shutdown = intel_dsi_shutdown; + encoder->enable = bxt_dsi_enable; + encoder->disable = intel_dsi_disable; + encoder->post_disable = intel_dsi_post_disable; + encoder->get_hw_state = intel_dsi_get_hw_state; + encoder->get_config = intel_dsi_get_config; + encoder->update_pipe = intel_backlight_update; + encoder->shutdown = intel_dsi_shutdown; - intel_connector->get_hw_state = intel_connector_get_hw_state; + connector->get_hw_state = intel_connector_get_hw_state; - intel_encoder->port = port; - intel_encoder->type = INTEL_OUTPUT_DSI; - intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; - intel_encoder->cloneable = 0; + encoder->port = port; + encoder->type = INTEL_OUTPUT_DSI; + encoder->power_domain = POWER_DOMAIN_PORT_DSI; + encoder->cloneable = 0; /* * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI * port C. BXT isn't limited like this. */ if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - intel_encoder->pipe_mask = ~0; + encoder->pipe_mask = ~0; else if (port == PORT_A) - intel_encoder->pipe_mask = BIT(PIPE_A); + encoder->pipe_mask = BIT(PIPE_A); else - intel_encoder->pipe_mask = BIT(PIPE_B); + encoder->pipe_mask = BIT(PIPE_B); intel_dsi->panel_power_off_time = ktime_get_boottime(); - intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); + intel_bios_init_panel_late(dev_priv, &connector->panel, NULL, NULL); - if (intel_connector->panel.vbt.dsi.config->dual_link) + if (connector->panel.vbt.dsi.config->dual_link) intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); else intel_dsi->ports = BIT(port); - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) - intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; + if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) + connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) - intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; + if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) + connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; /* Create a DSI host (and a device) for each port. */ for_each_dsi_port(port, intel_dsi->ports) { @@ -1979,7 +1965,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) } /* Use clock read-back from current hw-state for fastboot */ - current_mode = intel_encoder_current_mode(intel_encoder); + current_mode = intel_encoder_current_mode(encoder); if (current_mode) { drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", intel_dsi->pclk, current_mode->clock); @@ -1995,22 +1981,22 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) vlv_dphy_param_init(intel_dsi); intel_dsi_vbt_gpio_init(intel_dsi, - intel_dsi_get_hw_state(intel_encoder, &pipe)); + intel_dsi_get_hw_state(encoder, &pipe)); - drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, + drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); - drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); + drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); - connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ - intel_connector_attach_encoder(intel_connector, intel_encoder); + intel_connector_attach_encoder(connector, encoder); mutex_lock(&dev_priv->drm.mode_config.mutex); - intel_panel_add_vbt_lfp_fixed_mode(intel_connector); + intel_panel_add_vbt_lfp_fixed_mode(connector); mutex_unlock(&dev_priv->drm.mode_config.mutex); - if (!intel_panel_preferred_fixed_mode(intel_connector)) { + if (!intel_panel_preferred_fixed_mode(connector)) { drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); goto err_cleanup_connector; } @@ -2023,18 +2009,18 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) quirk_func(intel_dsi); } - intel_panel_init(intel_connector, NULL); + intel_panel_init(connector, NULL); - intel_backlight_setup(intel_connector, INVALID_PIPE); + intel_backlight_setup(connector, INVALID_PIPE); - vlv_dsi_add_properties(intel_connector); + vlv_dsi_add_properties(connector); return; err_cleanup_connector: - drm_connector_cleanup(&intel_connector->base); + drm_connector_cleanup(&connector->base); err: - drm_encoder_cleanup(&intel_encoder->base); + drm_encoder_cleanup(&encoder->base); kfree(intel_dsi); - kfree(intel_connector); + kfree(connector); } -- 2.39.2 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage 2024-04-19 10:04 ` [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage Jani Nikula @ 2024-04-22 21:07 ` Rodrigo Vivi 0 siblings, 0 replies; 18+ messages in thread From: Rodrigo Vivi @ 2024-04-22 21:07 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Fri, Apr 19, 2024 at 01:04:05PM +0300, Jani Nikula wrote: > Stop using struct drm_* local variables and parameters where > possible. Drop the intel_ prefix from struct intel_encoder and > intel_connector local variable and parameter names. Drop useless > intermediate variables. nice clean-up Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi.c | 134 +++++++++++-------------- > 1 file changed, 60 insertions(+), 74 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c > index 665247a2e834..9967ef58f1ec 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c > @@ -85,9 +85,7 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) > > void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) > { > - struct drm_encoder *encoder = &intel_dsi->base.base; > - struct drm_device *dev = encoder->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > u32 mask; > > mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > @@ -132,8 +130,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, > const struct mipi_dsi_msg *msg) > { > struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); > - struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; > + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > enum port port = intel_dsi_host->port; > struct mipi_dsi_packet packet; > ssize_t ret; > @@ -225,9 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { > static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, > enum port port) > { > - struct drm_encoder *encoder = &intel_dsi->base.base; > - struct drm_device *dev = encoder->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > u32 mask; > > /* XXX: pipe, hs */ > @@ -662,8 +658,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > > static void intel_dsi_port_disable(struct intel_encoder *encoder) > { > - struct drm_device *dev = encoder->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > @@ -675,7 +670,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) > intel_de_posting_read(dev_priv, port_ctrl); > } > } > -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > + > +static void intel_dsi_prepare(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config); > static void intel_dsi_unprepare(struct intel_encoder *encoder); > > @@ -1009,8 +1005,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > - struct drm_device *dev = encoder->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct drm_display_mode *adjusted_mode = > &pipe_config->hw.adjusted_mode; > struct drm_display_mode *adjusted_mode_sw; > @@ -1209,12 +1204,11 @@ static u16 txclkesc(u32 divider, unsigned int us) > } > } > > -static void set_dsi_timings(struct drm_encoder *encoder, > +static void set_dsi_timings(struct intel_encoder *encoder, > const struct drm_display_mode *adjusted_mode) > { > - struct drm_device *dev = encoder->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > - struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); > unsigned int lane_count = intel_dsi->lane_count; > @@ -1298,14 +1292,12 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) > } > } > > -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > +static void intel_dsi_prepare(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) > { > - struct drm_encoder *encoder = &intel_encoder->base; > - struct drm_device *dev = encoder->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > - struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; > enum port port; > unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); > @@ -1591,8 +1583,7 @@ static void vlv_dsi_add_properties(struct intel_connector *connector) > > static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) > { > - struct drm_device *dev = intel_dsi->base.base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns, extra_byte_count, tlpx_ui; > @@ -1878,10 +1869,8 @@ static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { > void vlv_dsi_init(struct drm_i915_private *dev_priv) > { > struct intel_dsi *intel_dsi; > - struct intel_encoder *intel_encoder; > - struct drm_encoder *encoder; > - struct intel_connector *intel_connector; > - struct drm_connector *connector; > + struct intel_encoder *encoder; > + struct intel_connector *connector; > struct drm_display_mode *current_mode; > const struct dmi_system_id *dmi_id; > enum port port; > @@ -1902,64 +1891,61 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > if (!intel_dsi) > return; > > - intel_connector = intel_connector_alloc(); > - if (!intel_connector) { > + connector = intel_connector_alloc(); > + if (!connector) { > kfree(intel_dsi); > return; > } > > - intel_encoder = &intel_dsi->base; > - encoder = &intel_encoder->base; > - intel_dsi->attached_connector = intel_connector; > - > - connector = &intel_connector->base; > + encoder = &intel_dsi->base; > + intel_dsi->attached_connector = connector; > > - drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, > - "DSI %c", port_name(port)); > + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs, > + DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); > > - intel_encoder->compute_config = intel_dsi_compute_config; > - intel_encoder->pre_enable = intel_dsi_pre_enable; > + encoder->compute_config = intel_dsi_compute_config; > + encoder->pre_enable = intel_dsi_pre_enable; > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > - intel_encoder->enable = bxt_dsi_enable; > - intel_encoder->disable = intel_dsi_disable; > - intel_encoder->post_disable = intel_dsi_post_disable; > - intel_encoder->get_hw_state = intel_dsi_get_hw_state; > - intel_encoder->get_config = intel_dsi_get_config; > - intel_encoder->update_pipe = intel_backlight_update; > - intel_encoder->shutdown = intel_dsi_shutdown; > + encoder->enable = bxt_dsi_enable; > + encoder->disable = intel_dsi_disable; > + encoder->post_disable = intel_dsi_post_disable; > + encoder->get_hw_state = intel_dsi_get_hw_state; > + encoder->get_config = intel_dsi_get_config; > + encoder->update_pipe = intel_backlight_update; > + encoder->shutdown = intel_dsi_shutdown; > > - intel_connector->get_hw_state = intel_connector_get_hw_state; > + connector->get_hw_state = intel_connector_get_hw_state; > > - intel_encoder->port = port; > - intel_encoder->type = INTEL_OUTPUT_DSI; > - intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; > - intel_encoder->cloneable = 0; > + encoder->port = port; > + encoder->type = INTEL_OUTPUT_DSI; > + encoder->power_domain = POWER_DOMAIN_PORT_DSI; > + encoder->cloneable = 0; > > /* > * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI > * port C. BXT isn't limited like this. > */ > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > - intel_encoder->pipe_mask = ~0; > + encoder->pipe_mask = ~0; > else if (port == PORT_A) > - intel_encoder->pipe_mask = BIT(PIPE_A); > + encoder->pipe_mask = BIT(PIPE_A); > else > - intel_encoder->pipe_mask = BIT(PIPE_B); > + encoder->pipe_mask = BIT(PIPE_B); > > intel_dsi->panel_power_off_time = ktime_get_boottime(); > > - intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); > + intel_bios_init_panel_late(dev_priv, &connector->panel, NULL, NULL); > > - if (intel_connector->panel.vbt.dsi.config->dual_link) > + if (connector->panel.vbt.dsi.config->dual_link) > intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); > else > intel_dsi->ports = BIT(port); > > - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) > - intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; > + if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) > + connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; > > - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) > - intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; > + if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) > + connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; > > /* Create a DSI host (and a device) for each port. */ > for_each_dsi_port(port, intel_dsi->ports) { > @@ -1979,7 +1965,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > } > > /* Use clock read-back from current hw-state for fastboot */ > - current_mode = intel_encoder_current_mode(intel_encoder); > + current_mode = intel_encoder_current_mode(encoder); > if (current_mode) { > drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", > intel_dsi->pclk, current_mode->clock); > @@ -1995,22 +1981,22 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > vlv_dphy_param_init(intel_dsi); > > intel_dsi_vbt_gpio_init(intel_dsi, > - intel_dsi_get_hw_state(intel_encoder, &pipe)); > + intel_dsi_get_hw_state(encoder, &pipe)); > > - drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, > + drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs, > DRM_MODE_CONNECTOR_DSI); > > - drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); > + drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); > > - connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ > + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ > > - intel_connector_attach_encoder(intel_connector, intel_encoder); > + intel_connector_attach_encoder(connector, encoder); > > mutex_lock(&dev_priv->drm.mode_config.mutex); > - intel_panel_add_vbt_lfp_fixed_mode(intel_connector); > + intel_panel_add_vbt_lfp_fixed_mode(connector); > mutex_unlock(&dev_priv->drm.mode_config.mutex); > > - if (!intel_panel_preferred_fixed_mode(intel_connector)) { > + if (!intel_panel_preferred_fixed_mode(connector)) { > drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); > goto err_cleanup_connector; > } > @@ -2023,18 +2009,18 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > quirk_func(intel_dsi); > } > > - intel_panel_init(intel_connector, NULL); > + intel_panel_init(connector, NULL); > > - intel_backlight_setup(intel_connector, INVALID_PIPE); > + intel_backlight_setup(connector, INVALID_PIPE); > > - vlv_dsi_add_properties(intel_connector); > + vlv_dsi_add_properties(connector); > > return; > > err_cleanup_connector: > - drm_connector_cleanup(&intel_connector->base); > + drm_connector_cleanup(&connector->base); > err: > - drm_encoder_cleanup(&intel_encoder->base); > + drm_encoder_cleanup(&encoder->base); > kfree(intel_dsi); > - kfree(intel_connector); > + kfree(connector); > } > -- > 2.39.2 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (2 preceding siblings ...) 2024-04-19 10:04 ` [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage Jani Nikula @ 2024-04-19 10:04 ` Jani Nikula 2024-04-22 21:10 ` Rodrigo Vivi 2024-04-19 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) Patchwork ` (4 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2024-04-19 10:04 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Stop relying on the dev_priv local variable in the DSI register macros. Pass struct intel_display pointer to the macros. Move the MIPI DSI MMIO base selection to a different level, passing it to _MMIO_MIPI() and doing the addition there. Start using the local display variable for all intel_de_* usage, and opportunistically use it for other things than display registers as well. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- Tip: Applying the patch and using 'git show --color-words' is probably the easiest way to review. --- drivers/gpu/drm/i915/display/intel_display.c | 8 +- drivers/gpu/drm/i915/display/vlv_dsi.c | 337 ++++++++++--------- drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +- drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 324 +++++++++--------- 4 files changed, 349 insertions(+), 342 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 96ed1490fec7..b9434465d3a7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder; enum port port; u32 tmp; @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, break; /* XXX: this works for video mode only */ - tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); + tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); if (!(tmp & DPI_ENABLE)) continue; - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + tmp = intel_de_read(display, MIPI_CTRL(display, port)); if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) continue; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 9967ef58f1ec..ee9923c7b115 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) { - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); + struct intel_display *display = to_intel_display(&intel_dsi->base); u32 mask; mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; - if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), + if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), mask, 100)) - drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); + drm_err(display->drm, "DPI FIFOs are not empty\n"); } -static void write_data(struct drm_i915_private *dev_priv, +static void write_data(struct intel_display *display, i915_reg_t reg, const u8 *data, u32 len) { @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private *dev_priv, for (j = 0; j < min_t(u32, len - i, 4); j++) val |= *data++ << 8 * j; - intel_de_write(dev_priv, reg, val); + intel_de_write(display, reg, val); } } -static void read_data(struct drm_i915_private *dev_priv, +static void read_data(struct intel_display *display, i915_reg_t reg, u8 *data, u32 len) { u32 i, j; for (i = 0; i < len; i += 4) { - u32 val = intel_de_read(dev_priv, reg); + u32 val = intel_de_read(display, reg); for (j = 0; j < min_t(u32, len - i, 4); j++) *data++ = val >> 8 * j; @@ -131,7 +131,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, { struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); + struct intel_display *display = to_intel_display(&intel_dsi->base); enum port port = intel_dsi_host->port; struct mipi_dsi_packet packet; ssize_t ret; @@ -146,51 +146,51 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, header = packet.header; if (msg->flags & MIPI_DSI_MSG_USE_LPM) { - data_reg = MIPI_LP_GEN_DATA(port); + data_reg = MIPI_LP_GEN_DATA(display, port); data_mask = LP_DATA_FIFO_FULL; - ctrl_reg = MIPI_LP_GEN_CTRL(port); + ctrl_reg = MIPI_LP_GEN_CTRL(display, port); ctrl_mask = LP_CTRL_FIFO_FULL; } else { - data_reg = MIPI_HS_GEN_DATA(port); + data_reg = MIPI_HS_GEN_DATA(display, port); data_mask = HS_DATA_FIFO_FULL; - ctrl_reg = MIPI_HS_GEN_CTRL(port); + ctrl_reg = MIPI_HS_GEN_CTRL(display, port); ctrl_mask = HS_CTRL_FIFO_FULL; } /* note: this is never true for reads */ if (packet.payload_length) { - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), data_mask, 50)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Timeout waiting for HS/LP DATA FIFO !full\n"); - write_data(dev_priv, data_reg, packet.payload, + write_data(display, data_reg, packet.payload, packet.payload_length); } if (msg->rx_len) { - intel_de_write(dev_priv, MIPI_INTR_STAT(port), + intel_de_write(display, MIPI_INTR_STAT(display, port), GEN_READ_DATA_AVAIL); } - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), ctrl_mask, 50)) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Timeout waiting for HS/LP CTRL FIFO !full\n"); } - intel_de_write(dev_priv, ctrl_reg, + intel_de_write(display, ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); /* ->rx_len is set only for reads */ if (msg->rx_len) { data_mask = GEN_READ_DATA_AVAIL; - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), data_mask, 50)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Timeout waiting for read data.\n"); - read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); + read_data(display, data_reg, msg->rx_buf, msg->rx_len); } /* XXX: fix for reads and writes */ @@ -223,7 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port) { - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); + struct intel_display *display = to_intel_display(&intel_dsi->base); u32 mask; /* XXX: pipe, hs */ @@ -233,18 +233,18 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, cmd |= DPI_LP_MODE; /* clear bit */ - intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); + intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); /* XXX: old code skips write if control unchanged */ - if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) - drm_dbg_kms(&dev_priv->drm, + if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) + drm_dbg_kms(display->drm, "Same special packet %02x twice in a row.\n", cmd); - intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); + intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); mask = SPL_PKT_SENT_INTERRUPT; - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) - drm_err(&dev_priv->drm, + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) + drm_err(display->drm, "Video mode command 0x%08x send failed.\n", cmd); return 0; @@ -324,7 +324,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, static bool glk_dsi_enable_io(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; bool cold_boot = false; @@ -334,29 +334,30 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) * Power ON MIPI IO first and then write into IO reset and LP wake bits */ for_each_dsi_port(port, intel_dsi->ports) - intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); + intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); /* Put the IO into reset */ - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); /* Program LP Wake */ for_each_dsi_port(port, intel_dsi->ports) { - u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); - intel_de_rmw(dev_priv, MIPI_CTRL(port), + u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); + + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); } /* Wait for Pwr ACK */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), GLK_MIPIIO_PORT_POWERED, 20)) - drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); + drm_err(display->drm, "MIPIO port is powergated\n"); } /* Check for cold boot scenario */ for_each_dsi_port(port, intel_dsi->ports) { cold_boot |= - !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); + !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); } return cold_boot; @@ -364,99 +365,100 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) static void glk_dsi_device_ready(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; /* Wait for MIPI PHY status bit to set */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), GLK_PHY_STATUS_PORT_READY, 20)) - drm_err(&dev_priv->drm, "PHY is not ON\n"); + drm_err(display->drm, "PHY is not ON\n"); } /* Get IO out of reset */ - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); /* Get IO out of Low power state*/ for_each_dsi_port(port, intel_dsi->ports) { - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_MASK, DEVICE_READY); usleep_range(10, 15); } else { /* Enter ULPS */ - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); /* Wait for ULPS active */ - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), GLK_ULPS_NOT_ACTIVE, 20)) - drm_err(&dev_priv->drm, "ULPS not active\n"); + drm_err(display->drm, "ULPS not active\n"); /* Exit ULPS */ - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); /* Enter Normal Mode */ - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_MASK, ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); } } /* Wait for Stop state */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), GLK_DATA_LANE_STOP_STATE, 20)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Date lane not in STOP state\n"); } /* Wait for AFE LATCH */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), + if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, 20)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "D-PHY not entering LP-11 state\n"); } } static void bxt_dsi_device_ready(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; u32 val; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); /* Enable MIPI PHY transparent latch */ for_each_dsi_port(port, intel_dsi->ports) { - intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); + intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); usleep_range(2000, 2500); } /* Clear ULPS and set device ready */ for_each_dsi_port(port, intel_dsi->ports) { - val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); + val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); val &= ~ULPS_STATE_MASK; - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); usleep_range(2000, 2500); val |= DEVICE_READY; - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); } } static void vlv_dsi_device_ready(struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); vlv_flisdsi_get(dev_priv); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms @@ -469,7 +471,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_ENTER); usleep_range(2500, 3000); @@ -477,14 +479,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) * Common bit for both MIPI Port A & MIPI Port C * No similar bit in MIPI Port C reg */ - intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); + intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); usleep_range(1000, 1500); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_EXIT); usleep_range(2500, 3000); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), DEVICE_READY); usleep_range(2500, 3000); } @@ -504,50 +506,50 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; /* Enter ULPS */ for_each_dsi_port(port, intel_dsi->ports) - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), GLK_PHY_STATUS_PORT_READY, 20)) - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); + drm_err(display->drm, "PHY is not turning OFF\n"); } /* Wait for Pwr ACK bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), GLK_MIPIIO_PORT_POWERED, 20)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "MIPI IO Port is not powergated\n"); } } static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; /* Put the IO into reset */ - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), GLK_PHY_STATUS_PORT_READY, 20)) - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); + drm_err(display->drm, "PHY is not turning OFF\n"); } /* Clear MIPI mode */ for_each_dsi_port(port, intel_dsi->ports) - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); } static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) @@ -564,25 +566,26 @@ static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), DEVICE_READY | ULPS_STATE_EXIT); usleep_range(2000, 2500); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + intel_de_write(display, MIPI_DEVICE_READY(display, port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); @@ -591,15 +594,15 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) * Port A only. MIPI Port C has no similar bit for checking. */ if ((IS_BROXTON(dev_priv) || port == PORT_A) && - intel_de_wait_for_clear(dev_priv, port_ctrl, + intel_de_wait_for_clear(display, port_ctrl, AFE_LATCHOUT, 30)) - drm_err(&dev_priv->drm, "DSI LP not going Low\n"); + drm_err(display->drm, "DSI LP not going Low\n"); /* Disable MIPI PHY transparent latch */ - intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); + intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); usleep_range(1000, 1500); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); usleep_range(2000, 2500); } } @@ -607,6 +610,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) static void intel_dsi_port_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); @@ -617,11 +621,11 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { for_each_dsi_port(port, intel_dsi->ports) - intel_de_rmw(dev_priv, MIPI_CTRL(port), + intel_de_rmw(display, MIPI_CTRL(display, port), BXT_PIXEL_OVERLAP_CNT_MASK, temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); } else { - intel_de_rmw(dev_priv, VLV_CHICKEN_3, + intel_de_rmw(display, VLV_CHICKEN_3, PIXEL_OVERLAP_CNT_MASK, temp << PIXEL_OVERLAP_CNT_SHIFT); } @@ -631,7 +635,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); u32 temp; - temp = intel_de_read(dev_priv, port_ctrl); + temp = intel_de_read(display, port_ctrl); temp &= ~LANE_CONFIGURATION_MASK; temp &= ~DUAL_LINK_MODE_MASK; @@ -651,13 +655,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, temp |= DITHERING_ENABLE; /* assert ip_tg_enable signal */ - intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); - intel_de_posting_read(dev_priv, port_ctrl); + intel_de_write(display, port_ctrl, temp | DPI_ENABLE); + intel_de_posting_read(display, port_ctrl); } } static void intel_dsi_port_disable(struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -666,8 +671,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); /* de-assert ip_tg_enable signal */ - intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); - intel_de_posting_read(dev_priv, port_ctrl); + intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); + intel_de_posting_read(display, port_ctrl); } } @@ -721,6 +726,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -728,7 +734,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, enum port port; bool glk_cold_boot = false; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); intel_dsi_wait_panel_power_cycle(intel_dsi); @@ -748,16 +754,16 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, if (IS_BROXTON(dev_priv)) { /* Add MIPI IO reset programming for modeset */ - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); /* Power up DSI regulator */ - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); } if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { /* Disable DPOunit clock gating, can stall pipe */ - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), 0, DPOUNIT_CLOCK_GATE_DISABLE); } @@ -793,8 +799,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, */ if (is_cmd_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) - intel_de_write(dev_priv, - MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); + intel_de_write(display, + MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); } else { @@ -866,11 +872,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { intel_crtc_vblank_off(old_crtc_state); @@ -901,12 +908,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, if (IS_BROXTON(dev_priv)) { /* Power down DSI regulator to save power */ - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); /* Add MIPI IO reset programming for modeset */ - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); } if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { @@ -914,7 +921,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, } else { vlv_dsi_pll_disable(encoder); - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), DPOUNIT_CLOCK_GATE_DISABLE, 0); } @@ -930,13 +937,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); intel_wakeref_t wakeref; enum port port; bool active = false; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); wakeref = intel_display_power_get_if_enabled(dev_priv, encoder->power_domain); @@ -955,7 +963,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, /* XXX: this only works for one DSI output */ for_each_dsi_port(port, intel_dsi->ports) { i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); - bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; + bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; /* * Due to some hardware limitations on VLV/CHV, the DPI enable @@ -964,27 +972,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, */ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && port == PORT_C) - enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; + enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; /* Try command mode if video mode not enabled */ if (!enabled) { - u32 tmp = intel_de_read(dev_priv, - MIPI_DSI_FUNC_PRG(port)); + u32 tmp = intel_de_read(display, + MIPI_DSI_FUNC_PRG(display, port)); enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; } if (!enabled) continue; - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) continue; if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); tmp &= BXT_PIPE_SELECT_MASK; tmp >>= BXT_PIPE_SELECT_SHIFT; - if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) + if (drm_WARN_ON(display->drm, tmp > PIPE_C)) continue; *pipe = tmp; @@ -1005,7 +1013,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_display_mode *adjusted_mode_sw; @@ -1027,11 +1035,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, * encoder->get_hw_state() returns true. */ for_each_dsi_port(port, intel_dsi->ports) { - if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) + if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) break; } - fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; + fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; bpp = mipi_dsi_pixel_format_to_bpp( pixel_format_from_register_bits(fmt)); @@ -1043,24 +1051,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, /* In terms of pixels */ adjusted_mode->crtc_hdisplay = - intel_de_read(dev_priv, + intel_de_read(display, BXT_MIPI_TRANS_HACTIVE(port)); adjusted_mode->crtc_vdisplay = - intel_de_read(dev_priv, + intel_de_read(display, BXT_MIPI_TRANS_VACTIVE(port)); adjusted_mode->crtc_vtotal = - intel_de_read(dev_priv, + intel_de_read(display, BXT_MIPI_TRANS_VTOTAL(port)); hactive = adjusted_mode->crtc_hdisplay; - hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); + hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); /* * Meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); - hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); + hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); + hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); /* harizontal values are in terms of high speed byte clock */ hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, @@ -1077,8 +1085,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, } /* vertical values are in terms of lines */ - vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); - vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); + vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); + vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; @@ -1207,6 +1215,7 @@ static u16 txclkesc(u32 divider, unsigned int us) static void set_dsi_timings(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -1249,29 +1258,29 @@ static void set_dsi_timings(struct intel_encoder *encoder, * vactive, as they are calculated per channel basis, * whereas these values should be based on resolution. */ - intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), + intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), adjusted_mode->crtc_hdisplay); - intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), + intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), adjusted_mode->crtc_vdisplay); - intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), + intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), adjusted_mode->crtc_vtotal); } - intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), + intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), hactive); - intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); + intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); /* meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), + intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), hsync); - intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); + intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); /* vertical values are in terms of lines */ - intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); - intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), + intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); + intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), vsync); - intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); + intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); } } @@ -1295,6 +1304,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) static void intel_dsi_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); @@ -1304,7 +1314,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, u32 val, tmp; u16 mode_hdisplay; - drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); + drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); mode_hdisplay = adjusted_mode->crtc_hdisplay; @@ -1320,31 +1330,31 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, * escape clock divider, 20MHz, shared for A and C. * device ready must be off when doing this! txclkesc? */ - tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); + tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - intel_de_write(dev_priv, MIPI_CTRL(PORT_A), + intel_de_write(display, MIPI_CTRL(display, PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); /* read request priority is per pipe */ - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + tmp = intel_de_read(display, MIPI_CTRL(display, port)); tmp &= ~READ_REQUEST_PRIORITY_MASK; - intel_de_write(dev_priv, MIPI_CTRL(port), + intel_de_write(display, MIPI_CTRL(display, port), tmp | READ_REQUEST_PRIORITY_HIGH); } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { enum pipe pipe = crtc->pipe; - intel_de_rmw(dev_priv, MIPI_CTRL(port), + intel_de_rmw(display, MIPI_CTRL(display, port), BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); } /* XXX: why here, why like this? handling in irq handler?! */ - intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); - intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); + intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); + intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); - intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), + intel_de_write(display, MIPI_DPHY_PARAM(display, port), intel_dsi->dphy_reg); - intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), + intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); } @@ -1372,7 +1382,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, } for_each_dsi_port(port, intel_dsi->ports) { - intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); + intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); /* timeouts for recovery. one frame IIUC. if counter expires, * EOT and stop state. */ @@ -1393,23 +1403,23 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, if (is_vid_mode(intel_dsi) && intel_dsi->video_mode == BURST_MODE) { - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } else { - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } - intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), + intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), intel_dsi->lp_rx_timeout); - intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), + intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), intel_dsi->turn_arnd_val); - intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), + intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), intel_dsi->rst_timer_val); /* dphy stuff */ /* in terms of low power clock */ - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + intel_de_write(display, MIPI_INIT_COUNT(display, port), txclkesc(intel_dsi->escape_clk_div, 100)); if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && @@ -1420,16 +1430,16 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, * getting used. So write the other port * if not in dual link mode. */ - intel_de_write(dev_priv, - MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), + intel_de_write(display, + MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), intel_dsi->init_count); } /* recovery disables */ - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); + intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); /* in terms of low power clock */ - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + intel_de_write(display, MIPI_INIT_COUNT(display, port), intel_dsi->init_count); /* in terms of txbyteclkhs. actual high to low switch + @@ -1437,7 +1447,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, * * XXX: write MIPI_STOP_STATE_STALL? */ - intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), + intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), intel_dsi->hs_to_lp_count); /* XXX: low power clock equivalence in terms of byte clock. @@ -1446,14 +1456,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL * ) / 105.??? */ - intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), + intel_de_write(display, MIPI_LP_BYTECLK(display, port), intel_dsi->lp_byte_clk); if (IS_GEMINILAKE(dev_priv)) { - intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), + intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), intel_dsi->lp_byte_clk); /* Shadow of DPHY reg */ - intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), + intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), intel_dsi->dphy_reg); } @@ -1462,10 +1472,10 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, * this register in terms of byte clocks. based on dsi transfer * rate and the number of lanes configured the time taken to * transmit 16 long packets in a dsi stream varies. */ - intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), + intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), intel_dsi->bw_timer); - intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), + intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); if (is_vid_mode(intel_dsi)) { @@ -1493,13 +1503,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, break; } - intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); + intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); } } } static void intel_dsi_unprepare(struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -1509,17 +1520,17 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { /* Panel commands can be sent when clock is in LP11 */ - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_dsi_reset_clocks(encoder, port); else vlv_dsi_reset_clocks(encoder, port); - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); - intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); + intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); } } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index ae0a0b11bae3..70c5a13a3c75 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -365,13 +365,13 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) { - u32 temp; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + u32 temp; - temp = intel_de_read(dev_priv, MIPI_CTRL(port)); + temp = intel_de_read(display, MIPI_CTRL(display, port)); temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - intel_de_write(dev_priv, MIPI_CTRL(port), + intel_de_write(display, MIPI_CTRL(display, port), temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); } @@ -570,24 +570,24 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) { + struct intel_display *display = to_intel_display(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 tmp; - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); /* Clear old configurations */ if (IS_BROXTON(dev_priv)) { - tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); + tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); - intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); + intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); } else { - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); } - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); } static void assert_dsi_pll(struct drm_i915_private *i915, bool state) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h index 12a608a73720..c1126d170ec6 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h @@ -11,26 +11,23 @@ #define VLV_MIPI_BASE VLV_DISPLAY_BASE #define BXT_MIPI_BASE 0x60000 -#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) +#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ -#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) +#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) /* BXT MIPI mode configure */ -#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 -#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 -#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ - _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) +#define _BXT_MIPIA_TRANS_HACTIVE 0xb0f8 +#define _BXT_MIPIC_TRANS_HACTIVE 0xb8f8 +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) -#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC -#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC -#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ - _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) +#define _BXT_MIPIA_TRANS_VACTIVE 0xb0fc +#define _BXT_MIPIC_TRANS_VACTIVE 0xb8fc +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) -#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 -#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 -#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ - _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) +#define _BXT_MIPIA_TRANS_VTOTAL 0xb100 +#define _BXT_MIPIC_TRANS_VTOTAL 0xb900 +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) #define STAP_SELECT (1 << 0) @@ -38,14 +35,14 @@ #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) #define HS_IO_CTRL_SELECT (1 << 0) -#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) -#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) -#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) +#define _MIPIA_PORT_CTRL 0x61190 +#define _MIPIC_PORT_CTRL 0x61700 +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) /* BXT port control */ -#define _BXT_MIPIA_PORT_CTRL 0x6B0C0 -#define _BXT_MIPIC_PORT_CTRL 0x6B8C0 -#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) +#define _BXT_MIPIA_PORT_CTRL 0xb0c0 +#define _BXT_MIPIC_PORT_CTRL 0xb8c0 +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) #define DPI_ENABLE (1 << 31) /* A + C */ #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 @@ -87,17 +84,17 @@ #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) -#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) -#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) -#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) +#define _MIPIA_TEARING_CTRL 0x61194 +#define _MIPIC_TEARING_CTRL 0x61704 +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) #define TEARING_EFFECT_DELAY_SHIFT 0 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) /* MIPI DSI Controller and D-PHY registers */ -#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) -#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) -#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) +#define _MIPIA_DEVICE_READY 0xb000 +#define _MIPIC_DEVICE_READY 0xb800 +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ #define ULPS_STATE_MASK (3 << 1) #define ULPS_STATE_ENTER (2 << 1) @@ -105,12 +102,12 @@ #define ULPS_STATE_NORMAL_OPERATION (0 << 1) #define DEVICE_READY (1 << 0) -#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) -#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) -#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) -#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) -#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) -#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) +#define _MIPIA_INTR_STAT 0xb004 +#define _MIPIC_INTR_STAT 0xb804 +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) +#define _MIPIA_INTR_EN 0xb008 +#define _MIPIC_INTR_EN 0xb808 +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) #define TEARING_EFFECT (1 << 31) #define SPL_PKT_SENT_INTERRUPT (1 << 30) #define GEN_READ_DATA_AVAIL (1 << 29) @@ -144,9 +141,9 @@ #define RXSOT_SYNC_ERROR (1 << 1) #define RXSOT_ERROR (1 << 0) -#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) -#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) -#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) +#define _MIPIA_DSI_FUNC_PRG 0xb00c +#define _MIPIC_DSI_FUNC_PRG 0xb80c +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) #define CMD_MODE_NOT_SUPPORTED (0 << 13) #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) @@ -167,77 +164,77 @@ #define DATA_LANES_PRG_REG_SHIFT 0 #define DATA_LANES_PRG_REG_MASK (7 << 0) -#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) -#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) -#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) +#define _MIPIA_HS_TX_TIMEOUT 0xb010 +#define _MIPIC_HS_TX_TIMEOUT 0xb810 +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff -#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) -#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) -#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) +#define _MIPIA_LP_RX_TIMEOUT 0xb014 +#define _MIPIC_LP_RX_TIMEOUT 0xb814 +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff -#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) -#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) -#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) +#define _MIPIA_TURN_AROUND_TIMEOUT 0xb018 +#define _MIPIC_TURN_AROUND_TIMEOUT 0xb818 +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) #define TURN_AROUND_TIMEOUT_MASK 0x3f -#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) -#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) -#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) +#define _MIPIA_DEVICE_RESET_TIMER 0xb01c +#define _MIPIC_DEVICE_RESET_TIMER 0xb81c +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) #define DEVICE_RESET_TIMER_MASK 0xffff -#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) -#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) -#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) +#define _MIPIA_DPI_RESOLUTION 0xb020 +#define _MIPIC_DPI_RESOLUTION 0xb820 +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) #define VERTICAL_ADDRESS_SHIFT 16 #define VERTICAL_ADDRESS_MASK (0xffff << 16) #define HORIZONTAL_ADDRESS_SHIFT 0 #define HORIZONTAL_ADDRESS_MASK 0xffff -#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) -#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) -#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) +#define _MIPIA_DBI_FIFO_THROTTLE 0xb024 +#define _MIPIC_DBI_FIFO_THROTTLE 0xb824 +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) #define DBI_FIFO_EMPTY_HALF (0 << 0) #define DBI_FIFO_EMPTY_QUARTER (1 << 0) #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) /* regs below are bits 15:0 */ -#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) -#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) -#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) +#define _MIPIA_HSYNC_PADDING_COUNT 0xb028 +#define _MIPIC_HSYNC_PADDING_COUNT 0xb828 +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) -#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) -#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) -#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) +#define _MIPIA_HBP_COUNT 0xb02c +#define _MIPIC_HBP_COUNT 0xb82c +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) -#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) -#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) -#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) +#define _MIPIA_HFP_COUNT 0xb030 +#define _MIPIC_HFP_COUNT 0xb830 +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) -#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) -#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) -#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) +#define _MIPIA_HACTIVE_AREA_COUNT 0xb034 +#define _MIPIC_HACTIVE_AREA_COUNT 0xb834 +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) -#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) -#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) -#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) +#define _MIPIA_VSYNC_PADDING_COUNT 0xb038 +#define _MIPIC_VSYNC_PADDING_COUNT 0xb838 +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) -#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) -#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) -#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) +#define _MIPIA_VBP_COUNT 0xb03c +#define _MIPIC_VBP_COUNT 0xb83c +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) -#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) -#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) -#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) +#define _MIPIA_VFP_COUNT 0xb040 +#define _MIPIC_VFP_COUNT 0xb840 +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) -#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) -#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) -#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) +#define _MIPIA_HIGH_LOW_SWITCH_COUNT 0xb044 +#define _MIPIC_HIGH_LOW_SWITCH_COUNT 0xb844 +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) -#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) -#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) -#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) +#define _MIPIA_DPI_CONTROL 0xb048 +#define _MIPIC_DPI_CONTROL 0xb848 +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) #define DPI_LP_MODE (1 << 6) #define BACKLIGHT_OFF (1 << 5) #define BACKLIGHT_ON (1 << 4) @@ -246,28 +243,27 @@ #define TURN_ON (1 << 1) #define SHUTDOWN (1 << 0) -#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) -#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) -#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) +#define _MIPIA_DPI_DATA 0xb04c +#define _MIPIC_DPI_DATA 0xb84c +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) #define COMMAND_BYTE_SHIFT 0 #define COMMAND_BYTE_MASK (0x3f << 0) -#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) -#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) -#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) +#define _MIPIA_INIT_COUNT 0xb050 +#define _MIPIC_INIT_COUNT 0xb850 +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) #define MASTER_INIT_TIMER_SHIFT 0 #define MASTER_INIT_TIMER_MASK (0xffff << 0) -#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) -#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) -#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) +#define _MIPIA_MAX_RETURN_PKT_SIZE 0xb054 +#define _MIPIC_MAX_RETURN_PKT_SIZE 0xb854 +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) #define MAX_RETURN_PKT_SIZE_SHIFT 0 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) -#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) -#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) -#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) +#define _MIPIA_VIDEO_MODE_FORMAT 0xb058 +#define _MIPIC_VIDEO_MODE_FORMAT 0xb858 +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) #define DISABLE_VIDEO_BTA (1 << 3) #define IP_TG_CONFIG (1 << 2) @@ -275,9 +271,9 @@ #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) #define VIDEO_MODE_BURST (3 << 0) -#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) -#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) -#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) +#define _MIPIA_EOT_DISABLE 0xb05c +#define _MIPIC_EOT_DISABLE 0xb85c +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) #define BXT_DPHY_DEFEATURE_EN (1 << 8) #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) @@ -289,36 +285,36 @@ #define CLOCKSTOP (1 << 1) #define EOT_DISABLE (1 << 0) -#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) -#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) -#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) +#define _MIPIA_LP_BYTECLK 0xb060 +#define _MIPIC_LP_BYTECLK 0xb860 +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) #define LP_BYTECLK_SHIFT 0 #define LP_BYTECLK_MASK (0xffff << 0) -#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) -#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) -#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) +#define _MIPIA_TLPX_TIME_COUNT 0xb0a4 +#define _MIPIC_TLPX_TIME_COUNT 0xb8a4 +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) -#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) -#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) -#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) +#define _MIPIA_CLK_LANE_TIMING 0xb098 +#define _MIPIC_CLK_LANE_TIMING 0xb898 +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) /* bits 31:0 */ -#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) -#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) -#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) +#define _MIPIA_LP_GEN_DATA 0xb064 +#define _MIPIC_LP_GEN_DATA 0xb864 +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) /* bits 31:0 */ -#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) -#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) -#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) - -#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) -#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) -#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) -#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) -#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) -#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) +#define _MIPIA_HS_GEN_DATA 0xb068 +#define _MIPIC_HS_GEN_DATA 0xb868 +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) + +#define _MIPIA_LP_GEN_CTRL 0xb06c +#define _MIPIC_LP_GEN_CTRL 0xb86c +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) +#define _MIPIA_HS_GEN_CTRL 0xb070 +#define _MIPIC_HS_GEN_CTRL 0xb870 +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) #define LONG_PACKET_WORD_COUNT_SHIFT 8 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) #define SHORT_PACKET_PARAM_SHIFT 8 @@ -329,9 +325,9 @@ #define DATA_TYPE_MASK (0x3f << 0) /* data type values, see include/video/mipi_display.h */ -#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) -#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) -#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) +#define _MIPIA_GEN_FIFO_STAT 0xb074 +#define _MIPIC_GEN_FIFO_STAT 0xb874 +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) #define DPI_FIFO_EMPTY (1 << 28) #define DBI_FIFO_EMPTY (1 << 27) #define LP_CTRL_FIFO_EMPTY (1 << 26) @@ -347,16 +343,16 @@ #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) #define HS_DATA_FIFO_FULL (1 << 0) -#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) -#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) -#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) +#define _MIPIA_HS_LS_DBI_ENABLE 0xb078 +#define _MIPIC_HS_LS_DBI_ENABLE 0xb878 +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) #define DBI_HS_LP_MODE_MASK (1 << 0) #define DBI_LP_MODE (1 << 0) #define DBI_HS_MODE (0 << 0) -#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) -#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) -#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) +#define _MIPIA_DPHY_PARAM 0xb080 +#define _MIPIC_DPHY_PARAM 0xb880 +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) #define EXIT_ZERO_COUNT_SHIFT 24 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) #define TRAIL_COUNT_SHIFT 16 @@ -366,34 +362,34 @@ #define PREPARE_COUNT_SHIFT 0 #define PREPARE_COUNT_MASK (0x3f << 0) -#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) -#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) -#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) +#define _MIPIA_DBI_BW_CTRL 0xb084 +#define _MIPIC_DBI_BW_CTRL 0xb884 +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) -#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT 0xb088 +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT 0xb888 +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) #define LP_HS_SSW_CNT_SHIFT 16 #define LP_HS_SSW_CNT_MASK (0xffff << 16) #define HS_LP_PWR_SW_CNT_SHIFT 0 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) -#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) -#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) -#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) +#define _MIPIA_STOP_STATE_STALL 0xb08c +#define _MIPIC_STOP_STATE_STALL 0xb88c +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) #define STOP_STATE_STALL_COUNTER_SHIFT 0 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) -#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) -#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) -#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) -#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) -#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) -#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) +#define _MIPIA_INTR_STAT_REG_1 0xb090 +#define _MIPIC_INTR_STAT_REG_1 0xb890 +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) +#define _MIPIA_INTR_EN_REG_1 0xb094 +#define _MIPIC_INTR_EN_REG_1 0xb894 +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) #define RX_CONTENTION_DETECTED (1 << 0) /* XXX: only pipe A ?!? */ -#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) +#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) #define DBI_TYPEC_ENABLE (1 << 31) #define DBI_TYPEC_WIP (1 << 30) #define DBI_TYPEC_OPTION_SHIFT 28 @@ -406,9 +402,9 @@ /* MIPI adapter registers */ -#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) -#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) -#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) +#define _MIPIA_CTRL 0xb104 +#define _MIPIC_CTRL 0xb904 +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) @@ -439,41 +435,41 @@ #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ #define GLK_MIPIIO_ENABLE (1 << 0) -#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) -#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) -#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) +#define _MIPIA_DATA_ADDRESS 0xb108 +#define _MIPIC_DATA_ADDRESS 0xb908 +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) #define DATA_MEM_ADDRESS_SHIFT 5 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) #define DATA_VALID (1 << 0) -#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) -#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) -#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) +#define _MIPIA_DATA_LENGTH 0xb10c +#define _MIPIC_DATA_LENGTH 0xb90c +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) #define DATA_LENGTH_SHIFT 0 #define DATA_LENGTH_MASK (0xfffff << 0) -#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) -#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) -#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) +#define _MIPIA_COMMAND_ADDRESS 0xb110 +#define _MIPIC_COMMAND_ADDRESS 0xb910 +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) #define COMMAND_MEM_ADDRESS_SHIFT 5 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) #define AUTO_PWG_ENABLE (1 << 2) #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) #define COMMAND_VALID (1 << 0) -#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) -#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) -#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) +#define _MIPIA_COMMAND_LENGTH 0xb114 +#define _MIPIC_COMMAND_LENGTH 0xb914 +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) -#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) -#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) -#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ +#define _MIPIA_READ_DATA_RETURN0 0xb118 +#define _MIPIC_READ_DATA_RETURN0 0xb918 +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ -#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) -#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) -#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) +#define _MIPIA_READ_DATA_VALID 0xb138 +#define _MIPIC_READ_DATA_VALID 0xb938 +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) #define READ_DATA_VALID(n) (1 << (n)) #endif /* __VLV_DSI_REGS_H__ */ -- 2.39.2 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable 2024-04-19 10:04 ` [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable Jani Nikula @ 2024-04-22 21:10 ` Rodrigo Vivi 2024-04-22 21:16 ` Gustavo Sousa 0 siblings, 1 reply; 18+ messages in thread From: Rodrigo Vivi @ 2024-04-22 21:10 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote: > Stop relying on the dev_priv local variable in the DSI register > macros. Pass struct intel_display pointer to the macros. Move the MIPI > DSI MMIO base selection to a different level, passing it to _MMIO_MIPI() > and doing the addition there. > > Start using the local display variable for all intel_de_* usage, and > opportunistically use it for other things than display registers as > well. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > Tip: Applying the patch and using 'git show --color-words' is probably > the easiest way to review. wow! this is indeed a nice feature for this case. I had never tried it before. Thanks for showing that. But the registers changes were easier to review the old way. ;) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 +- > drivers/gpu/drm/i915/display/vlv_dsi.c | 337 ++++++++++--------- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +- > drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 324 +++++++++--------- > 4 files changed, 349 insertions(+), 342 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 96ed1490fec7..b9434465d3a7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config, > struct intel_display_power_domain_set *power_domain_set) > { > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_display *display = to_intel_display(crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder; > enum port port; > u32 tmp; > @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, > break; > > /* XXX: this works for video mode only */ > - tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); > + tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); > if (!(tmp & DPI_ENABLE)) > continue; > > - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > + tmp = intel_de_read(display, MIPI_CTRL(display, port)); > if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) > continue; > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c > index 9967ef58f1ec..ee9923c7b115 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c > @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) > > void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) > { > - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > + struct intel_display *display = to_intel_display(&intel_dsi->base); > u32 mask; > > mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; > > - if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), > + if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), > mask, 100)) > - drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); > + drm_err(display->drm, "DPI FIFOs are not empty\n"); > } > > -static void write_data(struct drm_i915_private *dev_priv, > +static void write_data(struct intel_display *display, > i915_reg_t reg, > const u8 *data, u32 len) > { > @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private *dev_priv, > for (j = 0; j < min_t(u32, len - i, 4); j++) > val |= *data++ << 8 * j; > > - intel_de_write(dev_priv, reg, val); > + intel_de_write(display, reg, val); > } > } > > -static void read_data(struct drm_i915_private *dev_priv, > +static void read_data(struct intel_display *display, > i915_reg_t reg, > u8 *data, u32 len) > { > u32 i, j; > > for (i = 0; i < len; i += 4) { > - u32 val = intel_de_read(dev_priv, reg); > + u32 val = intel_de_read(display, reg); > > for (j = 0; j < min_t(u32, len - i, 4); j++) > *data++ = val >> 8 * j; > @@ -131,7 +131,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, > { > struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); > struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; > - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > + struct intel_display *display = to_intel_display(&intel_dsi->base); > enum port port = intel_dsi_host->port; > struct mipi_dsi_packet packet; > ssize_t ret; > @@ -146,51 +146,51 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, > header = packet.header; > > if (msg->flags & MIPI_DSI_MSG_USE_LPM) { > - data_reg = MIPI_LP_GEN_DATA(port); > + data_reg = MIPI_LP_GEN_DATA(display, port); > data_mask = LP_DATA_FIFO_FULL; > - ctrl_reg = MIPI_LP_GEN_CTRL(port); > + ctrl_reg = MIPI_LP_GEN_CTRL(display, port); > ctrl_mask = LP_CTRL_FIFO_FULL; > } else { > - data_reg = MIPI_HS_GEN_DATA(port); > + data_reg = MIPI_HS_GEN_DATA(display, port); > data_mask = HS_DATA_FIFO_FULL; > - ctrl_reg = MIPI_HS_GEN_CTRL(port); > + ctrl_reg = MIPI_HS_GEN_CTRL(display, port); > ctrl_mask = HS_CTRL_FIFO_FULL; > } > > /* note: this is never true for reads */ > if (packet.payload_length) { > - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), > + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), > data_mask, 50)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Timeout waiting for HS/LP DATA FIFO !full\n"); > > - write_data(dev_priv, data_reg, packet.payload, > + write_data(display, data_reg, packet.payload, > packet.payload_length); > } > > if (msg->rx_len) { > - intel_de_write(dev_priv, MIPI_INTR_STAT(port), > + intel_de_write(display, MIPI_INTR_STAT(display, port), > GEN_READ_DATA_AVAIL); > } > > - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), > + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), > ctrl_mask, 50)) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Timeout waiting for HS/LP CTRL FIFO !full\n"); > } > > - intel_de_write(dev_priv, ctrl_reg, > + intel_de_write(display, ctrl_reg, > header[2] << 16 | header[1] << 8 | header[0]); > > /* ->rx_len is set only for reads */ > if (msg->rx_len) { > data_mask = GEN_READ_DATA_AVAIL; > - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), > + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), > data_mask, 50)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Timeout waiting for read data.\n"); > > - read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); > + read_data(display, data_reg, msg->rx_buf, msg->rx_len); > } > > /* XXX: fix for reads and writes */ > @@ -223,7 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { > static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, > enum port port) > { > - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > + struct intel_display *display = to_intel_display(&intel_dsi->base); > u32 mask; > > /* XXX: pipe, hs */ > @@ -233,18 +233,18 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, > cmd |= DPI_LP_MODE; > > /* clear bit */ > - intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); > + intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); > > /* XXX: old code skips write if control unchanged */ > - if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) > - drm_dbg_kms(&dev_priv->drm, > + if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) > + drm_dbg_kms(display->drm, > "Same special packet %02x twice in a row.\n", cmd); > > - intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); > + intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); > > mask = SPL_PKT_SENT_INTERRUPT; > - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) > - drm_err(&dev_priv->drm, > + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) > + drm_err(display->drm, > "Video mode command 0x%08x send failed.\n", cmd); > > return 0; > @@ -324,7 +324,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, > > static bool glk_dsi_enable_io(struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > bool cold_boot = false; > @@ -334,29 +334,30 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) > * Power ON MIPI IO first and then write into IO reset and LP wake bits > */ > for_each_dsi_port(port, intel_dsi->ports) > - intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); > + intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); > > /* Put the IO into reset */ > - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > > /* Program LP Wake */ > for_each_dsi_port(port, intel_dsi->ports) { > - u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); > - intel_de_rmw(dev_priv, MIPI_CTRL(port), > + u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); > + > + intel_de_rmw(display, MIPI_CTRL(display, port), > GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); > } > > /* Wait for Pwr ACK */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > GLK_MIPIIO_PORT_POWERED, 20)) > - drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); > + drm_err(display->drm, "MIPIO port is powergated\n"); > } > > /* Check for cold boot scenario */ > for_each_dsi_port(port, intel_dsi->ports) { > cold_boot |= > - !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); > + !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); > } > > return cold_boot; > @@ -364,99 +365,100 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) > > static void glk_dsi_device_ready(struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > /* Wait for MIPI PHY status bit to set */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > GLK_PHY_STATUS_PORT_READY, 20)) > - drm_err(&dev_priv->drm, "PHY is not ON\n"); > + drm_err(display->drm, "PHY is not ON\n"); > } > > /* Get IO out of reset */ > - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); > + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); > > /* Get IO out of Low power state*/ > for_each_dsi_port(port, intel_dsi->ports) { > - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { > - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { > + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_MASK, DEVICE_READY); > usleep_range(10, 15); > } else { > /* Enter ULPS */ > - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); > > /* Wait for ULPS active */ > - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > GLK_ULPS_NOT_ACTIVE, 20)) > - drm_err(&dev_priv->drm, "ULPS not active\n"); > + drm_err(display->drm, "ULPS not active\n"); > > /* Exit ULPS */ > - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); > > /* Enter Normal Mode */ > - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_MASK, > ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > > - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); > + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); > } > } > > /* Wait for Stop state */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > GLK_DATA_LANE_STOP_STATE, 20)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Date lane not in STOP state\n"); > } > > /* Wait for AFE LATCH */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), > + if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), > AFE_LATCHOUT, 20)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "D-PHY not entering LP-11 state\n"); > } > } > > static void bxt_dsi_device_ready(struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > u32 val; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > > /* Enable MIPI PHY transparent latch */ > for_each_dsi_port(port, intel_dsi->ports) { > - intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); > + intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); > usleep_range(2000, 2500); > } > > /* Clear ULPS and set device ready */ > for_each_dsi_port(port, intel_dsi->ports) { > - val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); > + val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); > val &= ~ULPS_STATE_MASK; > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); > + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); > usleep_range(2000, 2500); > val |= DEVICE_READY; > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); > + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); > } > } > > static void vlv_dsi_device_ready(struct intel_encoder *encoder) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > > vlv_flisdsi_get(dev_priv); > /* program rcomp for compliance, reduce from 50 ohms to 45 ohms > @@ -469,7 +471,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > > for_each_dsi_port(port, intel_dsi->ports) { > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_ENTER); > usleep_range(2500, 3000); > > @@ -477,14 +479,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > * Common bit for both MIPI Port A & MIPI Port C > * No similar bit in MIPI Port C reg > */ > - intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > + intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_EXIT); > usleep_range(2500, 3000); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > DEVICE_READY); > usleep_range(2500, 3000); > } > @@ -504,50 +506,50 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > > static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > /* Enter ULPS */ > for_each_dsi_port(port, intel_dsi->ports) > - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); > > /* Wait for MIPI PHY status bit to unset */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > GLK_PHY_STATUS_PORT_READY, 20)) > - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); > + drm_err(display->drm, "PHY is not turning OFF\n"); > } > > /* Wait for Pwr ACK bit to unset */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > GLK_MIPIIO_PORT_POWERED, 20)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "MIPI IO Port is not powergated\n"); > } > } > > static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > /* Put the IO into reset */ > - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > > /* Wait for MIPI PHY status bit to unset */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > GLK_PHY_STATUS_PORT_READY, 20)) > - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); > + drm_err(display->drm, "PHY is not turning OFF\n"); > } > > /* Clear MIPI mode */ > for_each_dsi_port(port, intel_dsi->ports) > - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); > + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); > } > > static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) > @@ -564,25 +566,26 @@ static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) > > static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > for_each_dsi_port(port, intel_dsi->ports) { > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ > i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? > BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > DEVICE_READY | ULPS_STATE_EXIT); > usleep_range(2000, 2500); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > + intel_de_write(display, MIPI_DEVICE_READY(display, port), > DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > @@ -591,15 +594,15 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > * Port A only. MIPI Port C has no similar bit for checking. > */ > if ((IS_BROXTON(dev_priv) || port == PORT_A) && > - intel_de_wait_for_clear(dev_priv, port_ctrl, > + intel_de_wait_for_clear(display, port_ctrl, > AFE_LATCHOUT, 30)) > - drm_err(&dev_priv->drm, "DSI LP not going Low\n"); > + drm_err(display->drm, "DSI LP not going Low\n"); > > /* Disable MIPI PHY transparent latch */ > - intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); > + intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); > usleep_range(1000, 1500); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); > + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); > usleep_range(2000, 2500); > } > } > @@ -607,6 +610,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > static void intel_dsi_port_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > @@ -617,11 +621,11 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > for_each_dsi_port(port, intel_dsi->ports) > - intel_de_rmw(dev_priv, MIPI_CTRL(port), > + intel_de_rmw(display, MIPI_CTRL(display, port), > BXT_PIXEL_OVERLAP_CNT_MASK, > temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); > } else { > - intel_de_rmw(dev_priv, VLV_CHICKEN_3, > + intel_de_rmw(display, VLV_CHICKEN_3, > PIXEL_OVERLAP_CNT_MASK, > temp << PIXEL_OVERLAP_CNT_SHIFT); > } > @@ -631,7 +635,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > u32 temp; > > - temp = intel_de_read(dev_priv, port_ctrl); > + temp = intel_de_read(display, port_ctrl); > > temp &= ~LANE_CONFIGURATION_MASK; > temp &= ~DUAL_LINK_MODE_MASK; > @@ -651,13 +655,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > temp |= DITHERING_ENABLE; > > /* assert ip_tg_enable signal */ > - intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); > - intel_de_posting_read(dev_priv, port_ctrl); > + intel_de_write(display, port_ctrl, temp | DPI_ENABLE); > + intel_de_posting_read(display, port_ctrl); > } > } > > static void intel_dsi_port_disable(struct intel_encoder *encoder) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > @@ -666,8 +671,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) > i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > > /* de-assert ip_tg_enable signal */ > - intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); > - intel_de_posting_read(dev_priv, port_ctrl); > + intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); > + intel_de_posting_read(display, port_ctrl); > } > } > > @@ -721,6 +726,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > const struct intel_crtc_state *pipe_config, > const struct drm_connector_state *conn_state) > { > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > @@ -728,7 +734,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > enum port port; > bool glk_cold_boot = false; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > > intel_dsi_wait_panel_power_cycle(intel_dsi); > > @@ -748,16 +754,16 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > > if (IS_BROXTON(dev_priv)) { > /* Add MIPI IO reset programming for modeset */ > - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); > + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); > > /* Power up DSI regulator */ > - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); > + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); > } > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > /* Disable DPOunit clock gating, can stall pipe */ > - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), > + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), > 0, DPOUNIT_CLOCK_GATE_DISABLE); > } > > @@ -793,8 +799,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > */ > if (is_cmd_mode(intel_dsi)) { > for_each_dsi_port(port, intel_dsi->ports) > - intel_de_write(dev_priv, > - MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); > + intel_de_write(display, > + MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); > intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); > intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); > } else { > @@ -866,11 +872,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > const struct intel_crtc_state *old_crtc_state, > const struct drm_connector_state *old_conn_state) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > intel_crtc_vblank_off(old_crtc_state); > @@ -901,12 +908,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > > if (IS_BROXTON(dev_priv)) { > /* Power down DSI regulator to save power */ > - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, > + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, > HS_IO_CTRL_SELECT); > > /* Add MIPI IO reset programming for modeset */ > - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); > + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); > } > > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > @@ -914,7 +921,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > } else { > vlv_dsi_pll_disable(encoder); > > - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), > + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), > DPOUNIT_CLOCK_GATE_DISABLE, 0); > } > > @@ -930,13 +937,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > enum pipe *pipe) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > intel_wakeref_t wakeref; > enum port port; > bool active = false; > > - drm_dbg_kms(&dev_priv->drm, "\n"); > + drm_dbg_kms(display->drm, "\n"); > > wakeref = intel_display_power_get_if_enabled(dev_priv, > encoder->power_domain); > @@ -955,7 +963,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > /* XXX: this only works for one DSI output */ > for_each_dsi_port(port, intel_dsi->ports) { > i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > - bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; > + bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; > > /* > * Due to some hardware limitations on VLV/CHV, the DPI enable > @@ -964,27 +972,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > */ > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > port == PORT_C) > - enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; > + enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; > > /* Try command mode if video mode not enabled */ > if (!enabled) { > - u32 tmp = intel_de_read(dev_priv, > - MIPI_DSI_FUNC_PRG(port)); > + u32 tmp = intel_de_read(display, > + MIPI_DSI_FUNC_PRG(display, port)); > enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; > } > > if (!enabled) > continue; > > - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) > + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) > continue; > > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > - u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > + u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); > tmp &= BXT_PIPE_SELECT_MASK; > tmp >>= BXT_PIPE_SELECT_SHIFT; > > - if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) > + if (drm_WARN_ON(display->drm, tmp > PIPE_C)) > continue; > > *pipe = tmp; > @@ -1005,7 +1013,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct drm_display_mode *adjusted_mode = > &pipe_config->hw.adjusted_mode; > struct drm_display_mode *adjusted_mode_sw; > @@ -1027,11 +1035,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > * encoder->get_hw_state() returns true. > */ > for_each_dsi_port(port, intel_dsi->ports) { > - if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) > + if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) > break; > } > > - fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; > + fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; > bpp = mipi_dsi_pixel_format_to_bpp( > pixel_format_from_register_bits(fmt)); > > @@ -1043,24 +1051,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > > /* In terms of pixels */ > adjusted_mode->crtc_hdisplay = > - intel_de_read(dev_priv, > + intel_de_read(display, > BXT_MIPI_TRANS_HACTIVE(port)); > adjusted_mode->crtc_vdisplay = > - intel_de_read(dev_priv, > + intel_de_read(display, > BXT_MIPI_TRANS_VACTIVE(port)); > adjusted_mode->crtc_vtotal = > - intel_de_read(dev_priv, > + intel_de_read(display, > BXT_MIPI_TRANS_VTOTAL(port)); > > hactive = adjusted_mode->crtc_hdisplay; > - hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); > + hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); > > /* > * Meaningful for video mode non-burst sync pulse mode only, > * can be zero for non-burst sync events and burst modes > */ > - hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); > - hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); > + hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); > + hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); > > /* harizontal values are in terms of high speed byte clock */ > hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, > @@ -1077,8 +1085,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > } > > /* vertical values are in terms of lines */ > - vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); > - vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); > + vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); > + vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); > > adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; > adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; > @@ -1207,6 +1215,7 @@ static u16 txclkesc(u32 divider, unsigned int us) > static void set_dsi_timings(struct intel_encoder *encoder, > const struct drm_display_mode *adjusted_mode) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > @@ -1249,29 +1258,29 @@ static void set_dsi_timings(struct intel_encoder *encoder, > * vactive, as they are calculated per channel basis, > * whereas these values should be based on resolution. > */ > - intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), > + intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), > adjusted_mode->crtc_hdisplay); > - intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), > + intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), > adjusted_mode->crtc_vdisplay); > - intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), > + intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), > adjusted_mode->crtc_vtotal); > } > > - intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), > + intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), > hactive); > - intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); > + intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); > > /* meaningful for video mode non-burst sync pulse mode only, > * can be zero for non-burst sync events and burst modes */ > - intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), > + intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), > hsync); > - intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); > + intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); > > /* vertical values are in terms of lines */ > - intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); > - intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), > + intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); > + intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), > vsync); > - intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); > + intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); > } > } > > @@ -1295,6 +1304,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) > static void intel_dsi_prepare(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > @@ -1304,7 +1314,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > u32 val, tmp; > u16 mode_hdisplay; > > - drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); > + drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); > > mode_hdisplay = adjusted_mode->crtc_hdisplay; > > @@ -1320,31 +1330,31 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > * escape clock divider, 20MHz, shared for A and C. > * device ready must be off when doing this! txclkesc? > */ > - tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); > + tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); > tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - intel_de_write(dev_priv, MIPI_CTRL(PORT_A), > + intel_de_write(display, MIPI_CTRL(display, PORT_A), > tmp | ESCAPE_CLOCK_DIVIDER_1); > > /* read request priority is per pipe */ > - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > + tmp = intel_de_read(display, MIPI_CTRL(display, port)); > tmp &= ~READ_REQUEST_PRIORITY_MASK; > - intel_de_write(dev_priv, MIPI_CTRL(port), > + intel_de_write(display, MIPI_CTRL(display, port), > tmp | READ_REQUEST_PRIORITY_HIGH); > } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > enum pipe pipe = crtc->pipe; > > - intel_de_rmw(dev_priv, MIPI_CTRL(port), > + intel_de_rmw(display, MIPI_CTRL(display, port), > BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); > } > > /* XXX: why here, why like this? handling in irq handler?! */ > - intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); > - intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); > + intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); > + intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); > > - intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), > + intel_de_write(display, MIPI_DPHY_PARAM(display, port), > intel_dsi->dphy_reg); > > - intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), > + intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), > adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); > } > > @@ -1372,7 +1382,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > } > > for_each_dsi_port(port, intel_dsi->ports) { > - intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); > + intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); > > /* timeouts for recovery. one frame IIUC. if counter expires, > * EOT and stop state. */ > @@ -1393,23 +1403,23 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > > if (is_vid_mode(intel_dsi) && > intel_dsi->video_mode == BURST_MODE) { > - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), > + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), > txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); > } else { > - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), > + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), > txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); > } > - intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), > + intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), > intel_dsi->lp_rx_timeout); > - intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), > + intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), > intel_dsi->turn_arnd_val); > - intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), > + intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), > intel_dsi->rst_timer_val); > > /* dphy stuff */ > > /* in terms of low power clock */ > - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), > + intel_de_write(display, MIPI_INIT_COUNT(display, port), > txclkesc(intel_dsi->escape_clk_div, 100)); > > if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && > @@ -1420,16 +1430,16 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > * getting used. So write the other port > * if not in dual link mode. > */ > - intel_de_write(dev_priv, > - MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), > + intel_de_write(display, > + MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), > intel_dsi->init_count); > } > > /* recovery disables */ > - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); > + intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); > > /* in terms of low power clock */ > - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), > + intel_de_write(display, MIPI_INIT_COUNT(display, port), > intel_dsi->init_count); > > /* in terms of txbyteclkhs. actual high to low switch + > @@ -1437,7 +1447,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > * > * XXX: write MIPI_STOP_STATE_STALL? > */ > - intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), > + intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), > intel_dsi->hs_to_lp_count); > > /* XXX: low power clock equivalence in terms of byte clock. > @@ -1446,14 +1456,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL > * ) / 105.??? > */ > - intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), > + intel_de_write(display, MIPI_LP_BYTECLK(display, port), > intel_dsi->lp_byte_clk); > > if (IS_GEMINILAKE(dev_priv)) { > - intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), > + intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), > intel_dsi->lp_byte_clk); > /* Shadow of DPHY reg */ > - intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), > + intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), > intel_dsi->dphy_reg); > } > > @@ -1462,10 +1472,10 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > * this register in terms of byte clocks. based on dsi transfer > * rate and the number of lanes configured the time taken to > * transmit 16 long packets in a dsi stream varies. */ > - intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), > + intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), > intel_dsi->bw_timer); > > - intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), > + intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), > intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); > > if (is_vid_mode(intel_dsi)) { > @@ -1493,13 +1503,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > break; > } > > - intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); > + intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); > } > } > } > > static void intel_dsi_unprepare(struct intel_encoder *encoder) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > @@ -1509,17 +1520,17 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) > > for_each_dsi_port(port, intel_dsi->ports) { > /* Panel commands can be sent when clock is in LP11 */ > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); > + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); > > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > bxt_dsi_reset_clocks(encoder, port); > else > vlv_dsi_reset_clocks(encoder, port); > - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); > + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); > > - intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); > + intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); > > - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); > + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); > } > } > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > index ae0a0b11bae3..70c5a13a3c75 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > @@ -365,13 +365,13 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, > > void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) > { > - u32 temp; > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(encoder); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > + u32 temp; > > - temp = intel_de_read(dev_priv, MIPI_CTRL(port)); > + temp = intel_de_read(display, MIPI_CTRL(display, port)); > temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - intel_de_write(dev_priv, MIPI_CTRL(port), > + intel_de_write(display, MIPI_CTRL(display, port), > temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); > } > > @@ -570,24 +570,24 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, > > void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) > { > + struct intel_display *display = to_intel_display(encoder); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u32 tmp; > - struct drm_device *dev = encoder->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > > /* Clear old configurations */ > if (IS_BROXTON(dev_priv)) { > - tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); > + tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); > tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); > tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); > tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); > tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); > - intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); > + intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); > } else { > - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); > + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); > > - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); > + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); > } > - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); > + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); > } > > static void assert_dsi_pll(struct drm_i915_private *i915, bool state) > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > index 12a608a73720..c1126d170ec6 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > @@ -11,26 +11,23 @@ > #define VLV_MIPI_BASE VLV_DISPLAY_BASE > #define BXT_MIPI_BASE 0x60000 > > -#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) > +#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) > > #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ > -#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) > +#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) > > /* BXT MIPI mode configure */ > -#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 > -#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 > -#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ > - _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) > +#define _BXT_MIPIA_TRANS_HACTIVE 0xb0f8 > +#define _BXT_MIPIC_TRANS_HACTIVE 0xb8f8 > +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) > > -#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC > -#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC > -#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ > - _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) > +#define _BXT_MIPIA_TRANS_VACTIVE 0xb0fc > +#define _BXT_MIPIC_TRANS_VACTIVE 0xb8fc > +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) > > -#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 > -#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 > -#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ > - _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) > +#define _BXT_MIPIA_TRANS_VTOTAL 0xb100 > +#define _BXT_MIPIC_TRANS_VTOTAL 0xb900 > +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) > > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) > #define STAP_SELECT (1 << 0) > @@ -38,14 +35,14 @@ > #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) > #define HS_IO_CTRL_SELECT (1 << 0) > > -#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) > -#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > -#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > +#define _MIPIA_PORT_CTRL 0x61190 > +#define _MIPIC_PORT_CTRL 0x61700 > +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > > /* BXT port control */ > -#define _BXT_MIPIA_PORT_CTRL 0x6B0C0 > -#define _BXT_MIPIC_PORT_CTRL 0x6B8C0 > -#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) > +#define _BXT_MIPIA_PORT_CTRL 0xb0c0 > +#define _BXT_MIPIC_PORT_CTRL 0xb8c0 > +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) > > #define DPI_ENABLE (1 << 31) /* A + C */ > #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 > @@ -87,17 +84,17 @@ > #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) > #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) > > -#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) > -#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > -#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > +#define _MIPIA_TEARING_CTRL 0x61194 > +#define _MIPIC_TEARING_CTRL 0x61704 > +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > #define TEARING_EFFECT_DELAY_SHIFT 0 > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > /* MIPI DSI Controller and D-PHY registers */ > > -#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) > -#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) > -#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) > +#define _MIPIA_DEVICE_READY 0xb000 > +#define _MIPIC_DEVICE_READY 0xb800 > +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) > #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ > #define ULPS_STATE_MASK (3 << 1) > #define ULPS_STATE_ENTER (2 << 1) > @@ -105,12 +102,12 @@ > #define ULPS_STATE_NORMAL_OPERATION (0 << 1) > #define DEVICE_READY (1 << 0) > > -#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) > -#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) > -#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) > -#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) > -#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) > -#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) > +#define _MIPIA_INTR_STAT 0xb004 > +#define _MIPIC_INTR_STAT 0xb804 > +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) > +#define _MIPIA_INTR_EN 0xb008 > +#define _MIPIC_INTR_EN 0xb808 > +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) > #define TEARING_EFFECT (1 << 31) > #define SPL_PKT_SENT_INTERRUPT (1 << 30) > #define GEN_READ_DATA_AVAIL (1 << 29) > @@ -144,9 +141,9 @@ > #define RXSOT_SYNC_ERROR (1 << 1) > #define RXSOT_ERROR (1 << 0) > > -#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) > -#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) > -#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) > +#define _MIPIA_DSI_FUNC_PRG 0xb00c > +#define _MIPIC_DSI_FUNC_PRG 0xb80c > +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) > #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) > #define CMD_MODE_NOT_SUPPORTED (0 << 13) > #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) > @@ -167,77 +164,77 @@ > #define DATA_LANES_PRG_REG_SHIFT 0 > #define DATA_LANES_PRG_REG_MASK (7 << 0) > > -#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) > -#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) > -#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) > +#define _MIPIA_HS_TX_TIMEOUT 0xb010 > +#define _MIPIC_HS_TX_TIMEOUT 0xb810 > +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) > #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff > > -#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) > -#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) > -#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) > +#define _MIPIA_LP_RX_TIMEOUT 0xb014 > +#define _MIPIC_LP_RX_TIMEOUT 0xb814 > +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) > #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff > > -#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) > -#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) > -#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > +#define _MIPIA_TURN_AROUND_TIMEOUT 0xb018 > +#define _MIPIC_TURN_AROUND_TIMEOUT 0xb818 > +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > #define TURN_AROUND_TIMEOUT_MASK 0x3f > > -#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) > -#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) > -#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > +#define _MIPIA_DEVICE_RESET_TIMER 0xb01c > +#define _MIPIC_DEVICE_RESET_TIMER 0xb81c > +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > #define DEVICE_RESET_TIMER_MASK 0xffff > > -#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) > -#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) > -#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) > +#define _MIPIA_DPI_RESOLUTION 0xb020 > +#define _MIPIC_DPI_RESOLUTION 0xb820 > +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) > #define VERTICAL_ADDRESS_SHIFT 16 > #define VERTICAL_ADDRESS_MASK (0xffff << 16) > #define HORIZONTAL_ADDRESS_SHIFT 0 > #define HORIZONTAL_ADDRESS_MASK 0xffff > > -#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) > -#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) > -#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > +#define _MIPIA_DBI_FIFO_THROTTLE 0xb024 > +#define _MIPIC_DBI_FIFO_THROTTLE 0xb824 > +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > #define DBI_FIFO_EMPTY_HALF (0 << 0) > #define DBI_FIFO_EMPTY_QUARTER (1 << 0) > #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) > > /* regs below are bits 15:0 */ > -#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) > -#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) > -#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > +#define _MIPIA_HSYNC_PADDING_COUNT 0xb028 > +#define _MIPIC_HSYNC_PADDING_COUNT 0xb828 > +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > > -#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) > -#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) > -#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) > +#define _MIPIA_HBP_COUNT 0xb02c > +#define _MIPIC_HBP_COUNT 0xb82c > +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) > > -#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) > -#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) > -#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) > +#define _MIPIA_HFP_COUNT 0xb030 > +#define _MIPIC_HFP_COUNT 0xb830 > +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) > > -#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) > -#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) > -#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > +#define _MIPIA_HACTIVE_AREA_COUNT 0xb034 > +#define _MIPIC_HACTIVE_AREA_COUNT 0xb834 > +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > > -#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) > -#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) > -#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > +#define _MIPIA_VSYNC_PADDING_COUNT 0xb038 > +#define _MIPIC_VSYNC_PADDING_COUNT 0xb838 > +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > > -#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) > -#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) > -#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) > +#define _MIPIA_VBP_COUNT 0xb03c > +#define _MIPIC_VBP_COUNT 0xb83c > +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) > > -#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) > -#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) > -#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) > +#define _MIPIA_VFP_COUNT 0xb040 > +#define _MIPIC_VFP_COUNT 0xb840 > +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) > > -#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) > -#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) > -#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > +#define _MIPIA_HIGH_LOW_SWITCH_COUNT 0xb044 > +#define _MIPIC_HIGH_LOW_SWITCH_COUNT 0xb844 > +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > > -#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) > -#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) > -#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) > +#define _MIPIA_DPI_CONTROL 0xb048 > +#define _MIPIC_DPI_CONTROL 0xb848 > +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) > #define DPI_LP_MODE (1 << 6) > #define BACKLIGHT_OFF (1 << 5) > #define BACKLIGHT_ON (1 << 4) > @@ -246,28 +243,27 @@ > #define TURN_ON (1 << 1) > #define SHUTDOWN (1 << 0) > > -#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) > -#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) > -#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) > +#define _MIPIA_DPI_DATA 0xb04c > +#define _MIPIC_DPI_DATA 0xb84c > +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) > #define COMMAND_BYTE_SHIFT 0 > #define COMMAND_BYTE_MASK (0x3f << 0) > > -#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) > -#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) > -#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) > +#define _MIPIA_INIT_COUNT 0xb050 > +#define _MIPIC_INIT_COUNT 0xb850 > +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) > #define MASTER_INIT_TIMER_SHIFT 0 > #define MASTER_INIT_TIMER_MASK (0xffff << 0) > > -#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) > -#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) > -#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ > - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > +#define _MIPIA_MAX_RETURN_PKT_SIZE 0xb054 > +#define _MIPIC_MAX_RETURN_PKT_SIZE 0xb854 > +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > #define MAX_RETURN_PKT_SIZE_SHIFT 0 > #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) > > -#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) > -#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) > -#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > +#define _MIPIA_VIDEO_MODE_FORMAT 0xb058 > +#define _MIPIC_VIDEO_MODE_FORMAT 0xb858 > +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) > #define DISABLE_VIDEO_BTA (1 << 3) > #define IP_TG_CONFIG (1 << 2) > @@ -275,9 +271,9 @@ > #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) > #define VIDEO_MODE_BURST (3 << 0) > > -#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) > -#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) > -#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) > +#define _MIPIA_EOT_DISABLE 0xb05c > +#define _MIPIC_EOT_DISABLE 0xb85c > +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) > #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) > #define BXT_DPHY_DEFEATURE_EN (1 << 8) > #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) > @@ -289,36 +285,36 @@ > #define CLOCKSTOP (1 << 1) > #define EOT_DISABLE (1 << 0) > > -#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) > -#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) > -#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) > +#define _MIPIA_LP_BYTECLK 0xb060 > +#define _MIPIC_LP_BYTECLK 0xb860 > +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) > #define LP_BYTECLK_SHIFT 0 > #define LP_BYTECLK_MASK (0xffff << 0) > > -#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) > -#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) > -#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) > +#define _MIPIA_TLPX_TIME_COUNT 0xb0a4 > +#define _MIPIC_TLPX_TIME_COUNT 0xb8a4 > +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) > > -#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) > -#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) > -#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) > +#define _MIPIA_CLK_LANE_TIMING 0xb098 > +#define _MIPIC_CLK_LANE_TIMING 0xb898 > +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) > > /* bits 31:0 */ > -#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) > -#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) > -#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) > +#define _MIPIA_LP_GEN_DATA 0xb064 > +#define _MIPIC_LP_GEN_DATA 0xb864 > +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) > > /* bits 31:0 */ > -#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) > -#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) > -#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) > - > -#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) > -#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) > -#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) > -#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) > -#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) > -#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) > +#define _MIPIA_HS_GEN_DATA 0xb068 > +#define _MIPIC_HS_GEN_DATA 0xb868 > +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) > + > +#define _MIPIA_LP_GEN_CTRL 0xb06c > +#define _MIPIC_LP_GEN_CTRL 0xb86c > +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) > +#define _MIPIA_HS_GEN_CTRL 0xb070 > +#define _MIPIC_HS_GEN_CTRL 0xb870 > +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) > #define LONG_PACKET_WORD_COUNT_SHIFT 8 > #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) > #define SHORT_PACKET_PARAM_SHIFT 8 > @@ -329,9 +325,9 @@ > #define DATA_TYPE_MASK (0x3f << 0) > /* data type values, see include/video/mipi_display.h */ > > -#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) > -#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) > -#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) > +#define _MIPIA_GEN_FIFO_STAT 0xb074 > +#define _MIPIC_GEN_FIFO_STAT 0xb874 > +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) > #define DPI_FIFO_EMPTY (1 << 28) > #define DBI_FIFO_EMPTY (1 << 27) > #define LP_CTRL_FIFO_EMPTY (1 << 26) > @@ -347,16 +343,16 @@ > #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) > #define HS_DATA_FIFO_FULL (1 << 0) > > -#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) > -#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) > -#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > +#define _MIPIA_HS_LS_DBI_ENABLE 0xb078 > +#define _MIPIC_HS_LS_DBI_ENABLE 0xb878 > +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > #define DBI_HS_LP_MODE_MASK (1 << 0) > #define DBI_LP_MODE (1 << 0) > #define DBI_HS_MODE (0 << 0) > > -#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) > -#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) > -#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) > +#define _MIPIA_DPHY_PARAM 0xb080 > +#define _MIPIC_DPHY_PARAM 0xb880 > +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) > #define EXIT_ZERO_COUNT_SHIFT 24 > #define EXIT_ZERO_COUNT_MASK (0x3f << 24) > #define TRAIL_COUNT_SHIFT 16 > @@ -366,34 +362,34 @@ > #define PREPARE_COUNT_SHIFT 0 > #define PREPARE_COUNT_MASK (0x3f << 0) > > -#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) > -#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) > -#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) > +#define _MIPIA_DBI_BW_CTRL 0xb084 > +#define _MIPIC_DBI_BW_CTRL 0xb884 > +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) > > -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) > -#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) > -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT 0xb088 > +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT 0xb888 > +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > #define LP_HS_SSW_CNT_SHIFT 16 > #define LP_HS_SSW_CNT_MASK (0xffff << 16) > #define HS_LP_PWR_SW_CNT_SHIFT 0 > #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) > > -#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) > -#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) > -#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > +#define _MIPIA_STOP_STATE_STALL 0xb08c > +#define _MIPIC_STOP_STATE_STALL 0xb88c > +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > #define STOP_STATE_STALL_COUNTER_SHIFT 0 > #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) > > -#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) > -#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) > -#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > -#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) > -#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) > -#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) > +#define _MIPIA_INTR_STAT_REG_1 0xb090 > +#define _MIPIC_INTR_STAT_REG_1 0xb890 > +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > +#define _MIPIA_INTR_EN_REG_1 0xb094 > +#define _MIPIC_INTR_EN_REG_1 0xb894 > +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) > #define RX_CONTENTION_DETECTED (1 << 0) > > /* XXX: only pipe A ?!? */ > -#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) > +#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) > #define DBI_TYPEC_ENABLE (1 << 31) > #define DBI_TYPEC_WIP (1 << 30) > #define DBI_TYPEC_OPTION_SHIFT 28 > @@ -406,9 +402,9 @@ > > /* MIPI adapter registers */ > > -#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) > -#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) > -#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) > +#define _MIPIA_CTRL 0xb104 > +#define _MIPIC_CTRL 0xb904 > +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) > #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ > #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) > #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) > @@ -439,41 +435,41 @@ > #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ > #define GLK_MIPIIO_ENABLE (1 << 0) > > -#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) > -#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) > -#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) > +#define _MIPIA_DATA_ADDRESS 0xb108 > +#define _MIPIC_DATA_ADDRESS 0xb908 > +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) > #define DATA_MEM_ADDRESS_SHIFT 5 > #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define DATA_VALID (1 << 0) > > -#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) > -#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) > -#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) > +#define _MIPIA_DATA_LENGTH 0xb10c > +#define _MIPIC_DATA_LENGTH 0xb90c > +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) > #define DATA_LENGTH_SHIFT 0 > #define DATA_LENGTH_MASK (0xfffff << 0) > > -#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) > -#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) > -#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > +#define _MIPIA_COMMAND_ADDRESS 0xb110 > +#define _MIPIC_COMMAND_ADDRESS 0xb910 > +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > #define COMMAND_MEM_ADDRESS_SHIFT 5 > #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define AUTO_PWG_ENABLE (1 << 2) > #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) > #define COMMAND_VALID (1 << 0) > > -#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) > -#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) > -#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) > +#define _MIPIA_COMMAND_LENGTH 0xb114 > +#define _MIPIC_COMMAND_LENGTH 0xb914 > +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) > #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ > #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) > > -#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) > -#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) > -#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ > +#define _MIPIA_READ_DATA_RETURN0 0xb118 > +#define _MIPIC_READ_DATA_RETURN0 0xb918 > +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ > > -#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) > -#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) > -#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > +#define _MIPIA_READ_DATA_VALID 0xb138 > +#define _MIPIC_READ_DATA_VALID 0xb938 > +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > #define READ_DATA_VALID(n) (1 << (n)) > > #endif /* __VLV_DSI_REGS_H__ */ > -- > 2.39.2 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable 2024-04-22 21:10 ` Rodrigo Vivi @ 2024-04-22 21:16 ` Gustavo Sousa 2024-04-22 21:21 ` Rodrigo Vivi 0 siblings, 1 reply; 18+ messages in thread From: Gustavo Sousa @ 2024-04-22 21:16 UTC (permalink / raw) To: Jani Nikula, Rodrigo Vivi; +Cc: intel-gfx Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00) >On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote: >> Stop relying on the dev_priv local variable in the DSI register >> macros. Pass struct intel_display pointer to the macros. Move the MIPI >> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI() >> and doing the addition there. >> >> Start using the local display variable for all intel_de_* usage, and >> opportunistically use it for other things than display registers as >> well. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> >> --- >> >> Tip: Applying the patch and using 'git show --color-words' is probably >> the easiest way to review. > >wow! this is indeed a nice feature for this case. I had never tried it before. >Thanks for showing that. > >But the registers changes were easier to review the old way. ;) What about --word-diff for those? :-) -- Gustavo Sousa > >Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 8 +- >> drivers/gpu/drm/i915/display/vlv_dsi.c | 337 ++++++++++--------- >> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +- >> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 324 +++++++++--------- >> 4 files changed, 349 insertions(+), 342 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index 96ed1490fec7..b9434465d3a7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, >> struct intel_crtc_state *pipe_config, >> struct intel_display_power_domain_set *power_domain_set) >> { >> - struct drm_device *dev = crtc->base.dev; >> - struct drm_i915_private *dev_priv = to_i915(dev); >> + struct intel_display *display = to_intel_display(crtc); >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> enum transcoder cpu_transcoder; >> enum port port; >> u32 tmp; >> @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, >> break; >> >> /* XXX: this works for video mode only */ >> - tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); >> + tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); >> if (!(tmp & DPI_ENABLE)) >> continue; >> >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); >> + tmp = intel_de_read(display, MIPI_CTRL(display, port)); >> if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) >> continue; >> >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c >> index 9967ef58f1ec..ee9923c7b115 100644 >> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c >> @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) >> >> void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) >> { >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); >> + struct intel_display *display = to_intel_display(&intel_dsi->base); >> u32 mask; >> >> mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | >> LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; >> >> - if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), >> + if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), >> mask, 100)) >> - drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); >> + drm_err(display->drm, "DPI FIFOs are not empty\n"); >> } >> >> -static void write_data(struct drm_i915_private *dev_priv, >> +static void write_data(struct intel_display *display, >> i915_reg_t reg, >> const u8 *data, u32 len) >> { >> @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private *dev_priv, >> for (j = 0; j < min_t(u32, len - i, 4); j++) >> val |= *data++ << 8 * j; >> >> - intel_de_write(dev_priv, reg, val); >> + intel_de_write(display, reg, val); >> } >> } >> >> -static void read_data(struct drm_i915_private *dev_priv, >> +static void read_data(struct intel_display *display, >> i915_reg_t reg, >> u8 *data, u32 len) >> { >> u32 i, j; >> >> for (i = 0; i < len; i += 4) { >> - u32 val = intel_de_read(dev_priv, reg); >> + u32 val = intel_de_read(display, reg); >> >> for (j = 0; j < min_t(u32, len - i, 4); j++) >> *data++ = val >> 8 * j; >> @@ -131,7 +131,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, >> { >> struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); >> struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); >> + struct intel_display *display = to_intel_display(&intel_dsi->base); >> enum port port = intel_dsi_host->port; >> struct mipi_dsi_packet packet; >> ssize_t ret; >> @@ -146,51 +146,51 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, >> header = packet.header; >> >> if (msg->flags & MIPI_DSI_MSG_USE_LPM) { >> - data_reg = MIPI_LP_GEN_DATA(port); >> + data_reg = MIPI_LP_GEN_DATA(display, port); >> data_mask = LP_DATA_FIFO_FULL; >> - ctrl_reg = MIPI_LP_GEN_CTRL(port); >> + ctrl_reg = MIPI_LP_GEN_CTRL(display, port); >> ctrl_mask = LP_CTRL_FIFO_FULL; >> } else { >> - data_reg = MIPI_HS_GEN_DATA(port); >> + data_reg = MIPI_HS_GEN_DATA(display, port); >> data_mask = HS_DATA_FIFO_FULL; >> - ctrl_reg = MIPI_HS_GEN_CTRL(port); >> + ctrl_reg = MIPI_HS_GEN_CTRL(display, port); >> ctrl_mask = HS_CTRL_FIFO_FULL; >> } >> >> /* note: this is never true for reads */ >> if (packet.payload_length) { >> - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), >> + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), >> data_mask, 50)) >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "Timeout waiting for HS/LP DATA FIFO !full\n"); >> >> - write_data(dev_priv, data_reg, packet.payload, >> + write_data(display, data_reg, packet.payload, >> packet.payload_length); >> } >> >> if (msg->rx_len) { >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), >> + intel_de_write(display, MIPI_INTR_STAT(display, port), >> GEN_READ_DATA_AVAIL); >> } >> >> - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), >> + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), >> ctrl_mask, 50)) { >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "Timeout waiting for HS/LP CTRL FIFO !full\n"); >> } >> >> - intel_de_write(dev_priv, ctrl_reg, >> + intel_de_write(display, ctrl_reg, >> header[2] << 16 | header[1] << 8 | header[0]); >> >> /* ->rx_len is set only for reads */ >> if (msg->rx_len) { >> data_mask = GEN_READ_DATA_AVAIL; >> - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), >> + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), >> data_mask, 50)) >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "Timeout waiting for read data.\n"); >> >> - read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); >> + read_data(display, data_reg, msg->rx_buf, msg->rx_len); >> } >> >> /* XXX: fix for reads and writes */ >> @@ -223,7 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { >> static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, >> enum port port) >> { >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); >> + struct intel_display *display = to_intel_display(&intel_dsi->base); >> u32 mask; >> >> /* XXX: pipe, hs */ >> @@ -233,18 +233,18 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, >> cmd |= DPI_LP_MODE; >> >> /* clear bit */ >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); >> + intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); >> >> /* XXX: old code skips write if control unchanged */ >> - if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) >> - drm_dbg_kms(&dev_priv->drm, >> + if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) >> + drm_dbg_kms(display->drm, >> "Same special packet %02x twice in a row.\n", cmd); >> >> - intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); >> + intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); >> >> mask = SPL_PKT_SENT_INTERRUPT; >> - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) >> - drm_err(&dev_priv->drm, >> + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) >> + drm_err(display->drm, >> "Video mode command 0x%08x send failed.\n", cmd); >> >> return 0; >> @@ -324,7 +324,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, >> >> static bool glk_dsi_enable_io(struct intel_encoder *encoder) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> bool cold_boot = false; >> @@ -334,29 +334,30 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) >> * Power ON MIPI IO first and then write into IO reset and LP wake bits >> */ >> for_each_dsi_port(port, intel_dsi->ports) >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); >> + intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); >> >> /* Put the IO into reset */ >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); >> >> /* Program LP Wake */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), >> + u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); >> + >> + intel_de_rmw(display, MIPI_CTRL(display, port), >> GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); >> } >> >> /* Wait for Pwr ACK */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), >> GLK_MIPIIO_PORT_POWERED, 20)) >> - drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); >> + drm_err(display->drm, "MIPIO port is powergated\n"); >> } >> >> /* Check for cold boot scenario */ >> for_each_dsi_port(port, intel_dsi->ports) { >> cold_boot |= >> - !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); >> + !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); >> } >> >> return cold_boot; >> @@ -364,99 +365,100 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) >> >> static void glk_dsi_device_ready(struct intel_encoder *encoder) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> /* Wait for MIPI PHY status bit to set */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), >> GLK_PHY_STATUS_PORT_READY, 20)) >> - drm_err(&dev_priv->drm, "PHY is not ON\n"); >> + drm_err(display->drm, "PHY is not ON\n"); >> } >> >> /* Get IO out of reset */ >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); >> >> /* Get IO out of Low power state*/ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), >> + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_MASK, DEVICE_READY); >> usleep_range(10, 15); >> } else { >> /* Enter ULPS */ >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); >> >> /* Wait for ULPS active */ >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), >> GLK_ULPS_NOT_ACTIVE, 20)) >> - drm_err(&dev_priv->drm, "ULPS not active\n"); >> + drm_err(display->drm, "ULPS not active\n"); >> >> /* Exit ULPS */ >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); >> >> /* Enter Normal Mode */ >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_MASK, >> ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); >> >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); >> + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); >> } >> } >> >> /* Wait for Stop state */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), >> GLK_DATA_LANE_STOP_STATE, 20)) >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "Date lane not in STOP state\n"); >> } >> >> /* Wait for AFE LATCH */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), >> + if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), >> AFE_LATCHOUT, 20)) >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "D-PHY not entering LP-11 state\n"); >> } >> } >> >> static void bxt_dsi_device_ready(struct intel_encoder *encoder) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> u32 val; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> >> /* Enable MIPI PHY transparent latch */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); >> + intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); >> usleep_range(2000, 2500); >> } >> >> /* Clear ULPS and set device ready */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); >> + val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); >> val &= ~ULPS_STATE_MASK; >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); >> usleep_range(2000, 2500); >> val |= DEVICE_READY; >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); >> } >> } >> >> static void vlv_dsi_device_ready(struct intel_encoder *encoder) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> >> vlv_flisdsi_get(dev_priv); >> /* program rcomp for compliance, reduce from 50 ohms to 45 ohms >> @@ -469,7 +471,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) >> >> for_each_dsi_port(port, intel_dsi->ports) { >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_ENTER); >> usleep_range(2500, 3000); >> >> @@ -477,14 +479,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) >> * Common bit for both MIPI Port A & MIPI Port C >> * No similar bit in MIPI Port C reg >> */ >> - intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); >> + intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); >> usleep_range(1000, 1500); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_EXIT); >> usleep_range(2500, 3000); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> DEVICE_READY); >> usleep_range(2500, 3000); >> } >> @@ -504,50 +506,50 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> /* Enter ULPS */ >> for_each_dsi_port(port, intel_dsi->ports) >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), >> ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); >> >> /* Wait for MIPI PHY status bit to unset */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), >> GLK_PHY_STATUS_PORT_READY, 20)) >> - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); >> + drm_err(display->drm, "PHY is not turning OFF\n"); >> } >> >> /* Wait for Pwr ACK bit to unset */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), >> GLK_MIPIIO_PORT_POWERED, 20)) >> - drm_err(&dev_priv->drm, >> + drm_err(display->drm, >> "MIPI IO Port is not powergated\n"); >> } >> } >> >> static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> /* Put the IO into reset */ >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); >> >> /* Wait for MIPI PHY status bit to unset */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), >> GLK_PHY_STATUS_PORT_READY, 20)) >> - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); >> + drm_err(display->drm, "PHY is not turning OFF\n"); >> } >> >> /* Clear MIPI mode */ >> for_each_dsi_port(port, intel_dsi->ports) >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); >> + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); >> } >> >> static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) >> @@ -564,25 +566,26 @@ static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) >> >> static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> for_each_dsi_port(port, intel_dsi->ports) { >> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ >> i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? >> BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> DEVICE_READY | ULPS_STATE_ENTER); >> usleep_range(2000, 2500); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> DEVICE_READY | ULPS_STATE_EXIT); >> usleep_range(2000, 2500); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), >> DEVICE_READY | ULPS_STATE_ENTER); >> usleep_range(2000, 2500); >> >> @@ -591,15 +594,15 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) >> * Port A only. MIPI Port C has no similar bit for checking. >> */ >> if ((IS_BROXTON(dev_priv) || port == PORT_A) && >> - intel_de_wait_for_clear(dev_priv, port_ctrl, >> + intel_de_wait_for_clear(display, port_ctrl, >> AFE_LATCHOUT, 30)) >> - drm_err(&dev_priv->drm, "DSI LP not going Low\n"); >> + drm_err(display->drm, "DSI LP not going Low\n"); >> >> /* Disable MIPI PHY transparent latch */ >> - intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); >> + intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); >> usleep_range(1000, 1500); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); >> usleep_range(2000, 2500); >> } >> } >> @@ -607,6 +610,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) >> static void intel_dsi_port_enable(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> @@ -617,11 +621,11 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, >> >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { >> for_each_dsi_port(port, intel_dsi->ports) >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), >> + intel_de_rmw(display, MIPI_CTRL(display, port), >> BXT_PIXEL_OVERLAP_CNT_MASK, >> temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); >> } else { >> - intel_de_rmw(dev_priv, VLV_CHICKEN_3, >> + intel_de_rmw(display, VLV_CHICKEN_3, >> PIXEL_OVERLAP_CNT_MASK, >> temp << PIXEL_OVERLAP_CNT_SHIFT); >> } >> @@ -631,7 +635,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); >> u32 temp; >> >> - temp = intel_de_read(dev_priv, port_ctrl); >> + temp = intel_de_read(display, port_ctrl); >> >> temp &= ~LANE_CONFIGURATION_MASK; >> temp &= ~DUAL_LINK_MODE_MASK; >> @@ -651,13 +655,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, >> temp |= DITHERING_ENABLE; >> >> /* assert ip_tg_enable signal */ >> - intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); >> - intel_de_posting_read(dev_priv, port_ctrl); >> + intel_de_write(display, port_ctrl, temp | DPI_ENABLE); >> + intel_de_posting_read(display, port_ctrl); >> } >> } >> >> static void intel_dsi_port_disable(struct intel_encoder *encoder) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> @@ -666,8 +671,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); >> >> /* de-assert ip_tg_enable signal */ >> - intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); >> - intel_de_posting_read(dev_priv, port_ctrl); >> + intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); >> + intel_de_posting_read(display, port_ctrl); >> } >> } >> >> @@ -721,6 +726,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, >> const struct intel_crtc_state *pipe_config, >> const struct drm_connector_state *conn_state) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> @@ -728,7 +734,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, >> enum port port; >> bool glk_cold_boot = false; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> >> intel_dsi_wait_panel_power_cycle(intel_dsi); >> >> @@ -748,16 +754,16 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, >> >> if (IS_BROXTON(dev_priv)) { >> /* Add MIPI IO reset programming for modeset */ >> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); >> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); >> >> /* Power up DSI regulator */ >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); >> + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); >> + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); >> } >> >> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { >> /* Disable DPOunit clock gating, can stall pipe */ >> - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), >> + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), >> 0, DPOUNIT_CLOCK_GATE_DISABLE); >> } >> >> @@ -793,8 +799,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, >> */ >> if (is_cmd_mode(intel_dsi)) { >> for_each_dsi_port(port, intel_dsi->ports) >> - intel_de_write(dev_priv, >> - MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); >> + intel_de_write(display, >> + MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); >> } else { >> @@ -866,11 +872,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, >> const struct intel_crtc_state *old_crtc_state, >> const struct drm_connector_state *old_conn_state) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { >> intel_crtc_vblank_off(old_crtc_state); >> @@ -901,12 +908,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, >> >> if (IS_BROXTON(dev_priv)) { >> /* Power down DSI regulator to save power */ >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, >> + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); >> + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, >> HS_IO_CTRL_SELECT); >> >> /* Add MIPI IO reset programming for modeset */ >> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); >> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); >> } >> >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { >> @@ -914,7 +921,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, >> } else { >> vlv_dsi_pll_disable(encoder); >> >> - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), >> + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), >> DPOUNIT_CLOCK_GATE_DISABLE, 0); >> } >> >> @@ -930,13 +937,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, >> static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, >> enum pipe *pipe) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> intel_wakeref_t wakeref; >> enum port port; >> bool active = false; >> >> - drm_dbg_kms(&dev_priv->drm, "\n"); >> + drm_dbg_kms(display->drm, "\n"); >> >> wakeref = intel_display_power_get_if_enabled(dev_priv, >> encoder->power_domain); >> @@ -955,7 +963,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, >> /* XXX: this only works for one DSI output */ >> for_each_dsi_port(port, intel_dsi->ports) { >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); >> - bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; >> + bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; >> >> /* >> * Due to some hardware limitations on VLV/CHV, the DPI enable >> @@ -964,27 +972,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, >> */ >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && >> port == PORT_C) >> - enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; >> + enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; >> >> /* Try command mode if video mode not enabled */ >> if (!enabled) { >> - u32 tmp = intel_de_read(dev_priv, >> - MIPI_DSI_FUNC_PRG(port)); >> + u32 tmp = intel_de_read(display, >> + MIPI_DSI_FUNC_PRG(display, port)); >> enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; >> } >> >> if (!enabled) >> continue; >> >> - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) >> + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) >> continue; >> >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { >> - u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); >> + u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); >> tmp &= BXT_PIPE_SELECT_MASK; >> tmp >>= BXT_PIPE_SELECT_SHIFT; >> >> - if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) >> + if (drm_WARN_ON(display->drm, tmp > PIPE_C)) >> continue; >> >> *pipe = tmp; >> @@ -1005,7 +1013,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, >> static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, >> struct intel_crtc_state *pipe_config) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_display_mode *adjusted_mode = >> &pipe_config->hw.adjusted_mode; >> struct drm_display_mode *adjusted_mode_sw; >> @@ -1027,11 +1035,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, >> * encoder->get_hw_state() returns true. >> */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) >> + if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) >> break; >> } >> >> - fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; >> + fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; >> bpp = mipi_dsi_pixel_format_to_bpp( >> pixel_format_from_register_bits(fmt)); >> >> @@ -1043,24 +1051,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, >> >> /* In terms of pixels */ >> adjusted_mode->crtc_hdisplay = >> - intel_de_read(dev_priv, >> + intel_de_read(display, >> BXT_MIPI_TRANS_HACTIVE(port)); >> adjusted_mode->crtc_vdisplay = >> - intel_de_read(dev_priv, >> + intel_de_read(display, >> BXT_MIPI_TRANS_VACTIVE(port)); >> adjusted_mode->crtc_vtotal = >> - intel_de_read(dev_priv, >> + intel_de_read(display, >> BXT_MIPI_TRANS_VTOTAL(port)); >> >> hactive = adjusted_mode->crtc_hdisplay; >> - hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); >> + hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); >> >> /* >> * Meaningful for video mode non-burst sync pulse mode only, >> * can be zero for non-burst sync events and burst modes >> */ >> - hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); >> - hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); >> + hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); >> + hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); >> >> /* harizontal values are in terms of high speed byte clock */ >> hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, >> @@ -1077,8 +1085,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, >> } >> >> /* vertical values are in terms of lines */ >> - vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); >> - vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); >> + vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); >> + vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); >> >> adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; >> adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; >> @@ -1207,6 +1215,7 @@ static u16 txclkesc(u32 divider, unsigned int us) >> static void set_dsi_timings(struct intel_encoder *encoder, >> const struct drm_display_mode *adjusted_mode) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> @@ -1249,29 +1258,29 @@ static void set_dsi_timings(struct intel_encoder *encoder, >> * vactive, as they are calculated per channel basis, >> * whereas these values should be based on resolution. >> */ >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), >> + intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), >> adjusted_mode->crtc_hdisplay); >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), >> + intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), >> adjusted_mode->crtc_vdisplay); >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), >> + intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), >> adjusted_mode->crtc_vtotal); >> } >> >> - intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), >> + intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), >> hactive); >> - intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); >> + intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); >> >> /* meaningful for video mode non-burst sync pulse mode only, >> * can be zero for non-burst sync events and burst modes */ >> - intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), >> + intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), >> hsync); >> - intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); >> + intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); >> >> /* vertical values are in terms of lines */ >> - intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); >> - intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), >> + intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); >> + intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), >> vsync); >> - intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); >> + intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); >> } >> } >> >> @@ -1295,6 +1304,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) >> static void intel_dsi_prepare(struct intel_encoder *encoder, >> const struct intel_crtc_state *pipe_config) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> @@ -1304,7 +1314,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> u32 val, tmp; >> u16 mode_hdisplay; >> >> - drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); >> + drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); >> >> mode_hdisplay = adjusted_mode->crtc_hdisplay; >> >> @@ -1320,31 +1330,31 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> * escape clock divider, 20MHz, shared for A and C. >> * device ready must be off when doing this! txclkesc? >> */ >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); >> + tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); >> tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; >> - intel_de_write(dev_priv, MIPI_CTRL(PORT_A), >> + intel_de_write(display, MIPI_CTRL(display, PORT_A), >> tmp | ESCAPE_CLOCK_DIVIDER_1); >> >> /* read request priority is per pipe */ >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); >> + tmp = intel_de_read(display, MIPI_CTRL(display, port)); >> tmp &= ~READ_REQUEST_PRIORITY_MASK; >> - intel_de_write(dev_priv, MIPI_CTRL(port), >> + intel_de_write(display, MIPI_CTRL(display, port), >> tmp | READ_REQUEST_PRIORITY_HIGH); >> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { >> enum pipe pipe = crtc->pipe; >> >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), >> + intel_de_rmw(display, MIPI_CTRL(display, port), >> BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); >> } >> >> /* XXX: why here, why like this? handling in irq handler?! */ >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); >> - intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); >> + intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); >> + intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); >> >> - intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), >> + intel_de_write(display, MIPI_DPHY_PARAM(display, port), >> intel_dsi->dphy_reg); >> >> - intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), >> + intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), >> adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); >> } >> >> @@ -1372,7 +1382,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> } >> >> for_each_dsi_port(port, intel_dsi->ports) { >> - intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); >> + intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); >> >> /* timeouts for recovery. one frame IIUC. if counter expires, >> * EOT and stop state. */ >> @@ -1393,23 +1403,23 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> >> if (is_vid_mode(intel_dsi) && >> intel_dsi->video_mode == BURST_MODE) { >> - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), >> + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), >> txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); >> } else { >> - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), >> + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), >> txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); >> } >> - intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), >> + intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), >> intel_dsi->lp_rx_timeout); >> - intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), >> + intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), >> intel_dsi->turn_arnd_val); >> - intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), >> + intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), >> intel_dsi->rst_timer_val); >> >> /* dphy stuff */ >> >> /* in terms of low power clock */ >> - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), >> + intel_de_write(display, MIPI_INIT_COUNT(display, port), >> txclkesc(intel_dsi->escape_clk_div, 100)); >> >> if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && >> @@ -1420,16 +1430,16 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> * getting used. So write the other port >> * if not in dual link mode. >> */ >> - intel_de_write(dev_priv, >> - MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), >> + intel_de_write(display, >> + MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), >> intel_dsi->init_count); >> } >> >> /* recovery disables */ >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); >> >> /* in terms of low power clock */ >> - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), >> + intel_de_write(display, MIPI_INIT_COUNT(display, port), >> intel_dsi->init_count); >> >> /* in terms of txbyteclkhs. actual high to low switch + >> @@ -1437,7 +1447,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> * >> * XXX: write MIPI_STOP_STATE_STALL? >> */ >> - intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), >> + intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), >> intel_dsi->hs_to_lp_count); >> >> /* XXX: low power clock equivalence in terms of byte clock. >> @@ -1446,14 +1456,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL >> * ) / 105.??? >> */ >> - intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), >> + intel_de_write(display, MIPI_LP_BYTECLK(display, port), >> intel_dsi->lp_byte_clk); >> >> if (IS_GEMINILAKE(dev_priv)) { >> - intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), >> + intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), >> intel_dsi->lp_byte_clk); >> /* Shadow of DPHY reg */ >> - intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), >> + intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), >> intel_dsi->dphy_reg); >> } >> >> @@ -1462,10 +1472,10 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> * this register in terms of byte clocks. based on dsi transfer >> * rate and the number of lanes configured the time taken to >> * transmit 16 long packets in a dsi stream varies. */ >> - intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), >> + intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), >> intel_dsi->bw_timer); >> >> - intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), >> + intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), >> intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); >> >> if (is_vid_mode(intel_dsi)) { >> @@ -1493,13 +1503,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, >> break; >> } >> >> - intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); >> + intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); >> } >> } >> } >> >> static void intel_dsi_unprepare(struct intel_encoder *encoder) >> { >> + struct intel_display *display = to_intel_display(encoder); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> enum port port; >> @@ -1509,17 +1520,17 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) >> >> for_each_dsi_port(port, intel_dsi->ports) { >> /* Panel commands can be sent when clock is in LP11 */ >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); >> >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) >> bxt_dsi_reset_clocks(encoder, port); >> else >> vlv_dsi_reset_clocks(encoder, port); >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); >> >> - intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); >> + intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); >> >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); >> } >> } >> >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c >> index ae0a0b11bae3..70c5a13a3c75 100644 >> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c >> @@ -365,13 +365,13 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, >> >> void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) >> { >> - u32 temp; >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + struct intel_display *display = to_intel_display(encoder); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); >> + u32 temp; >> >> - temp = intel_de_read(dev_priv, MIPI_CTRL(port)); >> + temp = intel_de_read(display, MIPI_CTRL(display, port)); >> temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; >> - intel_de_write(dev_priv, MIPI_CTRL(port), >> + intel_de_write(display, MIPI_CTRL(display, port), >> temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); >> } >> >> @@ -570,24 +570,24 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, >> >> void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) >> { >> + struct intel_display *display = to_intel_display(encoder); >> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> u32 tmp; >> - struct drm_device *dev = encoder->base.dev; >> - struct drm_i915_private *dev_priv = to_i915(dev); >> >> /* Clear old configurations */ >> if (IS_BROXTON(dev_priv)) { >> - tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); >> + tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); >> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); >> tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); >> tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); >> tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); >> - intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); >> + intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); >> } else { >> - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); >> + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); >> >> - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); >> + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); >> } >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); >> } >> >> static void assert_dsi_pll(struct drm_i915_private *i915, bool state) >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> index 12a608a73720..c1126d170ec6 100644 >> --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h >> @@ -11,26 +11,23 @@ >> #define VLV_MIPI_BASE VLV_DISPLAY_BASE >> #define BXT_MIPI_BASE 0x60000 >> >> -#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) >> +#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) >> >> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ >> -#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) >> +#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) >> >> /* BXT MIPI mode configure */ >> -#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 >> -#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 >> -#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ >> - _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) >> +#define _BXT_MIPIA_TRANS_HACTIVE 0xb0f8 >> +#define _BXT_MIPIC_TRANS_HACTIVE 0xb8f8 >> +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) >> >> -#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC >> -#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC >> -#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ >> - _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) >> +#define _BXT_MIPIA_TRANS_VACTIVE 0xb0fc >> +#define _BXT_MIPIC_TRANS_VACTIVE 0xb8fc >> +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) >> >> -#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 >> -#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 >> -#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ >> - _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) >> +#define _BXT_MIPIA_TRANS_VTOTAL 0xb100 >> +#define _BXT_MIPIC_TRANS_VTOTAL 0xb900 >> +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) >> >> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) >> #define STAP_SELECT (1 << 0) >> @@ -38,14 +35,14 @@ >> #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) >> #define HS_IO_CTRL_SELECT (1 << 0) >> >> -#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) >> -#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) >> -#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) >> +#define _MIPIA_PORT_CTRL 0x61190 >> +#define _MIPIC_PORT_CTRL 0x61700 >> +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) >> >> /* BXT port control */ >> -#define _BXT_MIPIA_PORT_CTRL 0x6B0C0 >> -#define _BXT_MIPIC_PORT_CTRL 0x6B8C0 >> -#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) >> +#define _BXT_MIPIA_PORT_CTRL 0xb0c0 >> +#define _BXT_MIPIC_PORT_CTRL 0xb8c0 >> +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) >> >> #define DPI_ENABLE (1 << 31) /* A + C */ >> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 >> @@ -87,17 +84,17 @@ >> #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) >> #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) >> >> -#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) >> -#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) >> -#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) >> +#define _MIPIA_TEARING_CTRL 0x61194 >> +#define _MIPIC_TEARING_CTRL 0x61704 >> +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) >> #define TEARING_EFFECT_DELAY_SHIFT 0 >> #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) >> >> /* MIPI DSI Controller and D-PHY registers */ >> >> -#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) >> -#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) >> -#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) >> +#define _MIPIA_DEVICE_READY 0xb000 >> +#define _MIPIC_DEVICE_READY 0xb800 >> +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) >> #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ >> #define ULPS_STATE_MASK (3 << 1) >> #define ULPS_STATE_ENTER (2 << 1) >> @@ -105,12 +102,12 @@ >> #define ULPS_STATE_NORMAL_OPERATION (0 << 1) >> #define DEVICE_READY (1 << 0) >> >> -#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) >> -#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) >> -#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) >> -#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) >> -#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) >> -#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) >> +#define _MIPIA_INTR_STAT 0xb004 >> +#define _MIPIC_INTR_STAT 0xb804 >> +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) >> +#define _MIPIA_INTR_EN 0xb008 >> +#define _MIPIC_INTR_EN 0xb808 >> +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) >> #define TEARING_EFFECT (1 << 31) >> #define SPL_PKT_SENT_INTERRUPT (1 << 30) >> #define GEN_READ_DATA_AVAIL (1 << 29) >> @@ -144,9 +141,9 @@ >> #define RXSOT_SYNC_ERROR (1 << 1) >> #define RXSOT_ERROR (1 << 0) >> >> -#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) >> -#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) >> -#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) >> +#define _MIPIA_DSI_FUNC_PRG 0xb00c >> +#define _MIPIC_DSI_FUNC_PRG 0xb80c >> +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) >> #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) >> #define CMD_MODE_NOT_SUPPORTED (0 << 13) >> #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) >> @@ -167,77 +164,77 @@ >> #define DATA_LANES_PRG_REG_SHIFT 0 >> #define DATA_LANES_PRG_REG_MASK (7 << 0) >> >> -#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) >> -#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) >> -#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) >> +#define _MIPIA_HS_TX_TIMEOUT 0xb010 >> +#define _MIPIC_HS_TX_TIMEOUT 0xb810 >> +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) >> #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff >> >> -#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) >> -#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) >> -#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) >> +#define _MIPIA_LP_RX_TIMEOUT 0xb014 >> +#define _MIPIC_LP_RX_TIMEOUT 0xb814 >> +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) >> #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff >> >> -#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) >> -#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) >> -#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) >> +#define _MIPIA_TURN_AROUND_TIMEOUT 0xb018 >> +#define _MIPIC_TURN_AROUND_TIMEOUT 0xb818 >> +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) >> #define TURN_AROUND_TIMEOUT_MASK 0x3f >> >> -#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) >> -#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) >> -#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) >> +#define _MIPIA_DEVICE_RESET_TIMER 0xb01c >> +#define _MIPIC_DEVICE_RESET_TIMER 0xb81c >> +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) >> #define DEVICE_RESET_TIMER_MASK 0xffff >> >> -#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) >> -#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) >> -#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) >> +#define _MIPIA_DPI_RESOLUTION 0xb020 >> +#define _MIPIC_DPI_RESOLUTION 0xb820 >> +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) >> #define VERTICAL_ADDRESS_SHIFT 16 >> #define VERTICAL_ADDRESS_MASK (0xffff << 16) >> #define HORIZONTAL_ADDRESS_SHIFT 0 >> #define HORIZONTAL_ADDRESS_MASK 0xffff >> >> -#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) >> -#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) >> -#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) >> +#define _MIPIA_DBI_FIFO_THROTTLE 0xb024 >> +#define _MIPIC_DBI_FIFO_THROTTLE 0xb824 >> +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) >> #define DBI_FIFO_EMPTY_HALF (0 << 0) >> #define DBI_FIFO_EMPTY_QUARTER (1 << 0) >> #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) >> >> /* regs below are bits 15:0 */ >> -#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) >> -#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) >> -#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) >> +#define _MIPIA_HSYNC_PADDING_COUNT 0xb028 >> +#define _MIPIC_HSYNC_PADDING_COUNT 0xb828 >> +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) >> >> -#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) >> -#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) >> -#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) >> +#define _MIPIA_HBP_COUNT 0xb02c >> +#define _MIPIC_HBP_COUNT 0xb82c >> +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) >> >> -#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) >> -#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) >> -#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) >> +#define _MIPIA_HFP_COUNT 0xb030 >> +#define _MIPIC_HFP_COUNT 0xb830 >> +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) >> >> -#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) >> -#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) >> -#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) >> +#define _MIPIA_HACTIVE_AREA_COUNT 0xb034 >> +#define _MIPIC_HACTIVE_AREA_COUNT 0xb834 >> +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) >> >> -#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) >> -#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) >> -#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) >> +#define _MIPIA_VSYNC_PADDING_COUNT 0xb038 >> +#define _MIPIC_VSYNC_PADDING_COUNT 0xb838 >> +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) >> >> -#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) >> -#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) >> -#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) >> +#define _MIPIA_VBP_COUNT 0xb03c >> +#define _MIPIC_VBP_COUNT 0xb83c >> +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) >> >> -#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) >> -#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) >> -#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) >> +#define _MIPIA_VFP_COUNT 0xb040 >> +#define _MIPIC_VFP_COUNT 0xb840 >> +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) >> >> -#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) >> -#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) >> -#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) >> +#define _MIPIA_HIGH_LOW_SWITCH_COUNT 0xb044 >> +#define _MIPIC_HIGH_LOW_SWITCH_COUNT 0xb844 >> +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) >> >> -#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) >> -#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) >> -#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) >> +#define _MIPIA_DPI_CONTROL 0xb048 >> +#define _MIPIC_DPI_CONTROL 0xb848 >> +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) >> #define DPI_LP_MODE (1 << 6) >> #define BACKLIGHT_OFF (1 << 5) >> #define BACKLIGHT_ON (1 << 4) >> @@ -246,28 +243,27 @@ >> #define TURN_ON (1 << 1) >> #define SHUTDOWN (1 << 0) >> >> -#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) >> -#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) >> -#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) >> +#define _MIPIA_DPI_DATA 0xb04c >> +#define _MIPIC_DPI_DATA 0xb84c >> +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) >> #define COMMAND_BYTE_SHIFT 0 >> #define COMMAND_BYTE_MASK (0x3f << 0) >> >> -#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) >> -#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) >> -#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) >> +#define _MIPIA_INIT_COUNT 0xb050 >> +#define _MIPIC_INIT_COUNT 0xb850 >> +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) >> #define MASTER_INIT_TIMER_SHIFT 0 >> #define MASTER_INIT_TIMER_MASK (0xffff << 0) >> >> -#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) >> -#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) >> -#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ >> - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) >> +#define _MIPIA_MAX_RETURN_PKT_SIZE 0xb054 >> +#define _MIPIC_MAX_RETURN_PKT_SIZE 0xb854 >> +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) >> #define MAX_RETURN_PKT_SIZE_SHIFT 0 >> #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) >> >> -#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) >> -#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) >> -#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) >> +#define _MIPIA_VIDEO_MODE_FORMAT 0xb058 >> +#define _MIPIC_VIDEO_MODE_FORMAT 0xb858 >> +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) >> #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) >> #define DISABLE_VIDEO_BTA (1 << 3) >> #define IP_TG_CONFIG (1 << 2) >> @@ -275,9 +271,9 @@ >> #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) >> #define VIDEO_MODE_BURST (3 << 0) >> >> -#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) >> -#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) >> -#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) >> +#define _MIPIA_EOT_DISABLE 0xb05c >> +#define _MIPIC_EOT_DISABLE 0xb85c >> +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) >> #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) >> #define BXT_DPHY_DEFEATURE_EN (1 << 8) >> #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) >> @@ -289,36 +285,36 @@ >> #define CLOCKSTOP (1 << 1) >> #define EOT_DISABLE (1 << 0) >> >> -#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) >> -#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) >> -#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) >> +#define _MIPIA_LP_BYTECLK 0xb060 >> +#define _MIPIC_LP_BYTECLK 0xb860 >> +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) >> #define LP_BYTECLK_SHIFT 0 >> #define LP_BYTECLK_MASK (0xffff << 0) >> >> -#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) >> -#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) >> -#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) >> +#define _MIPIA_TLPX_TIME_COUNT 0xb0a4 >> +#define _MIPIC_TLPX_TIME_COUNT 0xb8a4 >> +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) >> >> -#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) >> -#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) >> -#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) >> +#define _MIPIA_CLK_LANE_TIMING 0xb098 >> +#define _MIPIC_CLK_LANE_TIMING 0xb898 >> +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) >> >> /* bits 31:0 */ >> -#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) >> -#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) >> -#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) >> +#define _MIPIA_LP_GEN_DATA 0xb064 >> +#define _MIPIC_LP_GEN_DATA 0xb864 >> +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) >> >> /* bits 31:0 */ >> -#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) >> -#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) >> -#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) >> - >> -#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) >> -#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) >> -#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) >> -#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) >> -#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) >> -#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) >> +#define _MIPIA_HS_GEN_DATA 0xb068 >> +#define _MIPIC_HS_GEN_DATA 0xb868 >> +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) >> + >> +#define _MIPIA_LP_GEN_CTRL 0xb06c >> +#define _MIPIC_LP_GEN_CTRL 0xb86c >> +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) >> +#define _MIPIA_HS_GEN_CTRL 0xb070 >> +#define _MIPIC_HS_GEN_CTRL 0xb870 >> +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) >> #define LONG_PACKET_WORD_COUNT_SHIFT 8 >> #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) >> #define SHORT_PACKET_PARAM_SHIFT 8 >> @@ -329,9 +325,9 @@ >> #define DATA_TYPE_MASK (0x3f << 0) >> /* data type values, see include/video/mipi_display.h */ >> >> -#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) >> -#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) >> -#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) >> +#define _MIPIA_GEN_FIFO_STAT 0xb074 >> +#define _MIPIC_GEN_FIFO_STAT 0xb874 >> +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) >> #define DPI_FIFO_EMPTY (1 << 28) >> #define DBI_FIFO_EMPTY (1 << 27) >> #define LP_CTRL_FIFO_EMPTY (1 << 26) >> @@ -347,16 +343,16 @@ >> #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) >> #define HS_DATA_FIFO_FULL (1 << 0) >> >> -#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) >> -#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) >> -#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) >> +#define _MIPIA_HS_LS_DBI_ENABLE 0xb078 >> +#define _MIPIC_HS_LS_DBI_ENABLE 0xb878 >> +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) >> #define DBI_HS_LP_MODE_MASK (1 << 0) >> #define DBI_LP_MODE (1 << 0) >> #define DBI_HS_MODE (0 << 0) >> >> -#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) >> -#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) >> -#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) >> +#define _MIPIA_DPHY_PARAM 0xb080 >> +#define _MIPIC_DPHY_PARAM 0xb880 >> +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) >> #define EXIT_ZERO_COUNT_SHIFT 24 >> #define EXIT_ZERO_COUNT_MASK (0x3f << 24) >> #define TRAIL_COUNT_SHIFT 16 >> @@ -366,34 +362,34 @@ >> #define PREPARE_COUNT_SHIFT 0 >> #define PREPARE_COUNT_MASK (0x3f << 0) >> >> -#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) >> -#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) >> -#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) >> +#define _MIPIA_DBI_BW_CTRL 0xb084 >> +#define _MIPIC_DBI_BW_CTRL 0xb884 >> +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) >> >> -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) >> -#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) >> -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) >> +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT 0xb088 >> +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT 0xb888 >> +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) >> #define LP_HS_SSW_CNT_SHIFT 16 >> #define LP_HS_SSW_CNT_MASK (0xffff << 16) >> #define HS_LP_PWR_SW_CNT_SHIFT 0 >> #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) >> >> -#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) >> -#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) >> -#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) >> +#define _MIPIA_STOP_STATE_STALL 0xb08c >> +#define _MIPIC_STOP_STATE_STALL 0xb88c >> +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) >> #define STOP_STATE_STALL_COUNTER_SHIFT 0 >> #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) >> >> -#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) >> -#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) >> -#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) >> -#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) >> -#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) >> -#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) >> +#define _MIPIA_INTR_STAT_REG_1 0xb090 >> +#define _MIPIC_INTR_STAT_REG_1 0xb890 >> +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) >> +#define _MIPIA_INTR_EN_REG_1 0xb094 >> +#define _MIPIC_INTR_EN_REG_1 0xb894 >> +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) >> #define RX_CONTENTION_DETECTED (1 << 0) >> >> /* XXX: only pipe A ?!? */ >> -#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) >> +#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) >> #define DBI_TYPEC_ENABLE (1 << 31) >> #define DBI_TYPEC_WIP (1 << 30) >> #define DBI_TYPEC_OPTION_SHIFT 28 >> @@ -406,9 +402,9 @@ >> >> /* MIPI adapter registers */ >> >> -#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) >> -#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) >> -#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) >> +#define _MIPIA_CTRL 0xb104 >> +#define _MIPIC_CTRL 0xb904 >> +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) >> #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ >> #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) >> #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) >> @@ -439,41 +435,41 @@ >> #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ >> #define GLK_MIPIIO_ENABLE (1 << 0) >> >> -#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) >> -#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) >> -#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) >> +#define _MIPIA_DATA_ADDRESS 0xb108 >> +#define _MIPIC_DATA_ADDRESS 0xb908 >> +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) >> #define DATA_MEM_ADDRESS_SHIFT 5 >> #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) >> #define DATA_VALID (1 << 0) >> >> -#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) >> -#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) >> -#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) >> +#define _MIPIA_DATA_LENGTH 0xb10c >> +#define _MIPIC_DATA_LENGTH 0xb90c >> +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) >> #define DATA_LENGTH_SHIFT 0 >> #define DATA_LENGTH_MASK (0xfffff << 0) >> >> -#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) >> -#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) >> -#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) >> +#define _MIPIA_COMMAND_ADDRESS 0xb110 >> +#define _MIPIC_COMMAND_ADDRESS 0xb910 >> +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) >> #define COMMAND_MEM_ADDRESS_SHIFT 5 >> #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) >> #define AUTO_PWG_ENABLE (1 << 2) >> #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) >> #define COMMAND_VALID (1 << 0) >> >> -#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) >> -#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) >> -#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) >> +#define _MIPIA_COMMAND_LENGTH 0xb114 >> +#define _MIPIC_COMMAND_LENGTH 0xb914 >> +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) >> #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ >> #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) >> >> -#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) >> -#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) >> -#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ >> +#define _MIPIA_READ_DATA_RETURN0 0xb118 >> +#define _MIPIC_READ_DATA_RETURN0 0xb918 >> +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ >> >> -#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) >> -#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) >> -#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) >> +#define _MIPIA_READ_DATA_VALID 0xb138 >> +#define _MIPIC_READ_DATA_VALID 0xb938 >> +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) >> #define READ_DATA_VALID(n) (1 << (n)) >> >> #endif /* __VLV_DSI_REGS_H__ */ >> -- >> 2.39.2 >> ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable 2024-04-22 21:16 ` Gustavo Sousa @ 2024-04-22 21:21 ` Rodrigo Vivi 0 siblings, 0 replies; 18+ messages in thread From: Rodrigo Vivi @ 2024-04-22 21:21 UTC (permalink / raw) To: Gustavo Sousa; +Cc: Jani Nikula, intel-gfx On Mon, Apr 22, 2024 at 06:16:59PM -0300, Gustavo Sousa wrote: > Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00) > >On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote: > >> Stop relying on the dev_priv local variable in the DSI register > >> macros. Pass struct intel_display pointer to the macros. Move the MIPI > >> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI() > >> and doing the addition there. > >> > >> Start using the local display variable for all intel_de_* usage, and > >> opportunistically use it for other things than display registers as > >> well. > >> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >> > >> --- > >> > >> Tip: Applying the patch and using 'git show --color-words' is probably > >> the easiest way to review. > > > >wow! this is indeed a nice feature for this case. I had never tried it before. > >Thanks for showing that. > > > >But the registers changes were easier to review the old way. ;) > > What about --word-diff for those? :-) this is overall better indeed! Thanks although for the registers the full context was more clear... but maybe it is just a matter of getting used to it... nowadays with the b4 in place these small/smart diffs might help the reviews Thank you so much > > -- > Gustavo Sousa > > > > >Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > >> --- > >> drivers/gpu/drm/i915/display/intel_display.c | 8 +- > >> drivers/gpu/drm/i915/display/vlv_dsi.c | 337 ++++++++++--------- > >> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +- > >> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 324 +++++++++--------- > >> 4 files changed, 349 insertions(+), 342 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > >> index 96ed1490fec7..b9434465d3a7 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_display.c > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c > >> @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, > >> struct intel_crtc_state *pipe_config, > >> struct intel_display_power_domain_set *power_domain_set) > >> { > >> - struct drm_device *dev = crtc->base.dev; > >> - struct drm_i915_private *dev_priv = to_i915(dev); > >> + struct intel_display *display = to_intel_display(crtc); > >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > >> enum transcoder cpu_transcoder; > >> enum port port; > >> u32 tmp; > >> @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, > >> break; > >> > >> /* XXX: this works for video mode only */ > >> - tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); > >> + tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); > >> if (!(tmp & DPI_ENABLE)) > >> continue; > >> > >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > >> + tmp = intel_de_read(display, MIPI_CTRL(display, port)); > >> if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) > >> continue; > >> > >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c > >> index 9967ef58f1ec..ee9923c7b115 100644 > >> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c > >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c > >> @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) > >> > >> void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > >> + struct intel_display *display = to_intel_display(&intel_dsi->base); > >> u32 mask; > >> > >> mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > >> LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; > >> > >> - if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), > >> + if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), > >> mask, 100)) > >> - drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); > >> + drm_err(display->drm, "DPI FIFOs are not empty\n"); > >> } > >> > >> -static void write_data(struct drm_i915_private *dev_priv, > >> +static void write_data(struct intel_display *display, > >> i915_reg_t reg, > >> const u8 *data, u32 len) > >> { > >> @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private *dev_priv, > >> for (j = 0; j < min_t(u32, len - i, 4); j++) > >> val |= *data++ << 8 * j; > >> > >> - intel_de_write(dev_priv, reg, val); > >> + intel_de_write(display, reg, val); > >> } > >> } > >> > >> -static void read_data(struct drm_i915_private *dev_priv, > >> +static void read_data(struct intel_display *display, > >> i915_reg_t reg, > >> u8 *data, u32 len) > >> { > >> u32 i, j; > >> > >> for (i = 0; i < len; i += 4) { > >> - u32 val = intel_de_read(dev_priv, reg); > >> + u32 val = intel_de_read(display, reg); > >> > >> for (j = 0; j < min_t(u32, len - i, 4); j++) > >> *data++ = val >> 8 * j; > >> @@ -131,7 +131,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, > >> { > >> struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); > >> struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; > >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > >> + struct intel_display *display = to_intel_display(&intel_dsi->base); > >> enum port port = intel_dsi_host->port; > >> struct mipi_dsi_packet packet; > >> ssize_t ret; > >> @@ -146,51 +146,51 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, > >> header = packet.header; > >> > >> if (msg->flags & MIPI_DSI_MSG_USE_LPM) { > >> - data_reg = MIPI_LP_GEN_DATA(port); > >> + data_reg = MIPI_LP_GEN_DATA(display, port); > >> data_mask = LP_DATA_FIFO_FULL; > >> - ctrl_reg = MIPI_LP_GEN_CTRL(port); > >> + ctrl_reg = MIPI_LP_GEN_CTRL(display, port); > >> ctrl_mask = LP_CTRL_FIFO_FULL; > >> } else { > >> - data_reg = MIPI_HS_GEN_DATA(port); > >> + data_reg = MIPI_HS_GEN_DATA(display, port); > >> data_mask = HS_DATA_FIFO_FULL; > >> - ctrl_reg = MIPI_HS_GEN_CTRL(port); > >> + ctrl_reg = MIPI_HS_GEN_CTRL(display, port); > >> ctrl_mask = HS_CTRL_FIFO_FULL; > >> } > >> > >> /* note: this is never true for reads */ > >> if (packet.payload_length) { > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), > >> + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), > >> data_mask, 50)) > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "Timeout waiting for HS/LP DATA FIFO !full\n"); > >> > >> - write_data(dev_priv, data_reg, packet.payload, > >> + write_data(display, data_reg, packet.payload, > >> packet.payload_length); > >> } > >> > >> if (msg->rx_len) { > >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), > >> + intel_de_write(display, MIPI_INTR_STAT(display, port), > >> GEN_READ_DATA_AVAIL); > >> } > >> > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), > >> + if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), > >> ctrl_mask, 50)) { > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "Timeout waiting for HS/LP CTRL FIFO !full\n"); > >> } > >> > >> - intel_de_write(dev_priv, ctrl_reg, > >> + intel_de_write(display, ctrl_reg, > >> header[2] << 16 | header[1] << 8 | header[0]); > >> > >> /* ->rx_len is set only for reads */ > >> if (msg->rx_len) { > >> data_mask = GEN_READ_DATA_AVAIL; > >> - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), > >> + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), > >> data_mask, 50)) > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "Timeout waiting for read data.\n"); > >> > >> - read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); > >> + read_data(display, data_reg, msg->rx_buf, msg->rx_len); > >> } > >> > >> /* XXX: fix for reads and writes */ > >> @@ -223,7 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = { > >> static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, > >> enum port port) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); > >> + struct intel_display *display = to_intel_display(&intel_dsi->base); > >> u32 mask; > >> > >> /* XXX: pipe, hs */ > >> @@ -233,18 +233,18 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, > >> cmd |= DPI_LP_MODE; > >> > >> /* clear bit */ > >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); > >> + intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); > >> > >> /* XXX: old code skips write if control unchanged */ > >> - if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) > >> - drm_dbg_kms(&dev_priv->drm, > >> + if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) > >> + drm_dbg_kms(display->drm, > >> "Same special packet %02x twice in a row.\n", cmd); > >> > >> - intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); > >> + intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); > >> > >> mask = SPL_PKT_SENT_INTERRUPT; > >> - if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) > >> - drm_err(&dev_priv->drm, > >> + if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) > >> + drm_err(display->drm, > >> "Video mode command 0x%08x send failed.\n", cmd); > >> > >> return 0; > >> @@ -324,7 +324,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, > >> > >> static bool glk_dsi_enable_io(struct intel_encoder *encoder) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> bool cold_boot = false; > >> @@ -334,29 +334,30 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) > >> * Power ON MIPI IO first and then write into IO reset and LP wake bits > >> */ > >> for_each_dsi_port(port, intel_dsi->ports) > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); > >> + intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); > >> > >> /* Put the IO into reset */ > >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > >> > >> /* Program LP Wake */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), > >> + u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); > >> + > >> + intel_de_rmw(display, MIPI_CTRL(display, port), > >> GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); > >> } > >> > >> /* Wait for Pwr ACK */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > >> GLK_MIPIIO_PORT_POWERED, 20)) > >> - drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); > >> + drm_err(display->drm, "MIPIO port is powergated\n"); > >> } > >> > >> /* Check for cold boot scenario */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> cold_boot |= > >> - !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); > >> + !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); > >> } > >> > >> return cold_boot; > >> @@ -364,99 +365,100 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) > >> > >> static void glk_dsi_device_ready(struct intel_encoder *encoder) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> /* Wait for MIPI PHY status bit to set */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > >> GLK_PHY_STATUS_PORT_READY, 20)) > >> - drm_err(&dev_priv->drm, "PHY is not ON\n"); > >> + drm_err(display->drm, "PHY is not ON\n"); > >> } > >> > >> /* Get IO out of reset */ > >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); > >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); > >> > >> /* Get IO out of Low power state*/ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { > >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > >> + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { > >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_MASK, DEVICE_READY); > >> usleep_range(10, 15); > >> } else { > >> /* Enter ULPS */ > >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); > >> > >> /* Wait for ULPS active */ > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > >> GLK_ULPS_NOT_ACTIVE, 20)) > >> - drm_err(&dev_priv->drm, "ULPS not active\n"); > >> + drm_err(display->drm, "ULPS not active\n"); > >> > >> /* Exit ULPS */ > >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); > >> > >> /* Enter Normal Mode */ > >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_MASK, > >> ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > >> > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); > >> + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); > >> } > >> } > >> > >> /* Wait for Stop state */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), > >> GLK_DATA_LANE_STOP_STATE, 20)) > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "Date lane not in STOP state\n"); > >> } > >> > >> /* Wait for AFE LATCH */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), > >> + if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), > >> AFE_LATCHOUT, 20)) > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "D-PHY not entering LP-11 state\n"); > >> } > >> } > >> > >> static void bxt_dsi_device_ready(struct intel_encoder *encoder) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> u32 val; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> > >> /* Enable MIPI PHY transparent latch */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); > >> + intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); > >> usleep_range(2000, 2500); > >> } > >> > >> /* Clear ULPS and set device ready */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); > >> + val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); > >> val &= ~ULPS_STATE_MASK; > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); > >> usleep_range(2000, 2500); > >> val |= DEVICE_READY; > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), val); > >> } > >> } > >> > >> static void vlv_dsi_device_ready(struct intel_encoder *encoder) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> > >> vlv_flisdsi_get(dev_priv); > >> /* program rcomp for compliance, reduce from 50 ohms to 45 ohms > >> @@ -469,7 +471,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > >> > >> for_each_dsi_port(port, intel_dsi->ports) { > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_ENTER); > >> usleep_range(2500, 3000); > >> > >> @@ -477,14 +479,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > >> * Common bit for both MIPI Port A & MIPI Port C > >> * No similar bit in MIPI Port C reg > >> */ > >> - intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > >> + intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); > >> usleep_range(1000, 1500); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_EXIT); > >> usleep_range(2500, 3000); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> DEVICE_READY); > >> usleep_range(2500, 3000); > >> } > >> @@ -504,50 +506,50 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > >> > >> static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> /* Enter ULPS */ > >> for_each_dsi_port(port, intel_dsi->ports) > >> - intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_rmw(display, MIPI_DEVICE_READY(display, port), > >> ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); > >> > >> /* Wait for MIPI PHY status bit to unset */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > >> GLK_PHY_STATUS_PORT_READY, 20)) > >> - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); > >> + drm_err(display->drm, "PHY is not turning OFF\n"); > >> } > >> > >> /* Wait for Pwr ACK bit to unset */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > >> GLK_MIPIIO_PORT_POWERED, 20)) > >> - drm_err(&dev_priv->drm, > >> + drm_err(display->drm, > >> "MIPI IO Port is not powergated\n"); > >> } > >> } > >> > >> static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> /* Put the IO into reset */ > >> - intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > >> + intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); > >> > >> /* Wait for MIPI PHY status bit to unset */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), > >> + if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), > >> GLK_PHY_STATUS_PORT_READY, 20)) > >> - drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); > >> + drm_err(display->drm, "PHY is not turning OFF\n"); > >> } > >> > >> /* Clear MIPI mode */ > >> for_each_dsi_port(port, intel_dsi->ports) > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); > >> + intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); > >> } > >> > >> static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) > >> @@ -564,25 +566,26 @@ static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) > >> > >> static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> for_each_dsi_port(port, intel_dsi->ports) { > >> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ > >> i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? > >> BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> DEVICE_READY | ULPS_STATE_ENTER); > >> usleep_range(2000, 2500); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> DEVICE_READY | ULPS_STATE_EXIT); > >> usleep_range(2000, 2500); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), > >> DEVICE_READY | ULPS_STATE_ENTER); > >> usleep_range(2000, 2500); > >> > >> @@ -591,15 +594,15 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > >> * Port A only. MIPI Port C has no similar bit for checking. > >> */ > >> if ((IS_BROXTON(dev_priv) || port == PORT_A) && > >> - intel_de_wait_for_clear(dev_priv, port_ctrl, > >> + intel_de_wait_for_clear(display, port_ctrl, > >> AFE_LATCHOUT, 30)) > >> - drm_err(&dev_priv->drm, "DSI LP not going Low\n"); > >> + drm_err(display->drm, "DSI LP not going Low\n"); > >> > >> /* Disable MIPI PHY transparent latch */ > >> - intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); > >> + intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); > >> usleep_range(1000, 1500); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); > >> usleep_range(2000, 2500); > >> } > >> } > >> @@ -607,6 +610,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > >> static void intel_dsi_port_enable(struct intel_encoder *encoder, > >> const struct intel_crtc_state *crtc_state) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> @@ -617,11 +621,11 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > >> > >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > >> for_each_dsi_port(port, intel_dsi->ports) > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), > >> + intel_de_rmw(display, MIPI_CTRL(display, port), > >> BXT_PIXEL_OVERLAP_CNT_MASK, > >> temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); > >> } else { > >> - intel_de_rmw(dev_priv, VLV_CHICKEN_3, > >> + intel_de_rmw(display, VLV_CHICKEN_3, > >> PIXEL_OVERLAP_CNT_MASK, > >> temp << PIXEL_OVERLAP_CNT_SHIFT); > >> } > >> @@ -631,7 +635,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > >> u32 temp; > >> > >> - temp = intel_de_read(dev_priv, port_ctrl); > >> + temp = intel_de_read(display, port_ctrl); > >> > >> temp &= ~LANE_CONFIGURATION_MASK; > >> temp &= ~DUAL_LINK_MODE_MASK; > >> @@ -651,13 +655,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > >> temp |= DITHERING_ENABLE; > >> > >> /* assert ip_tg_enable signal */ > >> - intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); > >> - intel_de_posting_read(dev_priv, port_ctrl); > >> + intel_de_write(display, port_ctrl, temp | DPI_ENABLE); > >> + intel_de_posting_read(display, port_ctrl); > >> } > >> } > >> > >> static void intel_dsi_port_disable(struct intel_encoder *encoder) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> @@ -666,8 +671,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) > >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > >> > >> /* de-assert ip_tg_enable signal */ > >> - intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); > >> - intel_de_posting_read(dev_priv, port_ctrl); > >> + intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); > >> + intel_de_posting_read(display, port_ctrl); > >> } > >> } > >> > >> @@ -721,6 +726,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > >> const struct intel_crtc_state *pipe_config, > >> const struct drm_connector_state *conn_state) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > >> @@ -728,7 +734,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > >> enum port port; > >> bool glk_cold_boot = false; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> > >> intel_dsi_wait_panel_power_cycle(intel_dsi); > >> > >> @@ -748,16 +754,16 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > >> > >> if (IS_BROXTON(dev_priv)) { > >> /* Add MIPI IO reset programming for modeset */ > >> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); > >> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); > >> > >> /* Power up DSI regulator */ > >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); > >> + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > >> + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); > >> } > >> > >> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > >> /* Disable DPOunit clock gating, can stall pipe */ > >> - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), > >> + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), > >> 0, DPOUNIT_CLOCK_GATE_DISABLE); > >> } > >> > >> @@ -793,8 +799,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, > >> */ > >> if (is_cmd_mode(intel_dsi)) { > >> for_each_dsi_port(port, intel_dsi->ports) > >> - intel_de_write(dev_priv, > >> - MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); > >> + intel_de_write(display, > >> + MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); > >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); > >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); > >> } else { > >> @@ -866,11 +872,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > >> const struct intel_crtc_state *old_crtc_state, > >> const struct drm_connector_state *old_conn_state) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> > >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > >> intel_crtc_vblank_off(old_crtc_state); > >> @@ -901,12 +908,12 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > >> > >> if (IS_BROXTON(dev_priv)) { > >> /* Power down DSI regulator to save power */ > >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > >> - intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, > >> + intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); > >> + intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, > >> HS_IO_CTRL_SELECT); > >> > >> /* Add MIPI IO reset programming for modeset */ > >> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); > >> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); > >> } > >> > >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > >> @@ -914,7 +921,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > >> } else { > >> vlv_dsi_pll_disable(encoder); > >> > >> - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), > >> + intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), > >> DPOUNIT_CLOCK_GATE_DISABLE, 0); > >> } > >> > >> @@ -930,13 +937,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, > >> static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > >> enum pipe *pipe) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> intel_wakeref_t wakeref; > >> enum port port; > >> bool active = false; > >> > >> - drm_dbg_kms(&dev_priv->drm, "\n"); > >> + drm_dbg_kms(display->drm, "\n"); > >> > >> wakeref = intel_display_power_get_if_enabled(dev_priv, > >> encoder->power_domain); > >> @@ -955,7 +963,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > >> /* XXX: this only works for one DSI output */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); > >> - bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; > >> + bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; > >> > >> /* > >> * Due to some hardware limitations on VLV/CHV, the DPI enable > >> @@ -964,27 +972,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > >> */ > >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > >> port == PORT_C) > >> - enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; > >> + enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; > >> > >> /* Try command mode if video mode not enabled */ > >> if (!enabled) { > >> - u32 tmp = intel_de_read(dev_priv, > >> - MIPI_DSI_FUNC_PRG(port)); > >> + u32 tmp = intel_de_read(display, > >> + MIPI_DSI_FUNC_PRG(display, port)); > >> enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; > >> } > >> > >> if (!enabled) > >> continue; > >> > >> - if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) > >> + if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) > >> continue; > >> > >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > >> - u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > >> + u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); > >> tmp &= BXT_PIPE_SELECT_MASK; > >> tmp >>= BXT_PIPE_SELECT_SHIFT; > >> > >> - if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) > >> + if (drm_WARN_ON(display->drm, tmp > PIPE_C)) > >> continue; > >> > >> *pipe = tmp; > >> @@ -1005,7 +1013,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > >> static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > >> struct intel_crtc_state *pipe_config) > >> { > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_display_mode *adjusted_mode = > >> &pipe_config->hw.adjusted_mode; > >> struct drm_display_mode *adjusted_mode_sw; > >> @@ -1027,11 +1035,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > >> * encoder->get_hw_state() returns true. > >> */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) > >> + if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) > >> break; > >> } > >> > >> - fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; > >> + fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; > >> bpp = mipi_dsi_pixel_format_to_bpp( > >> pixel_format_from_register_bits(fmt)); > >> > >> @@ -1043,24 +1051,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > >> > >> /* In terms of pixels */ > >> adjusted_mode->crtc_hdisplay = > >> - intel_de_read(dev_priv, > >> + intel_de_read(display, > >> BXT_MIPI_TRANS_HACTIVE(port)); > >> adjusted_mode->crtc_vdisplay = > >> - intel_de_read(dev_priv, > >> + intel_de_read(display, > >> BXT_MIPI_TRANS_VACTIVE(port)); > >> adjusted_mode->crtc_vtotal = > >> - intel_de_read(dev_priv, > >> + intel_de_read(display, > >> BXT_MIPI_TRANS_VTOTAL(port)); > >> > >> hactive = adjusted_mode->crtc_hdisplay; > >> - hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); > >> + hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); > >> > >> /* > >> * Meaningful for video mode non-burst sync pulse mode only, > >> * can be zero for non-burst sync events and burst modes > >> */ > >> - hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); > >> - hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); > >> + hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); > >> + hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); > >> > >> /* harizontal values are in terms of high speed byte clock */ > >> hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, > >> @@ -1077,8 +1085,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > >> } > >> > >> /* vertical values are in terms of lines */ > >> - vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); > >> - vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); > >> + vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); > >> + vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); > >> > >> adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; > >> adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; > >> @@ -1207,6 +1215,7 @@ static u16 txclkesc(u32 divider, unsigned int us) > >> static void set_dsi_timings(struct intel_encoder *encoder, > >> const struct drm_display_mode *adjusted_mode) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> @@ -1249,29 +1258,29 @@ static void set_dsi_timings(struct intel_encoder *encoder, > >> * vactive, as they are calculated per channel basis, > >> * whereas these values should be based on resolution. > >> */ > >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), > >> + intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), > >> adjusted_mode->crtc_hdisplay); > >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), > >> + intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), > >> adjusted_mode->crtc_vdisplay); > >> - intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), > >> + intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), > >> adjusted_mode->crtc_vtotal); > >> } > >> > >> - intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), > >> + intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), > >> hactive); > >> - intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); > >> + intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); > >> > >> /* meaningful for video mode non-burst sync pulse mode only, > >> * can be zero for non-burst sync events and burst modes */ > >> - intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), > >> + intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), > >> hsync); > >> - intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); > >> + intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); > >> > >> /* vertical values are in terms of lines */ > >> - intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); > >> - intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), > >> + intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); > >> + intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), > >> vsync); > >> - intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); > >> + intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); > >> } > >> } > >> > >> @@ -1295,6 +1304,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) > >> static void intel_dsi_prepare(struct intel_encoder *encoder, > >> const struct intel_crtc_state *pipe_config) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> @@ -1304,7 +1314,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> u32 val, tmp; > >> u16 mode_hdisplay; > >> > >> - drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); > >> + drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); > >> > >> mode_hdisplay = adjusted_mode->crtc_hdisplay; > >> > >> @@ -1320,31 +1330,31 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> * escape clock divider, 20MHz, shared for A and C. > >> * device ready must be off when doing this! txclkesc? > >> */ > >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); > >> + tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); > >> tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > >> - intel_de_write(dev_priv, MIPI_CTRL(PORT_A), > >> + intel_de_write(display, MIPI_CTRL(display, PORT_A), > >> tmp | ESCAPE_CLOCK_DIVIDER_1); > >> > >> /* read request priority is per pipe */ > >> - tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); > >> + tmp = intel_de_read(display, MIPI_CTRL(display, port)); > >> tmp &= ~READ_REQUEST_PRIORITY_MASK; > >> - intel_de_write(dev_priv, MIPI_CTRL(port), > >> + intel_de_write(display, MIPI_CTRL(display, port), > >> tmp | READ_REQUEST_PRIORITY_HIGH); > >> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > >> enum pipe pipe = crtc->pipe; > >> > >> - intel_de_rmw(dev_priv, MIPI_CTRL(port), > >> + intel_de_rmw(display, MIPI_CTRL(display, port), > >> BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); > >> } > >> > >> /* XXX: why here, why like this? handling in irq handler?! */ > >> - intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); > >> - intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); > >> + intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); > >> + intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); > >> > >> - intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), > >> + intel_de_write(display, MIPI_DPHY_PARAM(display, port), > >> intel_dsi->dphy_reg); > >> > >> - intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), > >> + intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), > >> adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); > >> } > >> > >> @@ -1372,7 +1382,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> } > >> > >> for_each_dsi_port(port, intel_dsi->ports) { > >> - intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); > >> + intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); > >> > >> /* timeouts for recovery. one frame IIUC. if counter expires, > >> * EOT and stop state. */ > >> @@ -1393,23 +1403,23 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> > >> if (is_vid_mode(intel_dsi) && > >> intel_dsi->video_mode == BURST_MODE) { > >> - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), > >> + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), > >> txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); > >> } else { > >> - intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), > >> + intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), > >> txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); > >> } > >> - intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), > >> + intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), > >> intel_dsi->lp_rx_timeout); > >> - intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), > >> + intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), > >> intel_dsi->turn_arnd_val); > >> - intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), > >> + intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), > >> intel_dsi->rst_timer_val); > >> > >> /* dphy stuff */ > >> > >> /* in terms of low power clock */ > >> - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), > >> + intel_de_write(display, MIPI_INIT_COUNT(display, port), > >> txclkesc(intel_dsi->escape_clk_div, 100)); > >> > >> if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && > >> @@ -1420,16 +1430,16 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> * getting used. So write the other port > >> * if not in dual link mode. > >> */ > >> - intel_de_write(dev_priv, > >> - MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), > >> + intel_de_write(display, > >> + MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), > >> intel_dsi->init_count); > >> } > >> > >> /* recovery disables */ > >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); > >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); > >> > >> /* in terms of low power clock */ > >> - intel_de_write(dev_priv, MIPI_INIT_COUNT(port), > >> + intel_de_write(display, MIPI_INIT_COUNT(display, port), > >> intel_dsi->init_count); > >> > >> /* in terms of txbyteclkhs. actual high to low switch + > >> @@ -1437,7 +1447,7 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> * > >> * XXX: write MIPI_STOP_STATE_STALL? > >> */ > >> - intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), > >> + intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), > >> intel_dsi->hs_to_lp_count); > >> > >> /* XXX: low power clock equivalence in terms of byte clock. > >> @@ -1446,14 +1456,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL > >> * ) / 105.??? > >> */ > >> - intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), > >> + intel_de_write(display, MIPI_LP_BYTECLK(display, port), > >> intel_dsi->lp_byte_clk); > >> > >> if (IS_GEMINILAKE(dev_priv)) { > >> - intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), > >> + intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), > >> intel_dsi->lp_byte_clk); > >> /* Shadow of DPHY reg */ > >> - intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), > >> + intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), > >> intel_dsi->dphy_reg); > >> } > >> > >> @@ -1462,10 +1472,10 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> * this register in terms of byte clocks. based on dsi transfer > >> * rate and the number of lanes configured the time taken to > >> * transmit 16 long packets in a dsi stream varies. */ > >> - intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), > >> + intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), > >> intel_dsi->bw_timer); > >> > >> - intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), > >> + intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), > >> intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); > >> > >> if (is_vid_mode(intel_dsi)) { > >> @@ -1493,13 +1503,14 @@ static void intel_dsi_prepare(struct intel_encoder *encoder, > >> break; > >> } > >> > >> - intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); > >> + intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); > >> } > >> } > >> } > >> > >> static void intel_dsi_unprepare(struct intel_encoder *encoder) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> enum port port; > >> @@ -1509,17 +1520,17 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) > >> > >> for_each_dsi_port(port, intel_dsi->ports) { > >> /* Panel commands can be sent when clock is in LP11 */ > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); > >> > >> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > >> bxt_dsi_reset_clocks(encoder, port); > >> else > >> vlv_dsi_reset_clocks(encoder, port); > >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); > >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); > >> > >> - intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); > >> + intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); > >> > >> - intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); > >> + intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); > >> } > >> } > >> > >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > >> index ae0a0b11bae3..70c5a13a3c75 100644 > >> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > >> @@ -365,13 +365,13 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, > >> > >> void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) > >> { > >> - u32 temp; > >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> + struct intel_display *display = to_intel_display(encoder); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > >> + u32 temp; > >> > >> - temp = intel_de_read(dev_priv, MIPI_CTRL(port)); > >> + temp = intel_de_read(display, MIPI_CTRL(display, port)); > >> temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > >> - intel_de_write(dev_priv, MIPI_CTRL(port), > >> + intel_de_write(display, MIPI_CTRL(display, port), > >> temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); > >> } > >> > >> @@ -570,24 +570,24 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, > >> > >> void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) > >> { > >> + struct intel_display *display = to_intel_display(encoder); > >> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> u32 tmp; > >> - struct drm_device *dev = encoder->base.dev; > >> - struct drm_i915_private *dev_priv = to_i915(dev); > >> > >> /* Clear old configurations */ > >> if (IS_BROXTON(dev_priv)) { > >> - tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); > >> + tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); > >> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); > >> tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); > >> tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); > >> tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); > >> - intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); > >> + intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); > >> } else { > >> - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); > >> + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); > >> > >> - intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); > >> + intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); > >> } > >> - intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); > >> + intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); > >> } > >> > >> static void assert_dsi_pll(struct drm_i915_private *i915, bool state) > >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > >> index 12a608a73720..c1126d170ec6 100644 > >> --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h > >> @@ -11,26 +11,23 @@ > >> #define VLV_MIPI_BASE VLV_DISPLAY_BASE > >> #define BXT_MIPI_BASE 0x60000 > >> > >> -#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) > >> +#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) > >> > >> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ > >> -#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) > >> +#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) > >> > >> /* BXT MIPI mode configure */ > >> -#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 > >> -#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 > >> -#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ > >> - _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) > >> +#define _BXT_MIPIA_TRANS_HACTIVE 0xb0f8 > >> +#define _BXT_MIPIC_TRANS_HACTIVE 0xb8f8 > >> +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) > >> > >> -#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC > >> -#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC > >> -#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ > >> - _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) > >> +#define _BXT_MIPIA_TRANS_VACTIVE 0xb0fc > >> +#define _BXT_MIPIC_TRANS_VACTIVE 0xb8fc > >> +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) > >> > >> -#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 > >> -#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 > >> -#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ > >> - _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) > >> +#define _BXT_MIPIA_TRANS_VTOTAL 0xb100 > >> +#define _BXT_MIPIC_TRANS_VTOTAL 0xb900 > >> +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) > >> > >> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) > >> #define STAP_SELECT (1 << 0) > >> @@ -38,14 +35,14 @@ > >> #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) > >> #define HS_IO_CTRL_SELECT (1 << 0) > >> > >> -#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) > >> -#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > >> -#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > >> +#define _MIPIA_PORT_CTRL 0x61190 > >> +#define _MIPIC_PORT_CTRL 0x61700 > >> +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > >> > >> /* BXT port control */ > >> -#define _BXT_MIPIA_PORT_CTRL 0x6B0C0 > >> -#define _BXT_MIPIC_PORT_CTRL 0x6B8C0 > >> -#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) > >> +#define _BXT_MIPIA_PORT_CTRL 0xb0c0 > >> +#define _BXT_MIPIC_PORT_CTRL 0xb8c0 > >> +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) > >> > >> #define DPI_ENABLE (1 << 31) /* A + C */ > >> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 > >> @@ -87,17 +84,17 @@ > >> #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) > >> #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) > >> > >> -#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) > >> -#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > >> -#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > >> +#define _MIPIA_TEARING_CTRL 0x61194 > >> +#define _MIPIC_TEARING_CTRL 0x61704 > >> +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > >> #define TEARING_EFFECT_DELAY_SHIFT 0 > >> #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > >> > >> /* MIPI DSI Controller and D-PHY registers */ > >> > >> -#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) > >> -#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) > >> -#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) > >> +#define _MIPIA_DEVICE_READY 0xb000 > >> +#define _MIPIC_DEVICE_READY 0xb800 > >> +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) > >> #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ > >> #define ULPS_STATE_MASK (3 << 1) > >> #define ULPS_STATE_ENTER (2 << 1) > >> @@ -105,12 +102,12 @@ > >> #define ULPS_STATE_NORMAL_OPERATION (0 << 1) > >> #define DEVICE_READY (1 << 0) > >> > >> -#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) > >> -#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) > >> -#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) > >> -#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) > >> -#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) > >> -#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) > >> +#define _MIPIA_INTR_STAT 0xb004 > >> +#define _MIPIC_INTR_STAT 0xb804 > >> +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) > >> +#define _MIPIA_INTR_EN 0xb008 > >> +#define _MIPIC_INTR_EN 0xb808 > >> +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) > >> #define TEARING_EFFECT (1 << 31) > >> #define SPL_PKT_SENT_INTERRUPT (1 << 30) > >> #define GEN_READ_DATA_AVAIL (1 << 29) > >> @@ -144,9 +141,9 @@ > >> #define RXSOT_SYNC_ERROR (1 << 1) > >> #define RXSOT_ERROR (1 << 0) > >> > >> -#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) > >> -#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) > >> -#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) > >> +#define _MIPIA_DSI_FUNC_PRG 0xb00c > >> +#define _MIPIC_DSI_FUNC_PRG 0xb80c > >> +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) > >> #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) > >> #define CMD_MODE_NOT_SUPPORTED (0 << 13) > >> #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) > >> @@ -167,77 +164,77 @@ > >> #define DATA_LANES_PRG_REG_SHIFT 0 > >> #define DATA_LANES_PRG_REG_MASK (7 << 0) > >> > >> -#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) > >> -#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) > >> -#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) > >> +#define _MIPIA_HS_TX_TIMEOUT 0xb010 > >> +#define _MIPIC_HS_TX_TIMEOUT 0xb810 > >> +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) > >> #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff > >> > >> -#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) > >> -#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) > >> -#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) > >> +#define _MIPIA_LP_RX_TIMEOUT 0xb014 > >> +#define _MIPIC_LP_RX_TIMEOUT 0xb814 > >> +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) > >> #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff > >> > >> -#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) > >> -#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) > >> -#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > >> +#define _MIPIA_TURN_AROUND_TIMEOUT 0xb018 > >> +#define _MIPIC_TURN_AROUND_TIMEOUT 0xb818 > >> +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > >> #define TURN_AROUND_TIMEOUT_MASK 0x3f > >> > >> -#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) > >> -#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) > >> -#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > >> +#define _MIPIA_DEVICE_RESET_TIMER 0xb01c > >> +#define _MIPIC_DEVICE_RESET_TIMER 0xb81c > >> +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > >> #define DEVICE_RESET_TIMER_MASK 0xffff > >> > >> -#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) > >> -#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) > >> -#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) > >> +#define _MIPIA_DPI_RESOLUTION 0xb020 > >> +#define _MIPIC_DPI_RESOLUTION 0xb820 > >> +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) > >> #define VERTICAL_ADDRESS_SHIFT 16 > >> #define VERTICAL_ADDRESS_MASK (0xffff << 16) > >> #define HORIZONTAL_ADDRESS_SHIFT 0 > >> #define HORIZONTAL_ADDRESS_MASK 0xffff > >> > >> -#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) > >> -#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) > >> -#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > >> +#define _MIPIA_DBI_FIFO_THROTTLE 0xb024 > >> +#define _MIPIC_DBI_FIFO_THROTTLE 0xb824 > >> +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > >> #define DBI_FIFO_EMPTY_HALF (0 << 0) > >> #define DBI_FIFO_EMPTY_QUARTER (1 << 0) > >> #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) > >> > >> /* regs below are bits 15:0 */ > >> -#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) > >> -#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) > >> -#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > >> +#define _MIPIA_HSYNC_PADDING_COUNT 0xb028 > >> +#define _MIPIC_HSYNC_PADDING_COUNT 0xb828 > >> +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > >> > >> -#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) > >> -#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) > >> -#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) > >> +#define _MIPIA_HBP_COUNT 0xb02c > >> +#define _MIPIC_HBP_COUNT 0xb82c > >> +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) > >> > >> -#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) > >> -#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) > >> -#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) > >> +#define _MIPIA_HFP_COUNT 0xb030 > >> +#define _MIPIC_HFP_COUNT 0xb830 > >> +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) > >> > >> -#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) > >> -#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) > >> -#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > >> +#define _MIPIA_HACTIVE_AREA_COUNT 0xb034 > >> +#define _MIPIC_HACTIVE_AREA_COUNT 0xb834 > >> +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > >> > >> -#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) > >> -#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) > >> -#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > >> +#define _MIPIA_VSYNC_PADDING_COUNT 0xb038 > >> +#define _MIPIC_VSYNC_PADDING_COUNT 0xb838 > >> +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > >> > >> -#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) > >> -#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) > >> -#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) > >> +#define _MIPIA_VBP_COUNT 0xb03c > >> +#define _MIPIC_VBP_COUNT 0xb83c > >> +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) > >> > >> -#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) > >> -#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) > >> -#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) > >> +#define _MIPIA_VFP_COUNT 0xb040 > >> +#define _MIPIC_VFP_COUNT 0xb840 > >> +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) > >> > >> -#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) > >> -#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) > >> -#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > >> +#define _MIPIA_HIGH_LOW_SWITCH_COUNT 0xb044 > >> +#define _MIPIC_HIGH_LOW_SWITCH_COUNT 0xb844 > >> +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > >> > >> -#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) > >> -#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) > >> -#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) > >> +#define _MIPIA_DPI_CONTROL 0xb048 > >> +#define _MIPIC_DPI_CONTROL 0xb848 > >> +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) > >> #define DPI_LP_MODE (1 << 6) > >> #define BACKLIGHT_OFF (1 << 5) > >> #define BACKLIGHT_ON (1 << 4) > >> @@ -246,28 +243,27 @@ > >> #define TURN_ON (1 << 1) > >> #define SHUTDOWN (1 << 0) > >> > >> -#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) > >> -#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) > >> -#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) > >> +#define _MIPIA_DPI_DATA 0xb04c > >> +#define _MIPIC_DPI_DATA 0xb84c > >> +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) > >> #define COMMAND_BYTE_SHIFT 0 > >> #define COMMAND_BYTE_MASK (0x3f << 0) > >> > >> -#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) > >> -#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) > >> -#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) > >> +#define _MIPIA_INIT_COUNT 0xb050 > >> +#define _MIPIC_INIT_COUNT 0xb850 > >> +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) > >> #define MASTER_INIT_TIMER_SHIFT 0 > >> #define MASTER_INIT_TIMER_MASK (0xffff << 0) > >> > >> -#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) > >> -#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) > >> -#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ > >> - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > >> +#define _MIPIA_MAX_RETURN_PKT_SIZE 0xb054 > >> +#define _MIPIC_MAX_RETURN_PKT_SIZE 0xb854 > >> +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > >> #define MAX_RETURN_PKT_SIZE_SHIFT 0 > >> #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) > >> > >> -#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) > >> -#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) > >> -#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > >> +#define _MIPIA_VIDEO_MODE_FORMAT 0xb058 > >> +#define _MIPIC_VIDEO_MODE_FORMAT 0xb858 > >> +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > >> #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) > >> #define DISABLE_VIDEO_BTA (1 << 3) > >> #define IP_TG_CONFIG (1 << 2) > >> @@ -275,9 +271,9 @@ > >> #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) > >> #define VIDEO_MODE_BURST (3 << 0) > >> > >> -#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) > >> -#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) > >> -#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) > >> +#define _MIPIA_EOT_DISABLE 0xb05c > >> +#define _MIPIC_EOT_DISABLE 0xb85c > >> +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) > >> #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) > >> #define BXT_DPHY_DEFEATURE_EN (1 << 8) > >> #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) > >> @@ -289,36 +285,36 @@ > >> #define CLOCKSTOP (1 << 1) > >> #define EOT_DISABLE (1 << 0) > >> > >> -#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) > >> -#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) > >> -#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) > >> +#define _MIPIA_LP_BYTECLK 0xb060 > >> +#define _MIPIC_LP_BYTECLK 0xb860 > >> +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) > >> #define LP_BYTECLK_SHIFT 0 > >> #define LP_BYTECLK_MASK (0xffff << 0) > >> > >> -#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) > >> -#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) > >> -#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) > >> +#define _MIPIA_TLPX_TIME_COUNT 0xb0a4 > >> +#define _MIPIC_TLPX_TIME_COUNT 0xb8a4 > >> +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) > >> > >> -#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) > >> -#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) > >> -#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) > >> +#define _MIPIA_CLK_LANE_TIMING 0xb098 > >> +#define _MIPIC_CLK_LANE_TIMING 0xb898 > >> +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) > >> > >> /* bits 31:0 */ > >> -#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) > >> -#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) > >> -#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) > >> +#define _MIPIA_LP_GEN_DATA 0xb064 > >> +#define _MIPIC_LP_GEN_DATA 0xb864 > >> +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) > >> > >> /* bits 31:0 */ > >> -#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) > >> -#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) > >> -#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) > >> - > >> -#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) > >> -#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) > >> -#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) > >> -#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) > >> -#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) > >> -#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) > >> +#define _MIPIA_HS_GEN_DATA 0xb068 > >> +#define _MIPIC_HS_GEN_DATA 0xb868 > >> +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) > >> + > >> +#define _MIPIA_LP_GEN_CTRL 0xb06c > >> +#define _MIPIC_LP_GEN_CTRL 0xb86c > >> +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) > >> +#define _MIPIA_HS_GEN_CTRL 0xb070 > >> +#define _MIPIC_HS_GEN_CTRL 0xb870 > >> +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) > >> #define LONG_PACKET_WORD_COUNT_SHIFT 8 > >> #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) > >> #define SHORT_PACKET_PARAM_SHIFT 8 > >> @@ -329,9 +325,9 @@ > >> #define DATA_TYPE_MASK (0x3f << 0) > >> /* data type values, see include/video/mipi_display.h */ > >> > >> -#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) > >> -#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) > >> -#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) > >> +#define _MIPIA_GEN_FIFO_STAT 0xb074 > >> +#define _MIPIC_GEN_FIFO_STAT 0xb874 > >> +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) > >> #define DPI_FIFO_EMPTY (1 << 28) > >> #define DBI_FIFO_EMPTY (1 << 27) > >> #define LP_CTRL_FIFO_EMPTY (1 << 26) > >> @@ -347,16 +343,16 @@ > >> #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) > >> #define HS_DATA_FIFO_FULL (1 << 0) > >> > >> -#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) > >> -#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) > >> -#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > >> +#define _MIPIA_HS_LS_DBI_ENABLE 0xb078 > >> +#define _MIPIC_HS_LS_DBI_ENABLE 0xb878 > >> +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > >> #define DBI_HS_LP_MODE_MASK (1 << 0) > >> #define DBI_LP_MODE (1 << 0) > >> #define DBI_HS_MODE (0 << 0) > >> > >> -#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) > >> -#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) > >> -#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) > >> +#define _MIPIA_DPHY_PARAM 0xb080 > >> +#define _MIPIC_DPHY_PARAM 0xb880 > >> +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) > >> #define EXIT_ZERO_COUNT_SHIFT 24 > >> #define EXIT_ZERO_COUNT_MASK (0x3f << 24) > >> #define TRAIL_COUNT_SHIFT 16 > >> @@ -366,34 +362,34 @@ > >> #define PREPARE_COUNT_SHIFT 0 > >> #define PREPARE_COUNT_MASK (0x3f << 0) > >> > >> -#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) > >> -#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) > >> -#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) > >> +#define _MIPIA_DBI_BW_CTRL 0xb084 > >> +#define _MIPIC_DBI_BW_CTRL 0xb884 > >> +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) > >> > >> -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) > >> -#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) > >> -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > >> +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT 0xb088 > >> +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT 0xb888 > >> +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > >> #define LP_HS_SSW_CNT_SHIFT 16 > >> #define LP_HS_SSW_CNT_MASK (0xffff << 16) > >> #define HS_LP_PWR_SW_CNT_SHIFT 0 > >> #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) > >> > >> -#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) > >> -#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) > >> -#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > >> +#define _MIPIA_STOP_STATE_STALL 0xb08c > >> +#define _MIPIC_STOP_STATE_STALL 0xb88c > >> +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > >> #define STOP_STATE_STALL_COUNTER_SHIFT 0 > >> #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) > >> > >> -#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) > >> -#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) > >> -#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > >> -#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) > >> -#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) > >> -#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) > >> +#define _MIPIA_INTR_STAT_REG_1 0xb090 > >> +#define _MIPIC_INTR_STAT_REG_1 0xb890 > >> +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > >> +#define _MIPIA_INTR_EN_REG_1 0xb094 > >> +#define _MIPIC_INTR_EN_REG_1 0xb894 > >> +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) > >> #define RX_CONTENTION_DETECTED (1 << 0) > >> > >> /* XXX: only pipe A ?!? */ > >> -#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) > >> +#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) > >> #define DBI_TYPEC_ENABLE (1 << 31) > >> #define DBI_TYPEC_WIP (1 << 30) > >> #define DBI_TYPEC_OPTION_SHIFT 28 > >> @@ -406,9 +402,9 @@ > >> > >> /* MIPI adapter registers */ > >> > >> -#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) > >> -#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) > >> -#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) > >> +#define _MIPIA_CTRL 0xb104 > >> +#define _MIPIC_CTRL 0xb904 > >> +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) > >> #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ > >> #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) > >> #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) > >> @@ -439,41 +435,41 @@ > >> #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ > >> #define GLK_MIPIIO_ENABLE (1 << 0) > >> > >> -#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) > >> -#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) > >> -#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) > >> +#define _MIPIA_DATA_ADDRESS 0xb108 > >> +#define _MIPIC_DATA_ADDRESS 0xb908 > >> +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) > >> #define DATA_MEM_ADDRESS_SHIFT 5 > >> #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) > >> #define DATA_VALID (1 << 0) > >> > >> -#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) > >> -#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) > >> -#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) > >> +#define _MIPIA_DATA_LENGTH 0xb10c > >> +#define _MIPIC_DATA_LENGTH 0xb90c > >> +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) > >> #define DATA_LENGTH_SHIFT 0 > >> #define DATA_LENGTH_MASK (0xfffff << 0) > >> > >> -#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) > >> -#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) > >> -#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > >> +#define _MIPIA_COMMAND_ADDRESS 0xb110 > >> +#define _MIPIC_COMMAND_ADDRESS 0xb910 > >> +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > >> #define COMMAND_MEM_ADDRESS_SHIFT 5 > >> #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) > >> #define AUTO_PWG_ENABLE (1 << 2) > >> #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) > >> #define COMMAND_VALID (1 << 0) > >> > >> -#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) > >> -#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) > >> -#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) > >> +#define _MIPIA_COMMAND_LENGTH 0xb114 > >> +#define _MIPIC_COMMAND_LENGTH 0xb914 > >> +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) > >> #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ > >> #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) > >> > >> -#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) > >> -#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) > >> -#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ > >> +#define _MIPIA_READ_DATA_RETURN0 0xb118 > >> +#define _MIPIC_READ_DATA_RETURN0 0xb918 > >> +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ > >> > >> -#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) > >> -#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) > >> -#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > >> +#define _MIPIA_READ_DATA_VALID 0xb138 > >> +#define _MIPIC_READ_DATA_VALID 0xb938 > >> +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > >> #define READ_DATA_VALID(n) (1 << (n)) > >> > >> #endif /* __VLV_DSI_REGS_H__ */ > >> -- > >> 2.39.2 > >> ^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (3 preceding siblings ...) 2024-04-19 10:04 ` [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable Jani Nikula @ 2024-04-19 10:46 ` Patchwork 2024-04-19 10:53 ` ✗ Fi.CI.BAT: failure " Patchwork ` (3 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2024-04-19 10:46 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) URL : https://patchwork.freedesktop.org/series/132285/ State : warning == Summary == Error: dim checkpatch failed aa3c68d4f30e drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition 0ba6f1a20ef1 drm/i915/dsi: add VLV_ prefix to VLV only register macros -:61: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #61: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:92: +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) total: 0 errors, 1 warnings, 0 checks, 40 lines checked 5b3d3c36152a drm/i915/dsi: unify connector/encoder type and name usage -:255: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB> #255: FILE: drivers/gpu/drm/i915/display/vlv_dsi.c:1991: + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ total: 0 errors, 0 warnings, 1 checks, 264 lines checked 7367bc42c786 drm/i915/dsi: pass display to register macros instead of implicit variable -:1107: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1107: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:22: +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) -:1115: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1115: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:26: +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) -:1123: WARNING:LONG_LINE: line length of 127 exceeds 100 columns #1123: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:30: +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) -:1136: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #1136: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:40: +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) -:1144: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #1144: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:45: +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) -:1157: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1157: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:89: +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) -:1168: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1168: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:97: +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) -:1184: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1184: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:107: +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) -:1187: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #1187: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:110: +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) -:1200: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1200: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:146: +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) -:1213: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1213: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:169: +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) -:1221: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1221: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:174: +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) -:1229: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1229: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:179: +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) -:1237: WARNING:LONG_LINE: line length of 144 exceeds 100 columns #1237: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:184: +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) -:1245: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #1245: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:189: +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) -:1256: WARNING:LONG_LINE: line length of 142 exceeds 100 columns #1256: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:197: +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) -:1267: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1267: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:205: +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) -:1274: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1274: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:209: +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) -:1281: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1281: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:213: +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) -:1288: WARNING:LONG_LINE: line length of 144 exceeds 100 columns #1288: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:217: +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) -:1295: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1295: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:221: +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) -:1302: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1302: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:225: +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) -:1309: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1309: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:229: +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) -:1316: WARNING:LONG_LINE: line length of 163 exceeds 100 columns #1316: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:233: +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) -:1323: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1323: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:237: +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) -:1336: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #1336: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:248: +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) -:1345: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1345: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:254: +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) -:1355: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1355: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:260: +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) -:1364: WARNING:LONG_LINE: line length of 142 exceeds 100 columns #1364: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:266: +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) -:1377: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1377: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:276: +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) -:1390: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1390: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:290: +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) -:1399: WARNING:LONG_LINE: line length of 139 exceeds 100 columns #1399: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:296: +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) -:1406: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1406: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:300: +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) -:1414: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1414: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:305: +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) -:1429: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1429: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:310: +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) -:1433: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1433: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:314: +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) -:1436: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1436: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:317: +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) -:1449: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1449: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:330: +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) -:1462: WARNING:LONG_LINE: line length of 140 exceeds 100 columns #1462: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:348: +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) -:1472: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1472: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:355: +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) -:1485: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1485: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:367: +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) -:1492: WARNING:LONG_LINE: line length of 164 exceeds 100 columns #1492: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:371: +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) -:1503: WARNING:LONG_LINE: line length of 140 exceeds 100 columns #1503: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:379: +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) -:1515: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1515: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:385: +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) -:1518: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1518: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:388: +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) -:1536: WARNING:LONG_LINE: line length of 116 exceeds 100 columns #1536: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:407: +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) -:1549: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1549: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:440: +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) -:1559: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1559: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:447: +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) -:1568: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1568: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:453: +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) -:1580: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #1580: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:462: +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) -:1589: WARNING:LONG_LINE: line length of 167 exceeds 100 columns #1589: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:468: +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ -:1596: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1596: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:472: +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) total: 0 errors, 52 warnings, 0 checks, 1502 lines checked ^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (4 preceding siblings ...) 2024-04-19 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) Patchwork @ 2024-04-19 10:53 ` Patchwork 2024-04-19 12:04 ` Jani Nikula 2024-04-22 23:33 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) Patchwork ` (2 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Patchwork @ 2024-04-19 10:53 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 15897 bytes --] == Series Details == Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) URL : https://patchwork.freedesktop.org/series/132285/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14611 -> Patchwork_132285v2 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_132285v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_132285v2, please notify your bug team ("I915-ci-infra@lists.freedesktop.org") to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/index.html Participating hosts (34 -> 33) ------------------------------ Additional (4): fi-glk-j4005 bat-dg2-11 bat-mtlp-6 fi-elk-e7500 Missing (5): fi-kbl-7567u bat-dg1-7 fi-apl-guc fi-kbl-8809g bat-jsl-1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_132285v2: ### IGT changes ### #### Possible regressions #### * igt@core_auth@basic-auth: - bat-arls-2: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-2/igt@core_auth@basic-auth.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-2/igt@core_auth@basic-auth.html * igt@i915_selftest@live@active: - fi-glk-j4005: NOTRUN -> [DMESG-FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@i915_selftest@live@active.html * igt@i915_selftest@live@gt_engines: - bat-arls-1: [PASS][4] -> [DMESG-WARN][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-1/igt@i915_selftest@live@gt_engines.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-1/igt@i915_selftest@live@gt_engines.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@debugfs_test@read_all_entries: - {bat-mtlp-9}: [PASS][6] -> [ABORT][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-mtlp-9/igt@debugfs_test@read_all_entries.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-9/igt@debugfs_test@read_all_entries.html Known issues ------------ Here are the changes found in Patchwork_132285v2 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#9318]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#1849] / [i915#2582]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@fbdev@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#2582]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@fbdev@write.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][11] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@gem_lmem_swapping@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4083]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_mmap@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4083]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_mmap@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4077]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4079]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_tiled_pread_basic.html - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4079]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][20] ([i915#6621]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@i915_pm_rps@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#6621]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html * igt@i915_selftest@live@objects: - bat-arls-1: [PASS][22] -> [DMESG-FAIL][23] ([i915#10262]) +32 other tests dmesg-fail [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-1/igt@i915_selftest@live@objects.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-1/igt@i915_selftest@live@objects.html * igt@i915_selftest@live@workarounds: - bat-adlp-6: [PASS][24] -> [INCOMPLETE][25] ([i915#9413]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-adlp-6/igt@i915_selftest@live@workarounds.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-adlp-6/igt@i915_selftest@live@workarounds.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][26] ([i915#4212] / [i915#9792]) +8 other tests skip [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][27] ([i915#4212]) +7 other tests skip [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][28] ([i915#5190] / [i915#9792]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html - bat-dg2-11: NOTRUN -> [SKIP][29] ([i915#5190]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][30] ([i915#4215] / [i915#5190]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][31] +10 other tests skip [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - bat-dg2-11: NOTRUN -> [SKIP][32] ([i915#4103] / [i915#4213]) +1 other test skip [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][33] ([i915#9792]) +17 other tests skip [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][34] ([i915#3555] / [i915#3840]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_dsc@dsc-basic.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][35] ([i915#3637] / [i915#9792]) +3 other tests skip [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][36] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][37] ([i915#5274]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html - bat-mtlp-6: NOTRUN -> [SKIP][38] ([i915#5274] / [i915#9792]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][39] ([i915#4342] / [i915#5354] / [i915#9792]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-11: NOTRUN -> [SKIP][40] ([i915#5354]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html - bat-mtlp-6: NOTRUN -> [SKIP][41] ([i915#5354] / [i915#9792]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html * igt@kms_pm_rpm@basic-pci-d3-state: - fi-elk-e7500: NOTRUN -> [SKIP][42] +24 other tests skip [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html * igt@kms_psr@psr-cursor-plane-move: - bat-mtlp-6: NOTRUN -> [SKIP][43] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-11: NOTRUN -> [SKIP][44] ([i915#1072] / [i915#9732]) +3 other tests skip [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-11: NOTRUN -> [SKIP][45] ([i915#3555]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html - bat-mtlp-6: NOTRUN -> [SKIP][46] ([i915#3555] / [i915#8809] / [i915#9792]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-11: NOTRUN -> [SKIP][47] ([i915#3708]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html - bat-mtlp-6: NOTRUN -> [SKIP][48] ([i915#3708] / [i915#9792]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-11: NOTRUN -> [SKIP][49] ([i915#3708] / [i915#4077]) +1 other test skip [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html - bat-mtlp-6: NOTRUN -> [SKIP][50] ([i915#3708] / [i915#4077]) +1 other test skip [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-read: - bat-dg2-11: NOTRUN -> [SKIP][51] ([i915#3291] / [i915#3708]) +2 other tests skip [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-read.html - bat-mtlp-6: NOTRUN -> [SKIP][52] ([i915#3708]) +1 other test skip [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-read.html * igt@prime_vgem@basic-write: - bat-mtlp-6: NOTRUN -> [SKIP][53] ([i915#10216] / [i915#3708]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-write.html #### Possible fixes #### * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [FAIL][54] ([i915#10378]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216 [i915#10262]: https://gitlab.freedesktop.org/drm/intel/issues/10262 [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809 [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 [i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413 [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673 [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732 [i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792 Build changes ------------- * Linux: CI_DRM_14611 -> Patchwork_132285v2 CI-20190529: 20190529 CI_DRM_14611: d02ac9d1c1a99eac3bb111d443de62d7286f7708 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7814: 7814 Patchwork_132285v2: d02ac9d1c1a99eac3bb111d443de62d7286f7708 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/index.html [-- Attachment #2: Type: text/html, Size: 19719 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) 2024-04-19 10:53 ` ✗ Fi.CI.BAT: failure " Patchwork @ 2024-04-19 12:04 ` Jani Nikula 0 siblings, 0 replies; 18+ messages in thread From: Jani Nikula @ 2024-04-19 12:04 UTC (permalink / raw) To: Patchwork, LGCI Bug Filing; +Cc: intel-gfx On Fri, 19 Apr 2024, Patchwork <patchwork@emeril.freedesktop.org> wrote: > == Series Details == > > Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) > URL : https://patchwork.freedesktop.org/series/132285/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14611 -> Patchwork_132285v2 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_132285v2 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_132285v2, please notify your bug team ("I915-ci-infra@lists.freedesktop.org") to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/index.html > > Participating hosts (34 -> 33) > ------------------------------ > > Additional (4): fi-glk-j4005 bat-dg2-11 bat-mtlp-6 fi-elk-e7500 > Missing (5): fi-kbl-7567u bat-dg1-7 fi-apl-guc fi-kbl-8809g bat-jsl-1 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_132285v2: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@core_auth@basic-auth: > - bat-arls-2: [PASS][1] -> [ABORT][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-2/igt@core_auth@basic-auth.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-2/igt@core_auth@basic-auth.html > > * igt@i915_selftest@live@active: > - fi-glk-j4005: NOTRUN -> [DMESG-FAIL][3] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@i915_selftest@live@active.html > > * igt@i915_selftest@live@gt_engines: > - bat-arls-1: [PASS][4] -> [DMESG-WARN][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-1/igt@i915_selftest@live@gt_engines.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-1/igt@i915_selftest@live@gt_engines.html Completely unrelated, please re-report. BR, Jani. > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * igt@debugfs_test@read_all_entries: > - {bat-mtlp-9}: [PASS][6] -> [ABORT][7] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-mtlp-9/igt@debugfs_test@read_all_entries.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-9/igt@debugfs_test@read_all_entries.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_132285v2 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@debugfs_test@basic-hwmon: > - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#9318]) > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html > > * igt@fbdev@info: > - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#1849] / [i915#2582]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@fbdev@info.html > > * igt@fbdev@write: > - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#2582]) +3 other tests skip > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@fbdev@write.html > > * igt@gem_huc_copy@huc-copy: > - fi-glk-j4005: NOTRUN -> [SKIP][11] ([i915#2190]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html > > * igt@gem_lmem_swapping@basic: > - fi-glk-j4005: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@gem_lmem_swapping@basic.html > > * igt@gem_lmem_swapping@verify-random: > - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html > > * igt@gem_mmap@basic: > - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4083]) > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_mmap@basic.html > - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4083]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_mmap@basic.html > > * igt@gem_tiled_blits@basic: > - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html > > * igt@gem_tiled_fence_blits@basic: > - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4077]) +2 other tests skip > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html > > * igt@gem_tiled_pread_basic: > - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4079]) +1 other test skip > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@gem_tiled_pread_basic.html > - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4079]) +1 other test skip > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html > > * igt@i915_pm_rps@basic-api: > - bat-dg2-11: NOTRUN -> [SKIP][20] ([i915#6621]) > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@i915_pm_rps@basic-api.html > - bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#6621]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html > > * igt@i915_selftest@live@objects: > - bat-arls-1: [PASS][22] -> [DMESG-FAIL][23] ([i915#10262]) +32 other tests dmesg-fail > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-arls-1/igt@i915_selftest@live@objects.html > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-arls-1/igt@i915_selftest@live@objects.html > > * igt@i915_selftest@live@workarounds: > - bat-adlp-6: [PASS][24] -> [INCOMPLETE][25] ([i915#9413]) > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-adlp-6/igt@i915_selftest@live@workarounds.html > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-adlp-6/igt@i915_selftest@live@workarounds.html > > * igt@kms_addfb_basic@addfb25-x-tiled-legacy: > - bat-mtlp-6: NOTRUN -> [SKIP][26] ([i915#4212] / [i915#9792]) +8 other tests skip > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html > > * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: > - bat-dg2-11: NOTRUN -> [SKIP][27] ([i915#4212]) +7 other tests skip > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html > > * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: > - bat-mtlp-6: NOTRUN -> [SKIP][28] ([i915#5190] / [i915#9792]) > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html > - bat-dg2-11: NOTRUN -> [SKIP][29] ([i915#5190]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html > > * igt@kms_addfb_basic@basic-y-tiled-legacy: > - bat-dg2-11: NOTRUN -> [SKIP][30] ([i915#4215] / [i915#5190]) > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-glk-j4005: NOTRUN -> [SKIP][31] +10 other tests skip > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > - bat-dg2-11: NOTRUN -> [SKIP][32] ([i915#4103] / [i915#4213]) +1 other test skip > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: > - bat-mtlp-6: NOTRUN -> [SKIP][33] ([i915#9792]) +17 other tests skip > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html > > * igt@kms_dsc@dsc-basic: > - bat-dg2-11: NOTRUN -> [SKIP][34] ([i915#3555] / [i915#3840]) > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_dsc@dsc-basic.html > > * igt@kms_flip@basic-flip-vs-dpms: > - bat-mtlp-6: NOTRUN -> [SKIP][35] ([i915#3637] / [i915#9792]) +3 other tests skip > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html > > * igt@kms_force_connector_basic@force-load-detect: > - bat-dg2-11: NOTRUN -> [SKIP][36] > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html > > * igt@kms_force_connector_basic@prune-stale-modes: > - bat-dg2-11: NOTRUN -> [SKIP][37] ([i915#5274]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html > - bat-mtlp-6: NOTRUN -> [SKIP][38] ([i915#5274] / [i915#9792]) > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html > > * igt@kms_frontbuffer_tracking@basic: > - bat-mtlp-6: NOTRUN -> [SKIP][39] ([i915#4342] / [i915#5354] / [i915#9792]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html > > * igt@kms_pm_backlight@basic-brightness: > - bat-dg2-11: NOTRUN -> [SKIP][40] ([i915#5354]) > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html > - bat-mtlp-6: NOTRUN -> [SKIP][41] ([i915#5354] / [i915#9792]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html > > * igt@kms_pm_rpm@basic-pci-d3-state: > - fi-elk-e7500: NOTRUN -> [SKIP][42] +24 other tests skip > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html > > * igt@kms_psr@psr-cursor-plane-move: > - bat-mtlp-6: NOTRUN -> [SKIP][43] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html > > * igt@kms_psr@psr-sprite-plane-onoff: > - bat-dg2-11: NOTRUN -> [SKIP][44] ([i915#1072] / [i915#9732]) +3 other tests skip > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html > > * igt@kms_setmode@basic-clone-single-crtc: > - bat-dg2-11: NOTRUN -> [SKIP][45] ([i915#3555]) > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html > - bat-mtlp-6: NOTRUN -> [SKIP][46] ([i915#3555] / [i915#8809] / [i915#9792]) > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html > > * igt@prime_vgem@basic-fence-flip: > - bat-dg2-11: NOTRUN -> [SKIP][47] ([i915#3708]) > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html > - bat-mtlp-6: NOTRUN -> [SKIP][48] ([i915#3708] / [i915#9792]) > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html > > * igt@prime_vgem@basic-fence-mmap: > - bat-dg2-11: NOTRUN -> [SKIP][49] ([i915#3708] / [i915#4077]) +1 other test skip > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html > - bat-mtlp-6: NOTRUN -> [SKIP][50] ([i915#3708] / [i915#4077]) +1 other test skip > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html > > * igt@prime_vgem@basic-read: > - bat-dg2-11: NOTRUN -> [SKIP][51] ([i915#3291] / [i915#3708]) +2 other tests skip > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-11/igt@prime_vgem@basic-read.html > - bat-mtlp-6: NOTRUN -> [SKIP][52] ([i915#3708]) +1 other test skip > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-read.html > > * igt@prime_vgem@basic-write: > - bat-mtlp-6: NOTRUN -> [SKIP][53] ([i915#10216] / [i915#3708]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-mtlp-6/igt@prime_vgem@basic-write.html > > > #### Possible fixes #### > > * igt@gem_lmem_swapping@basic@lmem0: > - bat-dg2-9: [FAIL][54] ([i915#10378]) -> [PASS][55] > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14611/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216 > [i915#10262]: https://gitlab.freedesktop.org/drm/intel/issues/10262 > [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 > [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 > [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 > [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 > [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 > [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 > [i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 > [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 > [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 > [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 > [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809 > [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 > [i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413 > [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673 > [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732 > [i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792 > > > Build changes > ------------- > > * Linux: CI_DRM_14611 -> Patchwork_132285v2 > > CI-20190529: 20190529 > CI_DRM_14611: d02ac9d1c1a99eac3bb111d443de62d7286f7708 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_7814: 7814 > Patchwork_132285v2: d02ac9d1c1a99eac3bb111d443de62d7286f7708 @ git://anongit.freedesktop.org/gfx-ci/linux > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v2/index.html -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (5 preceding siblings ...) 2024-04-19 10:53 ` ✗ Fi.CI.BAT: failure " Patchwork @ 2024-04-22 23:33 ` Patchwork 2024-04-22 23:40 ` ✓ Fi.CI.BAT: success " Patchwork 2024-04-23 20:48 ` ✗ Fi.CI.IGT: failure " Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2024-04-22 23:33 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) URL : https://patchwork.freedesktop.org/series/132285/ State : warning == Summary == Error: dim checkpatch failed 1c60cb4f5f7a drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition 0b6d2dbcdd06 drm/i915/dsi: add VLV_ prefix to VLV only register macros -:62: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #62: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:92: +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) total: 0 errors, 1 warnings, 0 checks, 40 lines checked 2567d11c3d9f drm/i915/dsi: unify connector/encoder type and name usage -:256: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB> #256: FILE: drivers/gpu/drm/i915/display/vlv_dsi.c:1991: + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ total: 0 errors, 0 warnings, 1 checks, 264 lines checked 832d9b2447e5 drm/i915/dsi: pass display to register macros instead of implicit variable -:1108: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1108: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:22: +#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) -:1116: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1116: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:26: +#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) -:1124: WARNING:LONG_LINE: line length of 127 exceeds 100 columns #1124: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:30: +#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) -:1137: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #1137: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:40: +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) -:1145: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #1145: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:45: +#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) -:1158: WARNING:LONG_LINE: line length of 129 exceeds 100 columns #1158: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:89: +#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) -:1169: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1169: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:97: +#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) -:1185: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1185: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:107: +#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) -:1188: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #1188: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:110: +#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) -:1201: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1201: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:146: +#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) -:1214: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1214: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:169: +#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) -:1222: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1222: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:174: +#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) -:1230: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1230: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:179: +#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) -:1238: WARNING:LONG_LINE: line length of 144 exceeds 100 columns #1238: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:184: +#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) -:1246: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #1246: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:189: +#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) -:1257: WARNING:LONG_LINE: line length of 142 exceeds 100 columns #1257: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:197: +#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) -:1268: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1268: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:205: +#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) -:1275: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1275: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:209: +#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) -:1282: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1282: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:213: +#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) -:1289: WARNING:LONG_LINE: line length of 144 exceeds 100 columns #1289: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:217: +#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) -:1296: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1296: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:221: +#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) -:1303: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1303: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:225: +#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) -:1310: WARNING:LONG_LINE: line length of 126 exceeds 100 columns #1310: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:229: +#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) -:1317: WARNING:LONG_LINE: line length of 163 exceeds 100 columns #1317: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:233: +#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) -:1324: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1324: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:237: +#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) -:1337: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #1337: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:248: +#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) -:1346: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1346: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:254: +#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) -:1356: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #1356: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:260: +#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) -:1365: WARNING:LONG_LINE: line length of 142 exceeds 100 columns #1365: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:266: +#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) -:1378: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1378: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:276: +#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) -:1391: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1391: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:290: +#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) -:1400: WARNING:LONG_LINE: line length of 139 exceeds 100 columns #1400: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:296: +#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) -:1407: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1407: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:300: +#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) -:1415: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1415: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:305: +#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) -:1430: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1430: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:310: +#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) -:1434: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1434: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:314: +#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) -:1437: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1437: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:317: +#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) -:1450: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1450: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:330: +#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) -:1463: WARNING:LONG_LINE: line length of 140 exceeds 100 columns #1463: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:348: +#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) -:1473: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #1473: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:355: +#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) -:1486: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1486: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:367: +#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) -:1493: WARNING:LONG_LINE: line length of 164 exceeds 100 columns #1493: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:371: +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) -:1504: WARNING:LONG_LINE: line length of 140 exceeds 100 columns #1504: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:379: +#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) -:1516: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1516: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:385: +#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) -:1519: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #1519: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:388: +#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) -:1537: WARNING:LONG_LINE: line length of 116 exceeds 100 columns #1537: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:407: +#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL) -:1550: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #1550: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:440: +#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) -:1560: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #1560: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:447: +#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) -:1569: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1569: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:453: +#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) -:1581: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #1581: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:462: +#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) -:1590: WARNING:LONG_LINE: line length of 167 exceeds 100 columns #1590: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:468: +#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */ -:1597: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #1597: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:472: +#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) total: 0 errors, 52 warnings, 0 checks, 1502 lines checked ^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (6 preceding siblings ...) 2024-04-22 23:33 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) Patchwork @ 2024-04-22 23:40 ` Patchwork 2024-04-23 20:48 ` ✗ Fi.CI.IGT: failure " Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2024-04-22 23:40 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 7471 bytes --] == Series Details == Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) URL : https://patchwork.freedesktop.org/series/132285/ State : success == Summary == CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132285v3 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/index.html Participating hosts (36 -> 35) ------------------------------ Additional (2): bat-dg2-11 fi-apl-guc Missing (3): bat-kbl-2 bat-jsl-1 fi-elk-e7500 Known issues ------------ Here are the changes found in Patchwork_132285v3 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/fi-apl-guc/igt@gem_lmem_swapping@basic.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_mmap@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@i915_pm_rps@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4212]) +7 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#5190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4215] / [i915#5190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4103] / [i915#4213]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#3840]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_dsc@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5274]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_hdmi_inject@inject-audio: - fi-apl-guc: NOTRUN -> [SKIP][13] +17 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/fi-apl-guc/igt@kms_hdmi_inject@inject-audio.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#5354]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1072] / [i915#9732]) +3 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3708]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-read: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#3291] / [i915#3708]) +2 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@prime_vgem@basic-read.html #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - {bat-mtlp-9}: [CRASH][20] -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732 Build changes ------------- * Linux: CI_DRM_14630 -> Patchwork_132285v3 CI-20190529: 20190529 CI_DRM_14630: d3410a305a38ffffd42343c3beba610f2ceca377 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7815: d5d516bfdf77898e934b4c7ed947a43711cfb226 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_132285v3: d3410a305a38ffffd42343c3beba610f2ceca377 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/index.html [-- Attachment #2: Type: text/html, Size: 8918 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula ` (7 preceding siblings ...) 2024-04-22 23:40 ` ✓ Fi.CI.BAT: success " Patchwork @ 2024-04-23 20:48 ` Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2024-04-23 20:48 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 90803 bytes --] == Series Details == Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) URL : https://patchwork.freedesktop.org/series/132285/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14630_full -> Patchwork_132285v3_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_132285v3_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_132285v3_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/index.html Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_132285v3_full: ### IGT changes ### #### Possible regressions #### * igt@sysfs_preempt_timeout@timeout@vcs0: - shard-dg1: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@sysfs_preempt_timeout@timeout@vcs0.html Known issues ------------ Here are the changes found in Patchwork_132285v3_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@object-reloc-keep-cache: - shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8411]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@api_intel_bb@object-reloc-keep-cache.html * igt@api_intel_bb@object-reloc-purge-cache: - shard-rkl: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@api_intel_bb@object-reloc-purge-cache.html * igt@core_hotunplug@unbind-rebind: - shard-mtlp: NOTRUN -> [ABORT][4] ([i915#10770]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@core_hotunplug@unbind-rebind.html * igt@debugfs_test@basic-hwmon: - shard-rkl: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@debugfs_test@basic-hwmon.html * igt@device_reset@cold-reset-bound: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#7701]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@device_reset@cold-reset-bound.html * igt@drm_fdinfo@all-busy-check-all: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +13 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@drm_fdinfo@all-busy-check-all.html - shard-dg1: NOTRUN -> [SKIP][8] ([i915#8414]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@drm_fdinfo@all-busy-check-all.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][9] -> [FAIL][10] ([i915#7742]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-5/igt@drm_fdinfo@most-busy-check-all@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][11] ([i915#9323]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@gem_ccs@block-multicopy-compressed.html * igt@gem_ccs@block-multicopy-inplace: - shard-dg1: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_ccs@block-multicopy-inplace.html * igt@gem_ccs@suspend-resume: - shard-tglu: NOTRUN -> [SKIP][13] ([i915#9323]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@gem_ccs@suspend-resume.html - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#9323]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_ccs@suspend-resume.html * igt@gem_close_race@multigpu-basic-process: - shard-mtlp: NOTRUN -> [SKIP][15] ([i915#7697]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_close_race@multigpu-basic-process.html - shard-dg1: NOTRUN -> [SKIP][16] ([i915#7697]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_close_race@multigpu-basic-process.html * igt@gem_create@create-ext-cpu-access-big: - shard-rkl: NOTRUN -> [SKIP][17] ([i915#6335]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_create@create-ext-set-pat: - shard-rkl: NOTRUN -> [SKIP][18] ([i915#8562]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_create@create-ext-set-pat.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][19] ([i915#8555]) +2 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-mtlp: NOTRUN -> [SKIP][20] ([i915#8555]) +1 other test skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_ctx_persistence@heartbeat-stop.html * igt@gem_ctx_sseu@engines: - shard-rkl: NOTRUN -> [SKIP][21] ([i915#280]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@gem_ctx_sseu@engines.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg1: NOTRUN -> [SKIP][22] ([i915#280]) +1 other test skip [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_ctx_sseu@invalid-sseu.html * igt@gem_ctx_sseu@mmap-args: - shard-mtlp: NOTRUN -> [SKIP][23] ([i915#280]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_ctx_sseu@mmap-args.html * igt@gem_eio@kms: - shard-dg1: NOTRUN -> [INCOMPLETE][24] ([i915#10513]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_eio@kms.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][25] ([i915#8555]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_exec_balancer@noheartbeat.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-rkl: NOTRUN -> [SKIP][26] ([i915#4525]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html * igt@gem_exec_capture@capture-invisible@smem0: - shard-rkl: NOTRUN -> [SKIP][27] ([i915#6334]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_exec_capture@capture-invisible@smem0.html * igt@gem_exec_capture@capture@vecs0-lmem0: - shard-dg2: NOTRUN -> [FAIL][28] ([i915#10386]) +3 other tests fail [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_exec_capture@capture@vecs0-lmem0.html - shard-dg1: NOTRUN -> [FAIL][29] ([i915#10386]) +1 other test fail [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_exec_capture@capture@vecs0-lmem0.html * igt@gem_exec_capture@many-4k-incremental: - shard-glk: NOTRUN -> [FAIL][30] ([i915#9606]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk1/igt@gem_exec_capture@many-4k-incremental.html * igt@gem_exec_fair@basic-deadline: - shard-rkl: NOTRUN -> [FAIL][31] ([i915#2846]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul: - shard-dg1: NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852]) +4 other tests skip [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_exec_fair@basic-none-rrul.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: NOTRUN -> [FAIL][33] ([i915#2842]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglu: [PASS][34] -> [FAIL][35] ([i915#2842]) +2 other tests fail [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-7/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-rkl: NOTRUN -> [FAIL][36] ([i915#2842]) +2 other tests fail [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-sync: - shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4473] / [i915#4771]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@gem_exec_fair@basic-sync.html - shard-dg1: NOTRUN -> [SKIP][38] ([i915#3539]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_exec_fair@basic-sync.html * igt@gem_exec_fence@concurrent: - shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4812]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_exec_fence@concurrent.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-dg2: NOTRUN -> [SKIP][40] ([i915#3539] / [i915#4852]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_reloc@basic-active: - shard-rkl: NOTRUN -> [SKIP][41] ([i915#3281]) +16 other tests skip [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@gem_exec_reloc@basic-active.html * igt@gem_exec_reloc@basic-gtt-cpu-noreloc: - shard-mtlp: NOTRUN -> [SKIP][42] ([i915#3281]) +10 other tests skip [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html * igt@gem_exec_reloc@basic-gtt-wc: - shard-dg2: NOTRUN -> [SKIP][43] ([i915#3281]) +1 other test skip [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_exec_reloc@basic-gtt-wc.html * igt@gem_exec_reloc@basic-wc-read-active: - shard-dg1: NOTRUN -> [SKIP][44] ([i915#3281]) +11 other tests skip [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_exec_reloc@basic-wc-read-active.html * igt@gem_exec_schedule@preempt-queue-contexts-chain: - shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4537] / [i915#4812]) +2 other tests skip [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@gem_exec_schedule@preempt-queue-contexts-chain.html * igt@gem_exec_schedule@reorder-wide: - shard-dg2: NOTRUN -> [SKIP][46] ([i915#4537] / [i915#4812]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html * igt@gem_exec_schedule@semaphore-power: - shard-dg1: NOTRUN -> [SKIP][47] ([i915#4812]) +2 other tests skip [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_exec_schedule@semaphore-power.html * igt@gem_exec_suspend@basic-s4-devices@smem: - shard-rkl: NOTRUN -> [ABORT][48] ([i915#7975] / [i915#8213]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@gem_exec_suspend@basic-s4-devices@smem.html * igt@gem_fence_thrash@bo-write-verify-threaded-none: - shard-dg1: NOTRUN -> [SKIP][49] ([i915#4860]) +1 other test skip [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_fence_thrash@bo-write-verify-threaded-none.html * igt@gem_fence_thrash@bo-write-verify-y: - shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4860]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@gem_fence_thrash@bo-write-verify-y.html * igt@gem_lmem_evict@dontneed-evict-race: - shard-tglu: NOTRUN -> [SKIP][51] ([i915#4613] / [i915#7582]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@gem_lmem_evict@dontneed-evict-race.html * igt@gem_lmem_swapping@heavy-verify-multi-ccs: - shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4613]) +5 other tests skip [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html * igt@gem_lmem_swapping@heavy-verify-random@lmem0: - shard-dg1: NOTRUN -> [FAIL][53] ([i915#10378]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglu: NOTRUN -> [SKIP][54] ([i915#4613]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@verify: - shard-rkl: NOTRUN -> [SKIP][55] ([i915#4613]) +1 other test skip [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_lmem_swapping@verify.html * igt@gem_lmem_swapping@verify-ccs: - shard-glk: NOTRUN -> [SKIP][56] ([i915#4613]) +2 other tests skip [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk1/igt@gem_lmem_swapping@verify-ccs.html * igt@gem_lmem_swapping@verify-random-ccs@lmem0: - shard-dg1: NOTRUN -> [SKIP][57] ([i915#4565]) +1 other test skip [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html * igt@gem_media_vme: - shard-dg2: NOTRUN -> [SKIP][58] ([i915#284]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_media_vme.html * igt@gem_mmap@big-bo: - shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4083]) +2 other tests skip [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_mmap@big-bo.html * igt@gem_mmap_gtt@cpuset-medium-copy: - shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4077]) +11 other tests skip [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_mmap_gtt@cpuset-medium-copy.html * igt@gem_mmap_gtt@medium-copy-odd: - shard-dg1: NOTRUN -> [SKIP][61] ([i915#4077]) +10 other tests skip [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_mmap_gtt@medium-copy-odd.html * igt@gem_mmap_wc@write-gtt-read-wc: - shard-dg2: NOTRUN -> [SKIP][62] ([i915#4083]) +1 other test skip [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_mmap_wc@write-gtt-read-wc.html * igt@gem_mmap_wc@write-read-distinct: - shard-dg1: NOTRUN -> [SKIP][63] ([i915#4083]) +5 other tests skip [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_mmap_wc@write-read-distinct.html * igt@gem_partial_pwrite_pread@writes-after-reads: - shard-dg2: NOTRUN -> [SKIP][64] ([i915#3282]) +1 other test skip [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_partial_pwrite_pread@writes-after-reads.html * igt@gem_pread@exhaustion: - shard-dg1: NOTRUN -> [SKIP][65] ([i915#3282]) +3 other tests skip [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_pread@exhaustion.html * igt@gem_pread@self: - shard-mtlp: NOTRUN -> [SKIP][66] ([i915#3282]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@gem_pread@self.html * igt@gem_pxp@create-protected-buffer: - shard-dg1: NOTRUN -> [SKIP][67] ([i915#4270]) +5 other tests skip [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_pxp@create-protected-buffer.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-tglu: NOTRUN -> [SKIP][68] ([i915#4270]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html * igt@gem_pxp@regular-baseline-src-copy-readible: - shard-rkl: NOTRUN -> [SKIP][69] ([i915#4270]) +2 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_pxp@regular-baseline-src-copy-readible.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-dg2: NOTRUN -> [SKIP][70] ([i915#4270]) +1 other test skip [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4270]) +3 other tests skip [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-mtlp: NOTRUN -> [SKIP][72] ([i915#8428]) +5 other tests skip [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@gem_render_copy@linear-to-vebox-y-tiled.html * igt@gem_render_copy@y-tiled: - shard-dg2: NOTRUN -> [SKIP][73] ([i915#5190] / [i915#8428]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_render_copy@y-tiled.html * igt@gem_set_tiling_vs_blt@untiled-to-tiled: - shard-dg1: NOTRUN -> [SKIP][74] ([i915#4079]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html * igt@gem_softpin@evict-snoop-interruptible: - shard-dg2: NOTRUN -> [SKIP][75] ([i915#4885]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_softpin@evict-snoop-interruptible.html - shard-dg1: NOTRUN -> [SKIP][76] ([i915#4885]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_tiled_partial_pwrite_pread@writes: - shard-dg2: NOTRUN -> [SKIP][77] ([i915#4077]) +4 other tests skip [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_tiled_partial_pwrite_pread@writes.html * igt@gem_userptr_blits@forbidden-operations: - shard-rkl: NOTRUN -> [SKIP][78] ([i915#3282]) +11 other tests skip [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@gem_userptr_blits@forbidden-operations.html * igt@gem_userptr_blits@unsync-unmap: - shard-dg1: NOTRUN -> [SKIP][79] ([i915#3297]) +2 other tests skip [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@gem_userptr_blits@unsync-unmap.html - shard-mtlp: NOTRUN -> [SKIP][80] ([i915#3297]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gem_userptr_blits@unsync-unmap.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-rkl: NOTRUN -> [SKIP][81] ([i915#3297]) +3 other tests skip [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@gen3_render_tiledy_blits: - shard-mtlp: NOTRUN -> [SKIP][82] +23 other tests skip [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gen3_render_tiledy_blits.html * igt@gen9_exec_parse@basic-rejected-ctx-param: - shard-dg2: NOTRUN -> [SKIP][83] ([i915#2856]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gen9_exec_parse@basic-rejected-ctx-param.html * igt@gen9_exec_parse@batch-without-end: - shard-mtlp: NOTRUN -> [SKIP][84] ([i915#2856]) +3 other tests skip [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@gen9_exec_parse@batch-without-end.html * igt@gen9_exec_parse@bb-chained: - shard-tglu: NOTRUN -> [SKIP][85] ([i915#2527] / [i915#2856]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@gen9_exec_parse@bb-chained.html * igt@gen9_exec_parse@bb-secure: - shard-dg1: NOTRUN -> [SKIP][86] ([i915#2527]) +3 other tests skip [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@gen9_exec_parse@bb-secure.html * igt@gen9_exec_parse@bb-start-out: - shard-rkl: NOTRUN -> [SKIP][87] ([i915#2527]) +5 other tests skip [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html * igt@i915_module_load@reload-with-fault-injection: - shard-rkl: [PASS][88] -> [ABORT][89] ([i915#9820]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html - shard-dg2: [PASS][90] -> [INCOMPLETE][91] ([i915#9820] / [i915#9849]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_module_load@resize-bar: - shard-rkl: NOTRUN -> [SKIP][92] ([i915#6412]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@i915_module_load@resize-bar.html * igt@i915_pipe_stress@stress-xrgb8888-ytiled: - shard-mtlp: NOTRUN -> [SKIP][93] ([i915#8436]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html * igt@i915_pm_freq_api@freq-reset-multiple: - shard-rkl: NOTRUN -> [SKIP][94] ([i915#8399]) +1 other test skip [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@i915_pm_freq_api@freq-reset-multiple.html * igt@i915_pm_freq_mult@media-freq@gt0: - shard-dg1: NOTRUN -> [SKIP][95] ([i915#6590]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@i915_pm_freq_mult@media-freq@gt0.html * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0: - shard-dg1: [PASS][96] -> [FAIL][97] ([i915#3591]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html * igt@i915_pm_rpm@gem-mmap-type@gtt-smem0: - shard-mtlp: NOTRUN -> [SKIP][98] ([i915#8431]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-7/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html * igt@i915_pm_rps@thresholds-park@gt0: - shard-dg1: NOTRUN -> [SKIP][99] ([i915#8925]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@i915_pm_rps@thresholds-park@gt0.html - shard-mtlp: NOTRUN -> [SKIP][100] ([i915#8925]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@i915_pm_rps@thresholds-park@gt0.html * igt@i915_pm_rps@thresholds-park@gt1: - shard-mtlp: NOTRUN -> [SKIP][101] ([i915#3555] / [i915#8925]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@i915_pm_rps@thresholds-park@gt1.html * igt@i915_pm_sseu@full-enable: - shard-dg1: NOTRUN -> [SKIP][102] ([i915#4387]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@i915_pm_sseu@full-enable.html - shard-mtlp: NOTRUN -> [SKIP][103] ([i915#8437]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@i915_pm_sseu@full-enable.html * igt@i915_power@sanity: - shard-mtlp: NOTRUN -> [SKIP][104] ([i915#7984]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@i915_power@sanity.html * igt@i915_query@test-query-geometry-subslices: - shard-rkl: NOTRUN -> [SKIP][105] ([i915#5723]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@i915_query@test-query-geometry-subslices.html * igt@i915_selftest@mock@memory_region: - shard-rkl: NOTRUN -> [DMESG-WARN][106] ([i915#9311]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@i915_selftest@mock@memory_region.html * igt@intel_hwmon@hwmon-write: - shard-mtlp: NOTRUN -> [SKIP][107] ([i915#7707]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@intel_hwmon@hwmon-write.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-mtlp: [PASS][108] -> [FAIL][109] ([i915#2521]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs: - shard-dg1: NOTRUN -> [SKIP][110] ([i915#8709]) +7 other tests skip [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs: - shard-dg2: NOTRUN -> [SKIP][111] ([i915#8709]) +11 other tests skip [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html * igt@kms_async_flips@invalid-async-flip: - shard-mtlp: NOTRUN -> [SKIP][112] ([i915#6228]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_async_flips@invalid-async-flip.html * igt@kms_atomic_transition@plane-all-modeset-transition: - shard-mtlp: NOTRUN -> [SKIP][113] ([i915#1769] / [i915#3555]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_atomic_transition@plane-all-modeset-transition.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels: - shard-rkl: NOTRUN -> [SKIP][114] ([i915#1769] / [i915#3555]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html * igt@kms_big_fb@4-tiled-addfb-size-overflow: - shard-dg1: NOTRUN -> [SKIP][115] ([i915#5286]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_big_fb@4-tiled-addfb-size-overflow.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-rkl: NOTRUN -> [SKIP][116] ([i915#5286]) +9 other tests skip [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-dg1: NOTRUN -> [SKIP][117] ([i915#4538] / [i915#5286]) +7 other tests skip [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-tglu: NOTRUN -> [SKIP][118] ([i915#5286]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-rkl: NOTRUN -> [SKIP][119] ([i915#3638]) +5 other tests skip [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-64bpp-rotate-270: - shard-dg1: NOTRUN -> [SKIP][120] ([i915#3638]) +5 other tests skip [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html * igt@kms_big_fb@y-tiled-8bpp-rotate-90: - shard-dg2: NOTRUN -> [SKIP][121] ([i915#4538] / [i915#5190]) +2 other tests skip [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0: - shard-dg1: NOTRUN -> [SKIP][122] ([i915#4538]) +6 other tests skip [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html * igt@kms_big_joiner@invalid-modeset: - shard-mtlp: NOTRUN -> [SKIP][123] ([i915#10656]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_big_joiner@invalid-modeset.html * igt@kms_big_joiner@invalid-modeset-force-joiner: - shard-dg2: NOTRUN -> [SKIP][124] ([i915#10656]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_big_joiner@invalid-modeset-force-joiner.html - shard-dg1: NOTRUN -> [SKIP][125] ([i915#10656]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_big_joiner@invalid-modeset-force-joiner.html * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1: - shard-dg2: NOTRUN -> [SKIP][126] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][127] ([i915#6095]) +49 other tests skip [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-1.html * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][128] ([i915#6095]) +11 other tests skip [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][129] ([i915#6095]) +55 other tests skip [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-hdmi-a-4.html * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][130] ([i915#6095]) +27 other tests skip [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-edp-1.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs: - shard-rkl: NOTRUN -> [SKIP][131] ([i915#10278]) +2 other tests skip [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4: - shard-dg2: NOTRUN -> [SKIP][132] ([i915#10307] / [i915#6095]) +132 other tests skip [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4.html * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][133] ([i915#7213]) +3 other tests skip [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-5/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html * igt@kms_cdclk@plane-scaling: - shard-rkl: NOTRUN -> [SKIP][134] ([i915#3742]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_cdclk@plane-scaling.html * igt@kms_chamelium_frames@dp-crc-multiple: - shard-tglu: NOTRUN -> [SKIP][135] ([i915#7828]) +1 other test skip [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_chamelium_frames@dp-crc-multiple.html * igt@kms_chamelium_hpd@dp-hpd: - shard-rkl: NOTRUN -> [SKIP][136] ([i915#7828]) +14 other tests skip [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd.html * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable: - shard-dg1: NOTRUN -> [SKIP][137] ([i915#7828]) +9 other tests skip [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html * igt@kms_chamelium_hpd@vga-hpd-after-suspend: - shard-dg2: NOTRUN -> [SKIP][138] ([i915#7828]) +1 other test skip [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode: - shard-mtlp: NOTRUN -> [SKIP][139] ([i915#7828]) +8 other tests skip [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html * igt@kms_content_protection@atomic@pipe-a-dp-4: - shard-dg2: NOTRUN -> [TIMEOUT][140] ([i915#7173]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html * igt@kms_content_protection@dp-mst-type-1: - shard-dg1: NOTRUN -> [SKIP][141] ([i915#3299]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_content_protection@dp-mst-type-1.html - shard-mtlp: NOTRUN -> [SKIP][142] ([i915#3299]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@lic-type-0: - shard-mtlp: NOTRUN -> [SKIP][143] ([i915#6944] / [i915#9424]) +1 other test skip [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_content_protection@lic-type-0.html * igt@kms_content_protection@mei-interface: - shard-dg1: NOTRUN -> [SKIP][144] ([i915#9424]) +2 other tests skip [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_content_protection@mei-interface.html - shard-mtlp: NOTRUN -> [SKIP][145] ([i915#8063] / [i915#9433]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_content_protection@mei-interface.html * igt@kms_content_protection@type1: - shard-rkl: NOTRUN -> [SKIP][146] ([i915#7118] / [i915#9424]) +2 other tests skip [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_content_protection@type1.html * igt@kms_cursor_crc@cursor-offscreen-32x32: - shard-dg2: NOTRUN -> [SKIP][147] ([i915#3555]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_cursor_crc@cursor-offscreen-32x32.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-mtlp: NOTRUN -> [SKIP][148] ([i915#3359]) +2 other tests skip [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_cursor_crc@cursor-onscreen-512x512.html - shard-dg1: NOTRUN -> [SKIP][149] ([i915#3359]) +1 other test skip [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_crc@cursor-random-128x42: - shard-mtlp: NOTRUN -> [SKIP][150] ([i915#8814]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_cursor_crc@cursor-random-128x42.html * igt@kms_cursor_crc@cursor-random-512x170: - shard-rkl: NOTRUN -> [SKIP][151] ([i915#3359]) +1 other test skip [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html * igt@kms_cursor_crc@cursor-random-max-size: - shard-mtlp: NOTRUN -> [SKIP][152] ([i915#3555] / [i915#8814]) [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_cursor_crc@cursor-random-max-size.html * igt@kms_cursor_crc@cursor-rapid-movement-32x10: - shard-rkl: NOTRUN -> [SKIP][153] ([i915#3555]) +7 other tests skip [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html * igt@kms_cursor_crc@cursor-rapid-movement-512x512: - shard-tglu: NOTRUN -> [SKIP][154] ([i915#3359]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-dg2: NOTRUN -> [SKIP][155] ([i915#5354]) +6 other tests skip [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: - shard-mtlp: NOTRUN -> [SKIP][156] ([i915#9809]) +3 other tests skip [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size: - shard-rkl: NOTRUN -> [SKIP][157] ([i915#4103]) +1 other test skip [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions: - shard-mtlp: NOTRUN -> [SKIP][158] ([i915#4213]) +1 other test skip [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html - shard-dg1: NOTRUN -> [SKIP][159] ([i915#4103] / [i915#4213]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html * igt@kms_cursor_legacy@torture-bo@pipe-a: - shard-dg1: [PASS][160] -> [DMESG-WARN][161] ([i915#10166]) [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg1-16/igt@kms_cursor_legacy@torture-bo@pipe-a.html [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-17/igt@kms_cursor_legacy@torture-bo@pipe-a.html * igt@kms_dirtyfb@drrs-dirtyfb-ioctl: - shard-rkl: NOTRUN -> [SKIP][162] ([i915#9723]) [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2: - shard-dg2: NOTRUN -> [SKIP][163] ([i915#9227]) [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][164] ([i915#9723]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html * igt@kms_display_modes@mst-extended-mode-negative: - shard-dg1: NOTRUN -> [SKIP][165] ([i915#8588]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_display_modes@mst-extended-mode-negative.html * igt@kms_dp_aux_dev: - shard-rkl: NOTRUN -> [SKIP][166] ([i915#1257]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@kms_dp_aux_dev.html * igt@kms_dsc@dsc-fractional-bpp: - shard-tglu: NOTRUN -> [SKIP][167] ([i915#3840]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_dsc@dsc-fractional-bpp.html - shard-mtlp: NOTRUN -> [SKIP][168] ([i915#3840] / [i915#9688]) [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_dsc@dsc-fractional-bpp.html * igt@kms_dsc@dsc-fractional-bpp-with-bpc: - shard-dg1: NOTRUN -> [SKIP][169] ([i915#3840]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html - shard-mtlp: NOTRUN -> [SKIP][170] ([i915#3840]) [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html * igt@kms_dsc@dsc-with-bpc: - shard-dg2: NOTRUN -> [SKIP][171] ([i915#3555] / [i915#3840]) [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_dsc@dsc-with-bpc.html * igt@kms_dsc@dsc-with-formats: - shard-dg1: NOTRUN -> [SKIP][172] ([i915#3555] / [i915#3840]) +1 other test skip [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_dsc@dsc-with-formats.html * igt@kms_dsc@dsc-with-output-formats-with-bpc: - shard-rkl: NOTRUN -> [SKIP][173] ([i915#3840] / [i915#9053]) [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats-with-bpc.html * igt@kms_fbcon_fbt@psr-suspend: - shard-rkl: NOTRUN -> [SKIP][174] ([i915#3955]) [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_feature_discovery@chamelium: - shard-rkl: NOTRUN -> [SKIP][175] ([i915#4854]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_feature_discovery@chamelium.html * igt@kms_feature_discovery@display-2x: - shard-rkl: NOTRUN -> [SKIP][176] ([i915#1839]) [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_feature_discovery@display-2x.html * igt@kms_feature_discovery@psr1: - shard-rkl: NOTRUN -> [SKIP][177] ([i915#658]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_feature_discovery@psr1.html * igt@kms_feature_discovery@psr2: - shard-dg1: NOTRUN -> [SKIP][178] ([i915#658]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_feature_discovery@psr2.html * igt@kms_fence_pin_leak: - shard-dg1: NOTRUN -> [SKIP][179] ([i915#4881]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_fence_pin_leak.html - shard-mtlp: NOTRUN -> [SKIP][180] ([i915#4881]) [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_fence_pin_leak.html * igt@kms_flip@2x-flip-vs-dpms: - shard-rkl: NOTRUN -> [SKIP][181] +63 other tests skip [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@kms_flip@2x-flip-vs-dpms.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-dg2: NOTRUN -> [SKIP][182] +2 other tests skip [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-flip-vs-rmfb-interruptible: - shard-mtlp: NOTRUN -> [SKIP][183] ([i915#3637]) +8 other tests skip [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-7/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check-interruptible: - shard-dg1: NOTRUN -> [SKIP][184] ([i915#9934]) +7 other tests skip [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html * igt@kms_flip@wf_vblank-ts-check@a-hdmi-a1: - shard-rkl: NOTRUN -> [FAIL][185] ([i915#2122]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a1.html * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][186] ([i915#2672]) [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][187] ([i915#2672]) +6 other tests skip [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][188] ([i915#2672]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode: - shard-dg1: NOTRUN -> [SKIP][189] ([i915#2587] / [i915#2672]) +3 other tests skip [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][190] ([i915#2672] / [i915#3555]) +2 other tests skip [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt: - shard-rkl: NOTRUN -> [SKIP][191] ([i915#1825]) +55 other tests skip [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt: - shard-dg1: NOTRUN -> [SKIP][192] +51 other tests skip [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-dg2: NOTRUN -> [SKIP][193] ([i915#8708]) +7 other tests skip [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc: - shard-tglu: NOTRUN -> [SKIP][194] +21 other tests skip [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][195] ([i915#8708]) +7 other tests skip [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@plane-fbc-rte: - shard-dg1: NOTRUN -> [SKIP][196] ([i915#10070]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_frontbuffer_tracking@plane-fbc-rte.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-dg1: NOTRUN -> [SKIP][197] ([i915#8708]) +28 other tests skip [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move: - shard-dg2: NOTRUN -> [SKIP][198] ([i915#3458]) +2 other tests skip [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt: - shard-mtlp: NOTRUN -> [SKIP][199] ([i915#1825]) +35 other tests skip [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@psr-modesetfrombusy: - shard-rkl: NOTRUN -> [SKIP][200] ([i915#3023]) +39 other tests skip [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-dg1: NOTRUN -> [SKIP][201] ([i915#3458]) +18 other tests skip [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch-dpms: - shard-dg1: NOTRUN -> [SKIP][202] ([i915#3555] / [i915#8228]) +1 other test skip [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_hdr@invalid-metadata-sizes: - shard-mtlp: NOTRUN -> [SKIP][203] ([i915#3555] / [i915#8228]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_hdr@invalid-metadata-sizes.html - shard-tglu: NOTRUN -> [SKIP][204] ([i915#3555] / [i915#8228]) [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_hdr@invalid-metadata-sizes.html * igt@kms_hdr@static-swap: - shard-dg2: NOTRUN -> [SKIP][205] ([i915#3555] / [i915#8228]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_hdr@static-swap.html * igt@kms_hdr@static-toggle-suspend: - shard-rkl: NOTRUN -> [SKIP][206] ([i915#3555] / [i915#8228]) +1 other test skip [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_hdr@static-toggle-suspend.html * igt@kms_panel_fitting@atomic-fastset: - shard-rkl: NOTRUN -> [SKIP][207] ([i915#6301]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_panel_fitting@atomic-fastset.html * igt@kms_panel_fitting@legacy: - shard-dg1: NOTRUN -> [SKIP][208] ([i915#6301]) [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_panel_fitting@legacy.html * igt@kms_plane_lowres@tiling-yf: - shard-dg1: NOTRUN -> [SKIP][209] ([i915#3555]) +3 other tests skip [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2: - shard-dg2: NOTRUN -> [SKIP][210] ([i915#9423]) +7 other tests skip [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][211] +214 other tests skip [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][212] ([i915#5176]) +3 other tests skip [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-edp-1.html * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][213] ([i915#9423]) +19 other tests skip [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][214] ([i915#9423]) +1 other test skip [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][215] ([i915#5176] / [i915#9423]) +1 other test skip [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][216] ([i915#5235] / [i915#9423]) +11 other tests skip [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2: - shard-dg2: NOTRUN -> [SKIP][217] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][218] ([i915#5235]) +7 other tests skip [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][219] ([i915#5235]) +16 other tests skip [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][220] ([i915#5235]) +5 other tests skip [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][221] ([i915#3555] / [i915#5235]) +2 other tests skip [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html * igt@kms_pm_backlight@basic-brightness: - shard-rkl: NOTRUN -> [SKIP][222] ([i915#5354]) +1 other test skip [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_pm_backlight@basic-brightness.html * igt@kms_pm_dc@dc5-dpms-negative: - shard-mtlp: NOTRUN -> [SKIP][223] ([i915#9293]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@kms_pm_dc@dc5-dpms-negative.html * igt@kms_pm_dc@dc6-dpms: - shard-rkl: NOTRUN -> [SKIP][224] ([i915#3361]) [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@kms_pm_dc@dc6-dpms.html * igt@kms_pm_dc@dc6-psr: - shard-rkl: NOTRUN -> [SKIP][225] ([i915#9685]) [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_pm_dc@dc6-psr.html * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp: - shard-rkl: NOTRUN -> [SKIP][226] ([i915#9519]) [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@kms_pm_rpm@modeset-non-lpsp: - shard-mtlp: NOTRUN -> [SKIP][227] ([i915#9519]) +1 other test skip [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_pm_rpm@modeset-non-lpsp.html - shard-dg2: [PASS][228] -> [SKIP][229] ([i915#9519]) [228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp.html [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp.html * igt@kms_prime@d3hot: - shard-rkl: NOTRUN -> [SKIP][230] ([i915#6524]) +1 other test skip [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_prime@d3hot.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-mtlp: NOTRUN -> [SKIP][231] ([i915#4348]) +1 other test skip [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html - shard-tglu: NOTRUN -> [SKIP][232] ([i915#9683]) [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-nv12: - shard-dg2: NOTRUN -> [SKIP][233] ([i915#9683]) [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr2_su@page_flip-p010: - shard-dg1: NOTRUN -> [SKIP][234] ([i915#9683]) +1 other test skip [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_psr2_su@page_flip-p010.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-rkl: NOTRUN -> [SKIP][235] ([i915#9683]) [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@fbc-psr-cursor-plane-move: - shard-dg2: NOTRUN -> [SKIP][236] ([i915#1072] / [i915#9732]) +4 other tests skip [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_psr@fbc-psr-cursor-plane-move.html * igt@kms_psr@pr-primary-mmap-cpu: - shard-mtlp: NOTRUN -> [SKIP][237] ([i915#9688]) +9 other tests skip [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_psr@pr-primary-mmap-cpu.html * igt@kms_psr@pr-sprite-mmap-cpu: - shard-tglu: NOTRUN -> [SKIP][238] ([i915#9732]) +4 other tests skip [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_psr@pr-sprite-mmap-cpu.html * igt@kms_psr@psr2-sprite-mmap-gtt: - shard-dg1: NOTRUN -> [SKIP][239] ([i915#1072] / [i915#9732]) +23 other tests skip [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html * igt@kms_psr@psr2-sprite-mmap-gtt@edp-1: - shard-mtlp: NOTRUN -> [SKIP][240] ([i915#4077] / [i915#9688]) [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_psr@psr2-sprite-mmap-gtt@edp-1.html * igt@kms_psr@psr2-suspend: - shard-rkl: NOTRUN -> [SKIP][241] ([i915#1072] / [i915#9732]) +31 other tests skip [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@kms_psr@psr2-suspend.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-dg1: NOTRUN -> [SKIP][242] ([i915#9685]) +1 other test skip [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@kms_rotation_crc@bad-tiling: - shard-mtlp: NOTRUN -> [SKIP][243] ([i915#4235]) +2 other tests skip [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_rotation_crc@bad-tiling.html * igt@kms_rotation_crc@exhaust-fences: - shard-dg1: NOTRUN -> [SKIP][244] ([i915#4884]) [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_rotation_crc@exhaust-fences.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-dg2: NOTRUN -> [SKIP][245] ([i915#4235] / [i915#5190]) [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-mtlp: NOTRUN -> [SKIP][246] ([i915#5289]) [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90: - shard-rkl: NOTRUN -> [SKIP][247] ([i915#5289]) +2 other tests skip [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html * igt@kms_setmode@invalid-clone-single-crtc-stealing: - shard-mtlp: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8809]) [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_setmode@invalid-clone-single-crtc-stealing.html * igt@kms_tiled_display@basic-test-pattern: - shard-dg1: NOTRUN -> [SKIP][249] ([i915#8623]) [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_tiled_display@basic-test-pattern.html - shard-dg2: NOTRUN -> [SKIP][250] ([i915#8623]) [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-mtlp: NOTRUN -> [SKIP][251] ([i915#8623]) [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1: - shard-mtlp: [PASS][252] -> [FAIL][253] ([i915#9196]) [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-2: - shard-dg2: NOTRUN -> [FAIL][254] ([i915#9196]) [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-2.html * igt@kms_vrr@flip-basic: - shard-tglu: NOTRUN -> [SKIP][255] ([i915#3555]) [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@kms_vrr@flip-basic.html - shard-mtlp: NOTRUN -> [SKIP][256] ([i915#3555] / [i915#8808]) [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@kms_vrr@flip-basic.html * igt@kms_vrr@seamless-rr-switch-drrs: - shard-rkl: NOTRUN -> [SKIP][257] ([i915#9906]) +1 other test skip [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-drrs.html * igt@kms_writeback@writeback-fb-id: - shard-rkl: NOTRUN -> [SKIP][258] ([i915#2437]) +1 other test skip [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_writeback@writeback-fb-id.html * igt@kms_writeback@writeback-fb-id-xrgb2101010: - shard-dg1: NOTRUN -> [SKIP][259] ([i915#2437] / [i915#9412]) [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@kms_writeback@writeback-fb-id-xrgb2101010.html * igt@perf@per-context-mode-unprivileged: - shard-rkl: NOTRUN -> [SKIP][260] ([i915#2435]) [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html * igt@perf_pmu@cpu-hotplug: - shard-dg1: NOTRUN -> [SKIP][261] ([i915#8850]) [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-15/igt@perf_pmu@cpu-hotplug.html * igt@perf_pmu@faulting-read@gtt: - shard-mtlp: NOTRUN -> [SKIP][262] ([i915#8440]) [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@perf_pmu@faulting-read@gtt.html * igt@perf_pmu@frequency@gt0: - shard-dg1: NOTRUN -> [FAIL][263] ([i915#6806]) [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@perf_pmu@frequency@gt0.html * igt@perf_pmu@rc6@other-idle-gt0: - shard-rkl: NOTRUN -> [SKIP][264] ([i915#8516]) [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@perf_pmu@rc6@other-idle-gt0.html * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: - shard-dg2: NOTRUN -> [INCOMPLETE][265] ([i915#5493]) [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html * igt@prime_vgem@basic-write: - shard-rkl: NOTRUN -> [SKIP][266] ([i915#3291] / [i915#3708]) [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@prime_vgem@basic-write.html * igt@prime_vgem@coherency-gtt: - shard-rkl: NOTRUN -> [SKIP][267] ([i915#3708]) +1 other test skip [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@prime_vgem@coherency-gtt.html * igt@prime_vgem@fence-flip-hang: - shard-dg1: NOTRUN -> [SKIP][268] ([i915#3708]) +1 other test skip [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@prime_vgem@fence-flip-hang.html * igt@prime_vgem@fence-read-hang: - shard-mtlp: NOTRUN -> [SKIP][269] ([i915#3708]) [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-3/igt@prime_vgem@fence-read-hang.html * igt@sriov_basic@enable-vfs-bind-unbind-each: - shard-mtlp: NOTRUN -> [SKIP][270] ([i915#9917]) [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@sriov_basic@enable-vfs-bind-unbind-each.html * igt@syncobj_timeline@invalid-wait-zero-handles: - shard-glk: NOTRUN -> [FAIL][271] ([i915#9781]) [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk2/igt@syncobj_timeline@invalid-wait-zero-handles.html - shard-mtlp: NOTRUN -> [FAIL][272] ([i915#9781]) [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@syncobj_timeline@invalid-wait-zero-handles.html * igt@tools_test@sysfs_l3_parity: - shard-dg1: NOTRUN -> [SKIP][273] ([i915#4818]) [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@tools_test@sysfs_l3_parity.html - shard-mtlp: NOTRUN -> [SKIP][274] ([i915#4818]) [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-7/igt@tools_test@sysfs_l3_parity.html * igt@v3d/v3d_perfmon@create-perfmon-invalid-counters: - shard-mtlp: NOTRUN -> [SKIP][275] ([i915#2575]) +8 other tests skip [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-2/igt@v3d/v3d_perfmon@create-perfmon-invalid-counters.html * igt@v3d/v3d_perfmon@get-values-invalid-pointer: - shard-dg1: NOTRUN -> [SKIP][276] ([i915#2575]) +13 other tests skip [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html * igt@v3d/v3d_submit_cl@bad-flag: - shard-tglu: NOTRUN -> [SKIP][277] ([i915#2575]) +3 other tests skip [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-9/igt@v3d/v3d_submit_cl@bad-flag.html * igt@v3d/v3d_submit_csd@multisync-out-syncs: - shard-dg2: NOTRUN -> [SKIP][278] ([i915#2575]) +2 other tests skip [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@v3d/v3d_submit_csd@multisync-out-syncs.html * igt@vc4/vc4_create_bo@create-bo-4096: - shard-mtlp: NOTRUN -> [SKIP][279] ([i915#7711]) +7 other tests skip [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-5/igt@vc4/vc4_create_bo@create-bo-4096.html * igt@vc4/vc4_create_bo@create-bo-zeroed: - shard-rkl: NOTRUN -> [SKIP][280] ([i915#7711]) +13 other tests skip [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-1/igt@vc4/vc4_create_bo@create-bo-zeroed.html * igt@vc4/vc4_wait_bo@unused-bo-0ns: - shard-dg1: NOTRUN -> [SKIP][281] ([i915#7711]) +9 other tests skip [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@vc4/vc4_wait_bo@unused-bo-0ns.html * igt@vc4/vc4_wait_seqno@bad-seqno-0ns: - shard-dg2: NOTRUN -> [SKIP][282] ([i915#7711]) +1 other test skip [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@vc4/vc4_wait_seqno@bad-seqno-0ns.html #### Possible fixes #### * igt@gem_eio@reset-stress: - shard-dg2: [FAIL][283] ([i915#5784]) -> [PASS][284] [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-2/igt@gem_eio@reset-stress.html [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@gem_eio@reset-stress.html * igt@gem_exec_fair@basic-none@vecs0: - shard-rkl: [FAIL][285] ([i915#2842]) -> [PASS][286] +3 other tests pass [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-3/igt@gem_exec_fair@basic-none@vecs0.html [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglu: [FAIL][287] ([i915#2842]) -> [PASS][288] +1 other test pass [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-tglu-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-10/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@i915_module_load@reload-with-fault-injection: - shard-dg1: [INCOMPLETE][289] ([i915#9820] / [i915#9849]) -> [PASS][290] [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html - shard-mtlp: [ABORT][291] ([i915#10131] / [i915#9820]) -> [PASS][292] [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-tglu: [FAIL][293] ([i915#2346]) -> [PASS][294] [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-tglu-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-tglu-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a1-hdmi-a2: - shard-glk: [INCOMPLETE][295] -> [PASS][296] [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-glk3/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a1-hdmi-a2.html [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-glk4/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1: - shard-snb: [FAIL][297] ([i915#10826]) -> [PASS][298] [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-snb7/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-snb7/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1: - shard-rkl: [FAIL][299] ([i915#2122]) -> [PASS][300] [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html * igt@kms_pm_rpm@modeset-non-lpsp-stress: - shard-dg2: [SKIP][301] ([i915#9519]) -> [PASS][302] +2 other tests pass [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html #### Warnings #### * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: [INCOMPLETE][303] ([i915#9364]) -> [ABORT][304] ([i915#9846]) [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-5/igt@gem_create@create-ext-cpu-access-big.html [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - shard-dg1: [SKIP][305] ([i915#4212]) -> [SKIP][306] ([i915#4212] / [i915#4423]) [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg1-18/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg1-16/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-dg2: [SKIP][307] ([i915#3458]) -> [SKIP][308] ([i915#10433] / [i915#3458]) [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-dg2: [SKIP][309] ([i915#10433] / [i915#3458]) -> [SKIP][310] ([i915#3458]) [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-rkl: [SKIP][311] ([i915#4816]) -> [SKIP][312] ([i915#4070] / [i915#4816]) [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_pm_dc@dc9-dpms: - shard-rkl: [SKIP][313] ([i915#4281]) -> [SKIP][314] ([i915#3361]) [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-rkl-4/igt@kms_pm_dc@dc9-dpms.html * igt@kms_psr@fbc-pr-cursor-render: - shard-dg2: [SKIP][315] ([i915#1072] / [i915#9732]) -> [SKIP][316] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-10/igt@kms_psr@fbc-pr-cursor-render.html [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-11/igt@kms_psr@fbc-pr-cursor-render.html * igt@kms_psr@psr2-primary-mmap-gtt: - shard-dg2: [SKIP][317] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][318] ([i915#1072] / [i915#9732]) +5 other tests skip [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/shard-dg2-8/igt@kms_psr@psr2-primary-mmap-gtt.html [i915#10070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10070 [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131 [i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166 [i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278 [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307 [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 [i915#10386]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10386 [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433 [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434 [i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513 [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656 [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072 [i915#10770]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10770 [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826 [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257 [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769 [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839 [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122 [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346 [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435 [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672 [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846 [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299 [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638 [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708 [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840 [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213 [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281 [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348 [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387 [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423 [i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473 [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525 [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537 [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538 [i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816 [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818 [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852 [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854 [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860 [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4884 [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885 [i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190 [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289 [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354 [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493 [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723 [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095 [i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228 [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301 [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334 [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412 [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590 [i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806 [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944 [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118 [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173 [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213 [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582 [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697 [i915#7701]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7701 [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707 [i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828 [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975 [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984 [i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063 [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228 [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399 [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428 [i915#8431]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8431 [i915#8436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8436 [i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437 [i915#8440]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8440 [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516 [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555 [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562 [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588 [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623 [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709 [i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808 [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809 [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814 [i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850 [i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925 [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053 [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196 [i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227 [i915#9293]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9293 [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311 [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318 [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323 [i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364 [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412 [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423 [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424 [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433 [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519 [i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606 [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673 [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683 [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685 [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688 [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723 [i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728 [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732 [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781 [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809 [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820 [i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846 [i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849 [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906 [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917 [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934 Build changes ------------- * Linux: CI_DRM_14630 -> Patchwork_132285v3 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_14630: d3410a305a38ffffd42343c3beba610f2ceca377 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7815: d5d516bfdf77898e934b4c7ed947a43711cfb226 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_132285v3: d3410a305a38ffffd42343c3beba610f2ceca377 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/index.html [-- Attachment #2: Type: text/html, Size: 112072 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-04-23 20:48 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-04-19 10:04 [PATCH v2 0/4] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula 2024-04-19 10:04 ` [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula 2024-04-22 20:59 ` Rodrigo Vivi 2024-04-23 14:41 ` Jani Nikula 2024-04-19 10:04 ` [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula 2024-04-22 21:00 ` Rodrigo Vivi 2024-04-19 10:04 ` [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage Jani Nikula 2024-04-22 21:07 ` Rodrigo Vivi 2024-04-19 10:04 ` [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable Jani Nikula 2024-04-22 21:10 ` Rodrigo Vivi 2024-04-22 21:16 ` Gustavo Sousa 2024-04-22 21:21 ` Rodrigo Vivi 2024-04-19 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev2) Patchwork 2024-04-19 10:53 ` ✗ Fi.CI.BAT: failure " Patchwork 2024-04-19 12:04 ` Jani Nikula 2024-04-22 23:33 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3) Patchwork 2024-04-22 23:40 ` ✓ Fi.CI.BAT: success " Patchwork 2024-04-23 20:48 ` ✗ Fi.CI.IGT: failure " Patchwork
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