[PATCH 00/16] Account for DSC bubble overhead for horizontal slices

[PATCH 00/16] Account for DSC bubble overhead for horizontal slices

[Ankit Nautiyal]

When DSC is enabled on a pipe, the pipe pixel rate input to cdclk frequency
and pipe joiner calculations needs to be adjusted to account for
compression overhead: specifically, the "bubbles" added at each horizontal
slice boundary. This overhead has always existed, even on earlier
platforms, but was not previously accounted for.

Currently, the number of joined pipes is computed much earlier than the
decision to use DSC: both during the mode_valid phase for each mode and in
the compute_config phase for a given mode. As a result, the DSC bubble
overhead cannot be considered when determining the number of pipes to join,
which may lead to incorrect configurations.

This series refactors the sequence of steps used to determine the number of
pipes to be joined and the DSC policy. The first few patches restructure
the mode_valid and compute config logic to make room for DSC bubble
overhead accounting. With these, we iterate over joiner candidates and
select the minimal joiner configuration that satisfies the
mode-requirements. The later patches introduce the actual overhead
adjustment and use it for: the minimum cdclk requirements with DSC,
SST mode_valid logic, and SST/MST compute_config logic.

Rev 2:
 - Refactor joiner computation for compute config.
 - Refactor DSC BW calculation.
 - Add overhead for SST/MST compute config phase for recomputing joiner
   requirements for DSC.
 - NOTE:
   - For Patch#7 (drm/i915/dp: Rework pipe joiner logic in mode_valid)
     git diff = --patience is used for better readability.

Rev 3:
 - Use diff = --patience in format-patch for better readability.
 - Add a macro to iterate over the joiner candidates.
 - Add a separate helper to check pixel rate against dotclock limit.
 - Add patch from Chaitanya for additional platform specific
   limitations [1].

[1] https://patchwork.freedesktop.org/patch/661952/?series=151047&rev=1

Rev 4:
 - Address review comments from Jani and Imre.
 - Drop enum for joiner candidates and iterate over num of pipes joined.
 - Rename some of the helpers.
 - Split the patch to check for pixel limit for max uncompressed
   dotclock into PTL and other platforms. For PTL the bspec and HSDES
   matches, but for other platforms need to confirm the need for the
   limits.

Ankit Nautiyal (14):
  drm/i915/dp: Early reject bad hdisplay in intel_dp_mode_valid
  drm/i915/dp: Move num_joined_pipes and related checks together
  drm/i915/dp: Extract helper to get the hdisplay limit
  drm/i915/dp: Rework pipe joiner logic in mode_valid
  drm/i915/dp: Rework pipe joiner logic in compute_config
  drm/i915/dp_mst: Move the check for dotclock at the end
  drm/i915/dp_mst: Move the joiner dependent code together
  drm/i915/dp_mst: Rework pipe joiner logic in mode_valid
  drm/i915/dp_mst: Extract helper to compute link for given joiner
    config
  drm/i915/dp_mst: Rework pipe joiner logic in compute_config
  drm/i915/dp: Introduce helper to check pixel rate against dotclock
    limits
  drm/i915/dp: Refactor dsc_slice_count handling in
    intel_dp_mode_valid()
  drm/i915/dp: Account for DSC slice overhead
  drm/i915/dp: Add helpers for joiner candidate loops

Chaitanya Kumar Borah (2):
  drm/i915/display: Add upper limit check for pixel clock
  drm/i915/display: Extend the max dotclock limit to WCL and pre PTL
    platforms

 drivers/gpu/drm/i915/display/intel_display.c |  17 ++
 drivers/gpu/drm/i915/display/intel_display.h |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 295 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h      |  39 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 195 ++++++++----
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   1 -
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   3 +
 7 files changed, 411 insertions(+), 140 deletions(-)

-- 
2.45.2

[PATCH 01/16] drm/i915/dp: Early reject bad hdisplay in intel_dp_mode_valid

[Ankit Nautiyal]

Move check for bad hdisplay early as it is independent on other checks.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 79fd3b8d8b25..126da297efc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1460,6 +1460,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
 
+	if (intel_dp_hdisplay_bad(display, mode->hdisplay))
+		return MODE_H_ILLEGAL;
+
 	fixed_mode = intel_panel_fixed_mode(connector, mode);
 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 		status = intel_panel_mode_valid(connector, mode);
@@ -1483,9 +1486,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	if (target_clock > max_dotclk)
 		return MODE_CLOCK_HIGH;
 
-	if (intel_dp_hdisplay_bad(display, mode->hdisplay))
-		return MODE_H_ILLEGAL;
-
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
-- 
2.45.2

[PATCH 02/16] drm/i915/dp: Move num_joined_pipes and related checks together

[Ankit Nautiyal]

Move the calculation of `num_joined_pipes` and other constraints that
depend on it, into a single block.
This groups all joiner-dependent logic together, preparing the code for a
future loop-based evaluation of multiple joiner configurations.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++-------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 126da297efc5..c0a8ffac6312 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1472,20 +1472,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 		target_clock = fixed_mode->clock;
 	}
 
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     mode->hdisplay, target_clock);
-	max_dotclk *= num_joined_pipes;
-
 	sink_format = intel_dp_sink_format(connector, mode);
 	output_format = intel_dp_output_format(connector, sink_format);
 
-	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
-	if (status != MODE_OK)
-		return status;
-
-	if (target_clock > max_dotclk)
-		return MODE_CLOCK_HIGH;
-
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -1496,6 +1485,17 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 					   target_clock, mode->hdisplay,
 					   link_bpp_x16, 0);
 
+	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
+						     mode->hdisplay, target_clock);
+	max_dotclk *= num_joined_pipes;
+
+	if (target_clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
+	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
+	if (status != MODE_OK)
+		return status;
+
 	if (intel_dp_has_dsc(connector)) {
 		int pipe_bpp;
 
@@ -1538,14 +1538,14 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
 		return MODE_CLOCK_HIGH;
 
+	status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+	if (status != MODE_OK)
+		return status;
+
 	if (mode_rate > max_rate && !dsc)
 		return MODE_CLOCK_HIGH;
 
-	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
-	if (status != MODE_OK)
-		return status;
-
-	return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+	return intel_dp_mode_valid_downstream(connector, mode, target_clock);
 }
 
 bool intel_dp_source_supports_tps3(struct intel_display *display)
-- 
2.45.2

[PATCH 03/16] drm/i915/dp: Extract helper to get the hdisplay limit

[Ankit Nautiyal]

Separate out function to get the hdisplay limit for a given platform.

v2: Rename the helper to intel_dp_max_hdisplay_per_pipe(). (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c0a8ffac6312..4c3a1b6d0015 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1371,6 +1371,12 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	return MODE_OK;
 }
 
+static
+int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
+{
+	return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
+}
+
 static
 bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
 			   struct intel_connector *connector,
@@ -1378,17 +1384,14 @@ bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
 			   int num_joined_pipes)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int hdisplay_limit;
 
 	if (!intel_dp_has_joiner(intel_dp))
 		return false;
 
 	num_joined_pipes /= 2;
 
-	hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
-
 	return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
-	       hdisplay > num_joined_pipes * hdisplay_limit;
+	       hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display);
 }
 
 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Ankit Nautiyal]

Currently in intel_dp_mode_valid(), we compute the number of joined pipes
required before deciding whether DSC is needed. This ordering prevents us
from accounting for DSC-related overhead when determining pipe
requirements.

It is not possible to first decide whether DSC is needed and then compute
the required number of joined pipes, because the two depend on each other:

 - DSC need is a function of the pipe count (e.g., 4‑pipe always requires
   DSC; 2‑pipe may require it if uncompressed joiner is unavailable).

 - Whether a given pipe‑join configuration is sufficient depends on
   effective bandwidth, which itself changes when DSC is used.

As a result, the only correct approach is to iterate candidate pipe counts.

So, refactor the logic to start with a single pipe and incrementally try
additional pipes only if needed. While DSC overhead is not yet computed
here, this restructuring prepares the code to support that in a follow-up
changes.

Additionally, if a forced joiner configuration is present, we first check
whether it satisfies the bandwidth and timing constraints. If it does not,
we fall back to evaluating configurations with 1, 2, or 4 pipes joined
and prune or keep the mode accordingly.

v2:
 - Iterate over number of pipes to be joined instead of joiner
   candidates. (Jani)
 - Document the rationale of iterating over number of joined pipes.
   (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 158 +++++++++++++++---------
 1 file changed, 103 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4c3a1b6d0015..599965a6e1a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static
+bool intel_dp_can_join(struct intel_display *display,
+		       int num_joined_pipes)
+{
+	switch (num_joined_pipes) {
+	case 1:
+		return true;
+	case 2:
+		return HAS_BIGJOINER(display) ||
+		       HAS_UNCOMPRESSED_JOINER(display);
+	case 4:
+		return HAS_ULTRAJOINER(display);
+	default:
+		return false;
+	}
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *_connector,
 		    const struct drm_display_mode *mode)
@@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	const struct drm_display_mode *fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
-	int max_dotclk = display->cdclk.max_dotclk_freq;
 	u16 dsc_max_compressed_bpp = 0;
 	u8 dsc_slice_count = 0;
 	enum drm_mode_status status;
 	bool dsc = false;
 	int num_joined_pipes;
 	int link_bpp_x16;
+	int num_pipes;
 
 	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
@@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 					   target_clock, mode->hdisplay,
 					   link_bpp_x16, 0);
 
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     mode->hdisplay, target_clock);
-	max_dotclk *= num_joined_pipes;
-
-	if (target_clock > max_dotclk)
-		return MODE_CLOCK_HIGH;
-
-	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
-	if (status != MODE_OK)
-		return status;
-
-	if (intel_dp_has_dsc(connector)) {
-		int pipe_bpp;
-
-		/*
-		 * TBD pass the connector BPC,
-		 * for now U8_MAX so that max BPC on that platform would be picked
-		 */
-		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
-
-		/*
-		 * Output bpp is stored in 6.4 format so right shift by 4 to get the
-		 * integer value since we support only integer values of bpp.
-		 */
-		if (intel_dp_is_edp(intel_dp)) {
-			dsc_max_compressed_bpp =
-				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
-
-			dsc_slice_count =
-				intel_dp_dsc_get_slice_count(connector,
-							     target_clock,
-							     mode->hdisplay,
-							     num_joined_pipes);
-
-			dsc = dsc_max_compressed_bpp && dsc_slice_count;
-		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
-			unsigned long bw_overhead_flags = 0;
-
-			if (!drm_dp_is_uhbr_rate(max_link_clock))
-				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
-
-			dsc = intel_dp_mode_valid_with_dsc(connector,
-							   max_link_clock, max_lanes,
-							   target_clock, mode->hdisplay,
-							   num_joined_pipes,
-							   output_format, pipe_bpp,
-							   bw_overhead_flags);
+	/*
+	 * We cannot determine the required pipe‑join count before knowing whether
+	 * DSC is needed, nor can we determine DSC need without knowing the pipe
+	 * count.
+	 * Because of this dependency cycle, the only correct approach is to iterate
+	 * over candidate pipe counts and evaluate each combination.
+	 */
+	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int max_dotclk = display->cdclk.max_dotclk_freq;
+
+		status = MODE_CLOCK_HIGH;
+
+		if (num_pipes == 0) {
+			if (!connector->force_joined_pipes)
+				continue;
+			num_joined_pipes = connector->force_joined_pipes;
+		} else {
+			num_joined_pipes = num_pipes;
+		}
+
+		if (!intel_dp_can_join(display, num_joined_pipes))
+			continue;
+
+		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+			continue;
+
+		status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
+		if (status != MODE_OK)
+			continue;
+
+		if (intel_dp_has_dsc(connector)) {
+			int pipe_bpp;
+
+			/*
+			 * TBD pass the connector BPC,
+			 * for now U8_MAX so that max BPC on that platform would be picked
+			 */
+			pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
+
+			/*
+			 * Output bpp is stored in 6.4 format so right shift by 4 to get the
+			 * integer value since we support only integer values of bpp.
+			 */
+			if (intel_dp_is_edp(intel_dp)) {
+				dsc_max_compressed_bpp =
+					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
+
+				dsc_slice_count =
+					intel_dp_dsc_get_slice_count(connector,
+								     target_clock,
+								     mode->hdisplay,
+								     num_joined_pipes);
+
+				dsc = dsc_max_compressed_bpp && dsc_slice_count;
+			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
+				unsigned long bw_overhead_flags = 0;
+
+				if (!drm_dp_is_uhbr_rate(max_link_clock))
+					bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
+
+				dsc = intel_dp_mode_valid_with_dsc(connector,
+								   max_link_clock, max_lanes,
+								   target_clock, mode->hdisplay,
+								   num_joined_pipes,
+								   output_format, pipe_bpp,
+								   bw_overhead_flags);
+			}
+		}
+
+		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
+			continue;
+
+		if (mode_rate > max_rate && !dsc)
+			continue;
+
+		status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+		if (status != MODE_OK)
+			continue;
+
+		max_dotclk *= num_joined_pipes;
+
+		if (target_clock <= max_dotclk) {
+			status = MODE_OK;
+			break;
 		}
 	}
 
-	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
-		return MODE_CLOCK_HIGH;
-
-	status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
 	if (status != MODE_OK)
 		return status;
 
-	if (mode_rate > max_rate && !dsc)
-		return MODE_CLOCK_HIGH;
-
 	return intel_dp_mode_valid_downstream(connector, mode, target_clock);
+
 }
 
 bool intel_dp_source_supports_tps3(struct intel_display *display)
-- 
2.45.2

[PATCH 05/16] drm/i915/dp: Rework pipe joiner logic in compute_config

[Ankit Nautiyal]

Currently, the number of joined pipes are determined early in the flow,
which limits flexibility for accounting DSC slice overhead. To address
this, recompute the joined pipe count during DSC configuration.

Refactor intel_dp_dsc_compute_config() to iterate over joiner candidates
and select the minimal joiner configuration that satisfies the mode
requirements. This prepares the logic for future changes that will
consider DSC slice overhead.

v2:
 - Rename helper to intel_dp_compute_link_for_joined_pipes(). (Imre)
 - Move the check for max dotclock inside the helper so that if dotclock
   check fails for non DSC case for a given number of joined pipes, we
   are able to fallback to the DSC mode. (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 93 ++++++++++++++++++++-----
 1 file changed, 77 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 599965a6e1a6..f8986f0acc79 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2804,33 +2804,23 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 }
 
 static int
-intel_dp_compute_link_config(struct intel_encoder *encoder,
-			     struct intel_crtc_state *pipe_config,
-			     struct drm_connector_state *conn_state,
-			     bool respect_downstream_limits)
+intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
+				       struct intel_crtc_state *pipe_config,
+				       struct drm_connector_state *conn_state,
+				       bool respect_downstream_limits)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int max_dotclk = display->cdclk.max_dotclk_freq;
 	struct link_config_limits limits;
 	bool dsc_needed, joiner_needs_dsc;
-	int num_joined_pipes;
 	int ret = 0;
 
-	if (pipe_config->fec_enable &&
-	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
-		return -EINVAL;
-
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     adjusted_mode->crtc_hdisplay,
-						     adjusted_mode->crtc_clock);
-	if (num_joined_pipes > 1)
-		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
-
 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
@@ -2880,6 +2870,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 			return ret;
 	}
 
+	max_dotclk *= num_joined_pipes;
+
+	if (adjusted_mode->crtc_clock > max_dotclk)
+		return -EINVAL;
+
 	drm_dbg_kms(display->drm,
 		    "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
 		    pipe_config->lane_count, pipe_config->port_clock,
@@ -2893,6 +2888,72 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+			     struct intel_crtc_state *crtc_state,
+			     struct drm_connector_state *conn_state,
+			     bool respect_downstream_limits)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_connector *connector =
+		to_intel_connector(conn_state->connector);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int num_joined_pipes;
+	int num_pipes;
+	int ret = 0;
+
+	if (crtc_state->fec_enable &&
+	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
+		return -EINVAL;
+
+	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		if (num_pipes == 0) {
+			if (!connector->force_joined_pipes)
+				continue;
+			num_joined_pipes = connector->force_joined_pipes;
+		} else {
+			num_joined_pipes = num_pipes;
+		}
+
+		if (!intel_dp_can_join(display, num_joined_pipes))
+			continue;
+
+		if (adjusted_mode->hdisplay >
+		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+			continue;
+
+		/*
+		 * NOTE:
+		 * The crtc_state->joiner_pipes should have been set at the end
+		 * only if all the conditions are met. However that would mean
+		 * that num_joined_pipes is passed around to all helpers and
+		 * make them use it instead of using crtc_state->joiner_pipes
+		 * directly or indirectly (via intel_crtc_num_joined_pipes()).
+		 *
+		 * For now, setting crtc_state->joiner_pipes to the candidate
+		 * value to avoid the above churn and resetting it to 0, in case
+		 * no joiner candidate is found to be suitable for the given
+		 * configuration.
+		 */
+		if (num_joined_pipes > 1)
+			crtc_state->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
+							   crtc->pipe);
+
+		ret = intel_dp_compute_link_for_joined_pipes(encoder, crtc_state, conn_state,
+							     respect_downstream_limits);
+		if (ret == 0)
+			break;
+	}
+
+	if (ret < 0)
+		crtc_state->joiner_pipes = 0;
+
+	return ret;
+}
+
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
-- 
2.45.2

[PATCH 06/16] drm/i915/dp_mst: Move the check for dotclock at the end

[Ankit Nautiyal]

Refactor the mode_valid to have all joiner dependent stuff together and
place the check for dotclock limit at the very end.

This will help in the following refactor to iterate over the joiner
candidates and find the best joiner candidate that satisfy all checks
and limits.

v2: Update status to MODE_CLOCK_HIGH if max_dotclock check fails. (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 ++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 24f8e60df9ac..24b0020acad0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1470,20 +1470,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	 *   corresponding link capabilities of the sink) in case the
 	 *   stream is uncompressed for it by the last branch device.
 	 */
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     mode->hdisplay, target_clock);
-	max_dotclk *= num_joined_pipes;
-
 	ret = drm_modeset_lock(&mgr->base.lock, ctx);
 	if (ret)
 		return ret;
 
-	if (mode_rate > max_rate || mode->clock > max_dotclk ||
+	if (mode_rate > max_rate ||
 	    drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
 		*status = MODE_CLOCK_HIGH;
 		return 0;
 	}
 
+	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
+						     mode->hdisplay, target_clock);
+
 	if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
 		/*
 		 * TBD pass the connector BPC,
@@ -1513,6 +1512,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	}
 
 	*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+
+	if (*status != MODE_OK)
+		return 0;
+
+	max_dotclk *= num_joined_pipes;
+
+	if (mode->clock > max_dotclk) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
+	*status = MODE_OK;
+
 	return 0;
 }
 
-- 
2.45.2

[PATCH 07/16] drm/i915/dp_mst: Move the joiner dependent code together

[Ankit Nautiyal]

Move the calculation of num_joined_pipes and other constraints that
depend on it, into a single block in mst_stream_compute_config().

This groups all joiner-dependent logic together, preparing the code for a
future loop-based evaluation of multiple joiner configurations.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 24b0020acad0..f47bf45d0bce 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -619,16 +619,16 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return -EINVAL;
 
+	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->has_pch_encoder = false;
+
 	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
 						     adjusted_mode->crtc_hdisplay,
 						     adjusted_mode->crtc_clock);
 	if (num_joined_pipes > 1)
 		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
 
-	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
-	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
-	pipe_config->has_pch_encoder = false;
-
 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
@@ -685,6 +685,10 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 						  pipe_config->dp_m_n.tu);
 	}
 
+	if (ret)
+		return ret;
+
+	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
 	if (ret)
 		return ret;
 
@@ -695,10 +699,6 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 		pipe_config->lane_lat_optim_mask =
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
-	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
-	if (ret)
-		return ret;
-
 	intel_vrr_compute_config(pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
-- 
2.45.2

[PATCH 08/16] drm/i915/dp_mst: Rework pipe joiner logic in mode_valid

[Ankit Nautiyal]

Refactor the logic to get the number of joined pipes. Start with a single
pipe and incrementally try additional pipes only if needed. While DSC
overhead is not yet computed here, this restructuring prepares the code to
support that in follow-up changes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     |  2 -
 drivers/gpu/drm/i915/display/intel_dp.h     |  3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 86 ++++++++++++---------
 3 files changed, 52 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f8986f0acc79..9bbd37ebd2ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1371,7 +1371,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	return MODE_OK;
 }
 
-static
 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
 {
 	return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
@@ -1434,7 +1433,6 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
-static
 bool intel_dp_can_join(struct intel_display *display,
 		       int num_joined_pipes)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 25bfbfd291b0..6d409c1998c9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -225,5 +225,8 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct drm_connector_state *conn_state);
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled);
+int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
+bool intel_dp_can_join(struct intel_display *display,
+		       int num_joined_pipes);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f47bf45d0bce..664004600564 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1420,7 +1420,6 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;
 	struct drm_dp_mst_port *port = connector->mst.port;
 	const int min_bpp = 18;
-	int max_dotclk = display->cdclk.max_dotclk_freq;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	unsigned long bw_overhead_flags =
 		DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK;
@@ -1428,6 +1427,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	bool dsc = false;
 	int target_clock = mode->clock;
 	int num_joined_pipes;
+	int num_pipes;
 
 	if (drm_connector_is_unregistered(&connector->base)) {
 		*status = MODE_ERROR;
@@ -1480,50 +1480,62 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		return 0;
 	}
 
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     mode->hdisplay, target_clock);
-
-	if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
-		/*
-		 * TBD pass the connector BPC,
-		 * for now U8_MAX so that max BPC on that platform would be picked
-		 */
-		int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
-
-		if (!drm_dp_is_uhbr_rate(max_link_clock))
-			bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
-
-		dsc = intel_dp_mode_valid_with_dsc(connector,
-						   max_link_clock, max_lanes,
-						   target_clock, mode->hdisplay,
-						   num_joined_pipes,
-						   INTEL_OUTPUT_FORMAT_RGB, pipe_bpp,
-						   bw_overhead_flags);
-	}
+	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int max_dotclk = display->cdclk.max_dotclk_freq;
 
-	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
 		*status = MODE_CLOCK_HIGH;
-		return 0;
-	}
 
-	if (mode_rate > max_rate && !dsc) {
-		*status = MODE_CLOCK_HIGH;
-		return 0;
-	}
+		if (num_pipes == 0) {
+			if (!connector->force_joined_pipes)
+				continue;
+			num_joined_pipes = connector->force_joined_pipes;
+		} else {
+			num_joined_pipes = num_pipes;
+		}
 
-	*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+		if (!intel_dp_can_join(display, num_joined_pipes))
+			continue;
 
-	if (*status != MODE_OK)
-		return 0;
+		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+			continue;
 
-	max_dotclk *= num_joined_pipes;
+		if (intel_dp_has_dsc(connector) &&
+		    drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
+			/*
+			 * TBD pass the connector BPC,
+			 * for now U8_MAX so that max BPC on that platform would be picked
+			 */
+			int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
 
-	if (mode->clock > max_dotclk) {
-		*status = MODE_CLOCK_HIGH;
-		return 0;
-	}
+			if (!drm_dp_is_uhbr_rate(max_link_clock))
+				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
+
+			dsc = intel_dp_mode_valid_with_dsc(connector,
+							   max_link_clock, max_lanes,
+							   target_clock, mode->hdisplay,
+							   num_joined_pipes,
+							   INTEL_OUTPUT_FORMAT_RGB, pipe_bpp,
+							   bw_overhead_flags);
+		}
 
-	*status = MODE_OK;
+		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
+			continue;
+
+		if (mode_rate > max_rate && !dsc)
+			continue;
+
+		*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
+
+		if (*status != MODE_OK)
+			continue;
+
+		max_dotclk *= num_joined_pipes;
+
+		if (mode->clock <= max_dotclk) {
+			*status = MODE_OK;
+			break;
+		}
+	}
 
 	return 0;
 }
-- 
2.45.2

[PATCH 09/16] drm/i915/dp_mst: Extract helper to compute link for given joiner config

[Ankit Nautiyal]

Move the joiner-dependent portion of mst_stream_compute_config() into
mst_stream_compute_link_for_joined_pipes(), which computes the MST link
configuration for a specific num_joined_pipes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 72 ++++++++++++++-------
 1 file changed, 47 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 664004600564..29ac7b2e1e9c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -595,40 +595,19 @@ mst_stream_compute_config_limits(struct intel_dp *intel_dp,
 							    dsc);
 }
 
-static int mst_stream_compute_config(struct intel_encoder *encoder,
-				     struct intel_crtc_state *pipe_config,
-				     struct drm_connector_state *conn_state)
+static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encoder,
+						    struct intel_crtc_state *pipe_config,
+						    struct drm_connector_state *conn_state,
+						    int num_joined_pipes)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_dp *intel_dp = to_primary_dp(encoder);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	const struct drm_display_mode *adjusted_mode =
-		&pipe_config->hw.adjusted_mode;
 	struct link_config_limits limits;
 	bool dsc_needed, joiner_needs_dsc;
-	int num_joined_pipes;
 	int ret = 0;
 
-	if (pipe_config->fec_enable &&
-	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
-		return -EINVAL;
-
-	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-		return -EINVAL;
-
-	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
-	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
-	pipe_config->has_pch_encoder = false;
-
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     adjusted_mode->crtc_hdisplay,
-						     adjusted_mode->crtc_clock);
-	if (num_joined_pipes > 1)
-		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
-
 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
@@ -692,6 +671,49 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
+	return 0;
+}
+
+static int mst_stream_compute_config(struct intel_encoder *encoder,
+				     struct intel_crtc_state *pipe_config,
+				     struct drm_connector_state *conn_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	struct intel_dp *intel_dp = to_primary_dp(encoder);
+	struct intel_connector *connector =
+		to_intel_connector(conn_state->connector);
+	const struct drm_display_mode *adjusted_mode =
+		&pipe_config->hw.adjusted_mode;
+	int num_joined_pipes;
+	int ret = 0;
+
+	if (pipe_config->fec_enable &&
+	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
+		return -EINVAL;
+
+	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+		return -EINVAL;
+
+	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->has_pch_encoder = false;
+
+	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
+						     adjusted_mode->crtc_hdisplay,
+						     adjusted_mode->crtc_clock);
+
+	if (num_joined_pipes > 1)
+		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
+
+	ret = mst_stream_compute_link_for_joined_pipes(encoder,
+						       pipe_config,
+						       conn_state,
+						       num_joined_pipes);
+	if (ret)
+		return ret;
+
 	pipe_config->limited_color_range =
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
-- 
2.45.2

[PATCH 10/16] drm/i915/dp_mst: Rework pipe joiner logic in compute_config

[Ankit Nautiyal]

Similar to the DP SST, refactor `mst_stream_compute_config()` to iterate
over joiner candidates and select the minimal joiner configuration that
satisfies the mode requirements. This prepares the logic for future changes
that will consider DSC slice overhead.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++----
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 29ac7b2e1e9c..7a83af89ef03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -687,6 +687,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->hw.adjusted_mode;
 	int num_joined_pipes;
+	int num_pipes;
 	int ret = 0;
 
 	if (pipe_config->fec_enable &&
@@ -700,17 +701,45 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	pipe_config->has_pch_encoder = false;
 
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     adjusted_mode->crtc_hdisplay,
-						     adjusted_mode->crtc_clock);
+	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int max_dotclk = display->cdclk.max_dotclk_freq;
 
-	if (num_joined_pipes > 1)
-		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
+		ret = -EINVAL;
+
+		if (num_pipes == 0) {
+			if (!connector->force_joined_pipes)
+				continue;
+			num_joined_pipes = connector->force_joined_pipes;
+		} else {
+			num_joined_pipes = num_pipes;
+		}
+
+		if (!intel_dp_can_join(display, num_joined_pipes))
+			continue;
+
+		if (adjusted_mode->hdisplay >
+		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+			continue;
+
+		if (num_joined_pipes > 1)
+			pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
+							    crtc->pipe);
+
+		ret = mst_stream_compute_link_for_joined_pipes(encoder,
+							       pipe_config,
+							       conn_state,
+							       num_joined_pipes);
+		if (ret)
+			continue;
+
+		max_dotclk *= num_joined_pipes;
+
+		if (adjusted_mode->clock <= max_dotclk) {
+			ret = 0;
+			break;
+		}
+	}
 
-	ret = mst_stream_compute_link_for_joined_pipes(encoder,
-						       pipe_config,
-						       conn_state,
-						       num_joined_pipes);
 	if (ret)
 		return ret;
 
-- 
2.45.2

[PATCH 11/16] drm/i915/dp: Introduce helper to check pixel rate against dotclock limits

[Ankit Nautiyal]

Add intel_dp_pixel_rate_fits_dotclk() helper, that checks the
required pixel rate against platform dotclock limit.
With joined pipes the effective dotclock limit depends upon the number
of joined pipes.

Call the helper from the mode_valid phase and from the compute_config
phase where we need to check the limits for the given target clock for a
given joiner candidate.

v2: Rename the helper to intel_dp_dotclk_valid(). (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 23 ++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h     |  3 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 ++++++-------
 3 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9bbd37ebd2ea..655688c8e6ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1449,6 +1449,18 @@ bool intel_dp_can_join(struct intel_display *display,
 	}
 }
 
+bool intel_dp_dotclk_valid(struct intel_display *display,
+			   int target_clock,
+			   int num_joined_pipes)
+{
+	int max_dotclk = display->cdclk.max_dotclk_freq;
+	int effective_dotclk_limit;
+
+	effective_dotclk_limit = max_dotclk * num_joined_pipes;
+
+	return target_clock <= effective_dotclk_limit;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *_connector,
 		    const struct drm_display_mode *mode)
@@ -1511,7 +1523,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	 * over candidate pipe counts and evaluate each combination.
 	 */
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
-		int max_dotclk = display->cdclk.max_dotclk_freq;
 
 		status = MODE_CLOCK_HIGH;
 
@@ -1582,9 +1593,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 		if (status != MODE_OK)
 			continue;
 
-		max_dotclk *= num_joined_pipes;
-
-		if (target_clock <= max_dotclk) {
+		if (intel_dp_dotclk_valid(display,
+					  target_clock,
+					  num_joined_pipes)) {
 			status = MODE_OK;
 			break;
 		}
@@ -2870,7 +2881,9 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
 
 	max_dotclk *= num_joined_pipes;
 
-	if (adjusted_mode->crtc_clock > max_dotclk)
+	if (!intel_dp_dotclk_valid(display,
+				   adjusted_mode->crtc_clock,
+				   num_joined_pipes))
 		return -EINVAL;
 
 	drm_dbg_kms(display->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6d409c1998c9..78fa8eaba4ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -228,5 +228,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
 bool intel_dp_can_join(struct intel_display *display,
 		       int num_joined_pipes);
+bool intel_dp_dotclk_valid(struct intel_display *display,
+			   int target_clock,
+			   int num_joined_pipes);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7a83af89ef03..f433a01dcfcb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -702,7 +702,6 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	pipe_config->has_pch_encoder = false;
 
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
-		int max_dotclk = display->cdclk.max_dotclk_freq;
 
 		ret = -EINVAL;
 
@@ -732,9 +731,9 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 		if (ret)
 			continue;
 
-		max_dotclk *= num_joined_pipes;
-
-		if (adjusted_mode->clock <= max_dotclk) {
+		if (intel_dp_dotclk_valid(display,
+					  adjusted_mode->clock,
+					  num_joined_pipes)) {
 			ret = 0;
 			break;
 		}
@@ -1532,7 +1531,6 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	}
 
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
-		int max_dotclk = display->cdclk.max_dotclk_freq;
 
 		*status = MODE_CLOCK_HIGH;
 
@@ -1580,9 +1578,9 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		if (*status != MODE_OK)
 			continue;
 
-		max_dotclk *= num_joined_pipes;
-
-		if (mode->clock <= max_dotclk) {
+		if (intel_dp_dotclk_valid(display,
+					  mode->clock,
+					  num_joined_pipes)) {
 			*status = MODE_OK;
 			break;
 		}
-- 
2.45.2

[PATCH 12/16] drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid()

[Ankit Nautiyal]

Make dsc_slice_count closer to the block where it is used and promote it
from u8 to int. This aligns it with upcoming DSC bubble pixel-rate
adjustments, where the slice count participates in wider arithmetic.

Currently, for non-eDP (DP/DP_MST) cases  the slice count is computed only
inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC
bubble handling is added, dp_mode_valid() will need access to its own local
slice count for non-eDP cases as well.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 655688c8e6ef..0acb3b64cf27 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1473,7 +1473,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	u16 dsc_max_compressed_bpp = 0;
-	u8 dsc_slice_count = 0;
 	enum drm_mode_status status;
 	bool dsc = false;
 	int num_joined_pipes;
@@ -1523,6 +1522,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	 * over candidate pipe counts and evaluate each combination.
 	 */
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int dsc_slice_count = 0;
 
 		status = MODE_CLOCK_HIGH;
 
@@ -1547,6 +1547,11 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 		if (intel_dp_has_dsc(connector)) {
 			int pipe_bpp;
 
+			dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
+								       target_clock,
+								       mode->hdisplay,
+								       num_joined_pipes);
+
 			/*
 			 * TBD pass the connector BPC,
 			 * for now U8_MAX so that max BPC on that platform would be picked
@@ -1561,12 +1566,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 				dsc_max_compressed_bpp =
 					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
 
-				dsc_slice_count =
-					intel_dp_dsc_get_slice_count(connector,
-								     target_clock,
-								     mode->hdisplay,
-								     num_joined_pipes);
-
 				dsc = dsc_max_compressed_bpp && dsc_slice_count;
 			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
 				unsigned long bw_overhead_flags = 0;
-- 
2.45.2

[PATCH 13/16] drm/i915/dp: Account for DSC slice overhead

[Ankit Nautiyal]

Account for DSC slice overhead bubbles and adjust the pixel rate while
checking the pixel rate against the max dotclock limits.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c   |  1 -
 drivers/gpu/drm/i915/display/intel_vdsc.h   |  3 +++
 5 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0acb3b64cf27..c1ff92367808 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1451,6 +1451,8 @@ bool intel_dp_can_join(struct intel_display *display,
 
 bool intel_dp_dotclk_valid(struct intel_display *display,
 			   int target_clock,
+			   int htotal,
+			   int dsc_slice_count,
 			   int num_joined_pipes)
 {
 	int max_dotclk = display->cdclk.max_dotclk_freq;
@@ -1458,6 +1460,12 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 
 	effective_dotclk_limit = max_dotclk * num_joined_pipes;
 
+	if (dsc_slice_count)
+		target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,
+									 target_clock,
+									 htotal,
+									 dsc_slice_count);
+
 	return target_clock <= effective_dotclk_limit;
 }
 
@@ -1592,8 +1600,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 		if (status != MODE_OK)
 			continue;
 
+		if (!dsc)
+			dsc_slice_count = 0;
+
 		if (intel_dp_dotclk_valid(display,
 					  target_clock,
+					  mode->htotal,
+					  dsc_slice_count,
 					  num_joined_pipes)) {
 			status = MODE_OK;
 			break;
@@ -2827,6 +2840,7 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
 	int max_dotclk = display->cdclk.max_dotclk_freq;
 	struct link_config_limits limits;
 	bool dsc_needed, joiner_needs_dsc;
+	int dsc_slice_count = 0;
 	int ret = 0;
 
 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
@@ -2878,10 +2892,15 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
 			return ret;
 	}
 
+	if (pipe_config->dsc.compression_enable)
+		dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
+
 	max_dotclk *= num_joined_pipes;
 
 	if (!intel_dp_dotclk_valid(display,
 				   adjusted_mode->crtc_clock,
+				   adjusted_mode->crtc_htotal,
+				   dsc_slice_count,
 				   num_joined_pipes))
 		return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 78fa8eaba4ac..beef480b7672 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -230,6 +230,8 @@ bool intel_dp_can_join(struct intel_display *display,
 		       int num_joined_pipes);
 bool intel_dp_dotclk_valid(struct intel_display *display,
 			   int target_clock,
+			   int htotal,
+			   int dsc_slice_count,
 			   int num_joined_pipes);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f433a01dcfcb..bdf2f09fa03e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -702,6 +702,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	pipe_config->has_pch_encoder = false;
 
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int dsc_slice_count = 0;
 
 		ret = -EINVAL;
 
@@ -731,8 +732,12 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 		if (ret)
 			continue;
 
+		dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, pipe_config);
+
 		if (intel_dp_dotclk_valid(display,
 					  adjusted_mode->clock,
+					  adjusted_mode->htotal,
+					  dsc_slice_count,
 					  num_joined_pipes)) {
 			ret = 0;
 			break;
@@ -1531,6 +1536,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	}
 
 	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+		int dsc_slice_count = 0;
 
 		*status = MODE_CLOCK_HIGH;
 
@@ -1556,6 +1562,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 			 */
 			int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
 
+			dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
+								       mode->clock,
+								       mode->hdisplay,
+								       num_joined_pipes);
+
 			if (!drm_dp_is_uhbr_rate(max_link_clock))
 				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
 
@@ -1580,6 +1591,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 
 		if (intel_dp_dotclk_valid(display,
 					  mode->clock,
+					  mode->htotal,
+					  dsc_slice_count,
 					  num_joined_pipes)) {
 			*status = MODE_OK;
 			break;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 642a89270d8e..7e53201b3cb1 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1104,7 +1104,6 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
 }
 
-static
 int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
 					      int pixel_rate, int htotal,
 					      int dsc_horizontal_slices)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index aeb17670307b..f4d5b37293cf 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -41,5 +41,8 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
 unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state);
+int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
+					      int pixel_rate, int htotal,
+					      int dsc_horizontal_slices);
 
 #endif /* __INTEL_VDSC_H__ */
-- 
2.45.2

[PATCH 14/16] drm/i915/dp: Add helpers for joiner candidate loops

[Ankit Nautiyal]

Introduce for_each_joiner_candidate(), intel_dp_pick_joiner_candidate() and
intel_dp_joiner_candidate_valid() to remove duplicated joiner enumeration
and validity checks across DP SST and MST paths.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 37 ++++++++-------------
 drivers/gpu/drm/i915/display/intel_dp.h     | 31 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 37 ++++++++-------------
 3 files changed, 59 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c1ff92367808..9eba8f90bc90 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1529,23 +1529,19 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	 * Because of this dependency cycle, the only correct approach is to iterate
 	 * over candidate pipe counts and evaluate each combination.
 	 */
-	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+	for_each_joiner_candidate(num_pipes) {
 		int dsc_slice_count = 0;
 
 		status = MODE_CLOCK_HIGH;
 
-		if (num_pipes == 0) {
-			if (!connector->force_joined_pipes)
-				continue;
-			num_joined_pipes = connector->force_joined_pipes;
-		} else {
-			num_joined_pipes = num_pipes;
-		}
-
-		if (!intel_dp_can_join(display, num_joined_pipes))
+		if (!intel_dp_pick_joiner_candidate(num_pipes,
+						    connector->force_joined_pipes,
+						    &num_joined_pipes))
 			continue;
 
-		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+		if (!intel_dp_joiner_candidate_valid(display,
+						     mode->hdisplay,
+						     num_joined_pipes))
 			continue;
 
 		status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
@@ -2938,20 +2934,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
 		return -EINVAL;
 
-	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
-		if (num_pipes == 0) {
-			if (!connector->force_joined_pipes)
-				continue;
-			num_joined_pipes = connector->force_joined_pipes;
-		} else {
-			num_joined_pipes = num_pipes;
-		}
-
-		if (!intel_dp_can_join(display, num_joined_pipes))
+	for_each_joiner_candidate(num_pipes) {
+		if (!intel_dp_pick_joiner_candidate(num_pipes,
+						    connector->force_joined_pipes,
+						    &num_joined_pipes))
 			continue;
 
-		if (adjusted_mode->hdisplay >
-		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+		if (!intel_dp_joiner_candidate_valid(display,
+						     adjusted_mode->hdisplay,
+						     num_joined_pipes))
 			continue;
 
 		/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index beef480b7672..111a5d4b3992 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -234,4 +234,35 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 			   int dsc_slice_count,
 			   int num_joined_pipes);
 
+#define for_each_joiner_candidate(__num_pipes) \
+	for ((__num_pipes) = 0; (__num_pipes) < (I915_MAX_PIPES); (__num_pipes)++)
+
+static inline bool intel_dp_pick_joiner_candidate(int num_pipes,
+						  int force_joined_pipes,
+						  int *num_joined_pipes)
+{
+	if (num_pipes == 0) {
+		if (!force_joined_pipes)
+			return false;
+		*num_joined_pipes = force_joined_pipes;
+	} else {
+		*num_joined_pipes = num_pipes;
+	}
+
+	return true;
+}
+
+static inline bool intel_dp_joiner_candidate_valid(struct intel_display *display,
+						   int hdisplay,
+						   int num_joined_pipes)
+{
+	if (!intel_dp_can_join(display, num_joined_pipes))
+		return false;
+
+	if (hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+		return false;
+
+	return true;
+}
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bdf2f09fa03e..005efcb5d2bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -701,24 +701,19 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	pipe_config->has_pch_encoder = false;
 
-	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+	for_each_joiner_candidate(num_pipes) {
 		int dsc_slice_count = 0;
 
 		ret = -EINVAL;
 
-		if (num_pipes == 0) {
-			if (!connector->force_joined_pipes)
-				continue;
-			num_joined_pipes = connector->force_joined_pipes;
-		} else {
-			num_joined_pipes = num_pipes;
-		}
-
-		if (!intel_dp_can_join(display, num_joined_pipes))
+		if (!intel_dp_pick_joiner_candidate(num_pipes,
+						    connector->force_joined_pipes,
+						    &num_joined_pipes))
 			continue;
 
-		if (adjusted_mode->hdisplay >
-		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+		if (!intel_dp_joiner_candidate_valid(display,
+						     adjusted_mode->hdisplay,
+						     num_joined_pipes))
 			continue;
 
 		if (num_joined_pipes > 1)
@@ -1535,23 +1530,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		return 0;
 	}
 
-	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
+	for_each_joiner_candidate(num_pipes) {
 		int dsc_slice_count = 0;
 
 		*status = MODE_CLOCK_HIGH;
 
-		if (num_pipes == 0) {
-			if (!connector->force_joined_pipes)
-				continue;
-			num_joined_pipes = connector->force_joined_pipes;
-		} else {
-			num_joined_pipes = num_pipes;
-		}
-
-		if (!intel_dp_can_join(display, num_joined_pipes))
+		if (!intel_dp_pick_joiner_candidate(num_pipes,
+						    connector->force_joined_pipes,
+						    &num_joined_pipes))
 			continue;
 
-		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+		if (!intel_dp_joiner_candidate_valid(display,
+						     mode->hdisplay,
+						     num_joined_pipes))
 			continue;
 
 		if (intel_dp_has_dsc(connector) &&
-- 
2.45.2

[PATCH 15/16] drm/i915/display: Add upper limit check for pixel clock

[Ankit Nautiyal]

From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add upper limit check for pixel clock for DISPLAY_VER >= 30.
Limits don't apply when DSC is enabled.

The helper returns the upper limit for the platforms, capped to the
max dotclock (khz).

For the currently supported versions of HDMI, pixel clock is already
limited to 600Mhz so nothing needs to be done there as of now.

v2:
 - Add this limit to the new helper.
v3:
 - Rename helper to intel_max_uncompressed_dotclock(). (Imre)
 - Limit only for PTL and cap the limit to max_dotclock. (Imre)

BSpec: 49199, 68912
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display.h |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c      |  3 +++
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7491e00e3858..9cfeb5530fd8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8001,6 +8001,17 @@ void intel_setup_outputs(struct intel_display *display)
 	drm_helper_move_panel_connectors_to_head(display->drm);
 }
 
+int intel_max_uncompressed_dotclock(struct intel_display *display)
+{
+	int max_dotclock = display->cdclk.max_dotclk_freq;
+	int limit = max_dotclock;
+
+	if (DISPLAY_VER(display) >= 30)
+		limit = 1350000;
+
+	return min(max_dotclock, limit);
+}
+
 static int max_dotclock(struct intel_display *display)
 {
 	int max_dotclock = display->cdclk.max_dotclk_freq;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index f8e6e4e82722..0e9192da601d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -488,6 +488,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 				    struct intel_link_m_n *m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
+int intel_max_uncompressed_dotclock(struct intel_display *display);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9eba8f90bc90..6584e28ab2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1465,6 +1465,9 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 									 target_clock,
 									 htotal,
 									 dsc_slice_count);
+	else
+		effective_dotclk_limit =
+			intel_max_uncompressed_dotclock(display) * num_joined_pipes;
 
 	return target_clock <= effective_dotclk_limit;
 }
-- 
2.45.2

[PATCH 16/16] drm/i915/display: Extend the max dotclock limit to WCL and pre PTL platforms

[Ankit Nautiyal]

From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add upper limit check for pixel clock for WCL and pre PTL platforms.

BSpec: 49199, 68912
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9cfeb5530fd8..2cd950b57918 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8006,8 +8006,14 @@ int intel_max_uncompressed_dotclock(struct intel_display *display)
 	int max_dotclock = display->cdclk.max_dotclk_freq;
 	int limit = max_dotclock;
 
-	if (DISPLAY_VER(display) >= 30)
+	if (DISPLAY_VERx100(display) == 3002)
+		limit = 937500;
+	else if (DISPLAY_VER(display) >= 30)
 		limit = 1350000;
+	else if (DISPLAY_VER(display) >= 13)
+		limit = 1200000;
+	else
+		limit = 1100000;
 
 	return min(max_dotclock, limit);
 }
-- 
2.45.2

✓ i915.CI.BAT: success for Account for DSC bubble overhead for horizontal slices (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5216 bytes --]

== Series Details ==

Series: Account for DSC bubble overhead for horizontal slices (rev4)
URL   : https://patchwork.freedesktop.org/series/152804/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17900 -> Patchwork_152804v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/index.html

Participating hosts (42 -> 41)
------------------------------

  Additional (1): bat-adls-6 
  Missing    (2): bat-dg2-13 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_152804v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adls-6:         NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - bat-adls-6:         NOTRUN -> [SKIP][2] ([i915#3282])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adls-6:         NOTRUN -> [SKIP][5] ([i915#7707]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adls-6:         NOTRUN -> [SKIP][6] ([i915#4103]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-adls-6:         NOTRUN -> [SKIP][7] ([i915#3555] / [i915#3840])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adls-6:         NOTRUN -> [SKIP][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#5354])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-adls-6:         NOTRUN -> [SKIP][10] ([i915#1072] / [i915#9732]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#3555])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adls-6:         NOTRUN -> [SKIP][12] ([i915#3291]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-adls-6/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_17900 -> Patchwork_152804v4

  CI-20190529: 20190529
  CI_DRM_17900: 8059f097e25f736bb3da09af6a9b283079abfd4f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_152804v4: 8059f097e25f736bb3da09af6a9b283079abfd4f @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/index.html

[-- Attachment #2: Type: text/html, Size: 6262 bytes --]

Re: [PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:24PM +0530, Ankit Nautiyal wrote:
> Currently in intel_dp_mode_valid(), we compute the number of joined pipes
> required before deciding whether DSC is needed. This ordering prevents us
> from accounting for DSC-related overhead when determining pipe
> requirements.
> 
> It is not possible to first decide whether DSC is needed and then compute
> the required number of joined pipes, because the two depend on each other:
> 
>  - DSC need is a function of the pipe count (e.g., 4‑pipe always requires
>    DSC; 2‑pipe may require it if uncompressed joiner is unavailable).
> 
>  - Whether a given pipe‑join configuration is sufficient depends on
>    effective bandwidth, which itself changes when DSC is used.
> 
> As a result, the only correct approach is to iterate candidate pipe counts.
> 
> So, refactor the logic to start with a single pipe and incrementally try
> additional pipes only if needed. While DSC overhead is not yet computed
> here, this restructuring prepares the code to support that in a follow-up
> changes.
> 
> Additionally, if a forced joiner configuration is present, we first check
> whether it satisfies the bandwidth and timing constraints. If it does not,
> we fall back to evaluating configurations with 1, 2, or 4 pipes joined
> and prune or keep the mode accordingly.
> 
> v2:
>  - Iterate over number of pipes to be joined instead of joiner
>    candidates. (Jani)
>  - Document the rationale of iterating over number of joined pipes.
>    (Imre)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 158 +++++++++++++++---------
>  1 file changed, 103 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4c3a1b6d0015..599965a6e1a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
>  	return true;
>  }
>  
> +static
> +bool intel_dp_can_join(struct intel_display *display,
> +		       int num_joined_pipes)
> +{
> +	switch (num_joined_pipes) {
> +	case 1:
> +		return true;
> +	case 2:
> +		return HAS_BIGJOINER(display) ||
> +		       HAS_UNCOMPRESSED_JOINER(display);
> +	case 4:
> +		return HAS_ULTRAJOINER(display);
> +	default:
> +		return false;
> +	}
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid(struct drm_connector *_connector,
>  		    const struct drm_display_mode *mode)
> @@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	const struct drm_display_mode *fixed_mode;
>  	int target_clock = mode->clock;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
> -	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	u16 dsc_max_compressed_bpp = 0;
>  	u8 dsc_slice_count = 0;
>  	enum drm_mode_status status;
>  	bool dsc = false;
>  	int num_joined_pipes;
>  	int link_bpp_x16;
> +	int num_pipes;
>  
>  	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
> @@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  					   target_clock, mode->hdisplay,
>  					   link_bpp_x16, 0);
>  
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     mode->hdisplay, target_clock);
> -	max_dotclk *= num_joined_pipes;
> -
> -	if (target_clock > max_dotclk)
> -		return MODE_CLOCK_HIGH;
> -
> -	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
> -	if (status != MODE_OK)
> -		return status;
> -
> -	if (intel_dp_has_dsc(connector)) {
> -		int pipe_bpp;
> -
> -		/*
> -		 * TBD pass the connector BPC,
> -		 * for now U8_MAX so that max BPC on that platform would be picked
> -		 */
> -		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
> -
> -		/*
> -		 * Output bpp is stored in 6.4 format so right shift by 4 to get the
> -		 * integer value since we support only integer values of bpp.
> -		 */
> -		if (intel_dp_is_edp(intel_dp)) {
> -			dsc_max_compressed_bpp =
> -				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
> -
> -			dsc_slice_count =
> -				intel_dp_dsc_get_slice_count(connector,
> -							     target_clock,
> -							     mode->hdisplay,
> -							     num_joined_pipes);
> -
> -			dsc = dsc_max_compressed_bpp && dsc_slice_count;
> -		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> -			unsigned long bw_overhead_flags = 0;
> -
> -			if (!drm_dp_is_uhbr_rate(max_link_clock))
> -				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> -
> -			dsc = intel_dp_mode_valid_with_dsc(connector,
> -							   max_link_clock, max_lanes,
> -							   target_clock, mode->hdisplay,
> -							   num_joined_pipes,
> -							   output_format, pipe_bpp,
> -							   bw_overhead_flags);
> +	/*
> +	 * We cannot determine the required pipe‑join count before knowing whether
> +	 * DSC is needed, nor can we determine DSC need without knowing the pipe
> +	 * count.
> +	 * Because of this dependency cycle, the only correct approach is to iterate
> +	 * over candidate pipe counts and evaluate each combination.
> +	 */
> +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int max_dotclk = display->cdclk.max_dotclk_freq;
> +
> +		status = MODE_CLOCK_HIGH;
> +
> +		if (num_pipes == 0) {
> +			if (!connector->force_joined_pipes)
> +				continue;
> +			num_joined_pipes = connector->force_joined_pipes;
> +		} else {
> +			num_joined_pipes = num_pipes;
> +		}

The current way is to try connector->force_joined_pipes and fail the
commit if that doesn't work. Here you'd change that to fall back trying
non-forced pipe-joined configs in that case. If that's needed (not sure
if that's a good idea, since then the user wouldn't know which case
succeeded or failed), it should be a separate change. Here it could be
simply an if (forced_joined_pipes && num_pipes != forced_joined_pipes)
continue and then use num_pipes instead of num_joined_pipes later in the
loop.

> +
> +		if (!intel_dp_can_join(display, num_joined_pipes))
> +			continue;
> +
> +		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +			continue;
> +
> +		status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
> +		if (status != MODE_OK)
> +			continue;
> +
> +		if (intel_dp_has_dsc(connector)) {
> +			int pipe_bpp;
> +
> +			/*
> +			 * TBD pass the connector BPC,
> +			 * for now U8_MAX so that max BPC on that platform would be picked
> +			 */
> +			pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
> +
> +			/*
> +			 * Output bpp is stored in 6.4 format so right shift by 4 to get the
> +			 * integer value since we support only integer values of bpp.
> +			 */
> +			if (intel_dp_is_edp(intel_dp)) {
> +				dsc_max_compressed_bpp =
> +					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
> +
> +				dsc_slice_count =
> +					intel_dp_dsc_get_slice_count(connector,
> +								     target_clock,
> +								     mode->hdisplay,
> +								     num_joined_pipes);
> +
> +				dsc = dsc_max_compressed_bpp && dsc_slice_count;
> +			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> +				unsigned long bw_overhead_flags = 0;
> +
> +				if (!drm_dp_is_uhbr_rate(max_link_clock))
> +					bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> +
> +				dsc = intel_dp_mode_valid_with_dsc(connector,
> +								   max_link_clock, max_lanes,
> +								   target_clock, mode->hdisplay,
> +								   num_joined_pipes,
> +								   output_format, pipe_bpp,
> +								   bw_overhead_flags);
> +			}
> +		}
> +
> +		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
> +			continue;
> +
> +		if (mode_rate > max_rate && !dsc)
> +			continue;
> +
> +		status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> +		if (status != MODE_OK)
> +			continue;
> +
> +		max_dotclk *= num_joined_pipes;
> +
> +		if (target_clock <= max_dotclk) {
> +			status = MODE_OK;

status stays MODE_OK if target_clock > max_dotclk.

> +			break;
>  		}
>  	}
>  
> -	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
> -		return MODE_CLOCK_HIGH;
> -
> -	status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
>  	if (status != MODE_OK)
>  		return status;
>  
> -	if (mode_rate > max_rate && !dsc)
> -		return MODE_CLOCK_HIGH;
> -
>  	return intel_dp_mode_valid_downstream(connector, mode, target_clock);
> +

Extra w/s.

>  }
>  
>  bool intel_dp_source_supports_tps3(struct intel_display *display)
> -- 
> 2.45.2
> 

Re: [PATCH 05/16] drm/i915/dp: Rework pipe joiner logic in compute_config

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:25PM +0530, Ankit Nautiyal wrote:
> Currently, the number of joined pipes are determined early in the flow,
> which limits flexibility for accounting DSC slice overhead. To address
> this, recompute the joined pipe count during DSC configuration.
> 
> Refactor intel_dp_dsc_compute_config() to iterate over joiner candidates
> and select the minimal joiner configuration that satisfies the mode
> requirements. This prepares the logic for future changes that will
> consider DSC slice overhead.
> 
> v2:
>  - Rename helper to intel_dp_compute_link_for_joined_pipes(). (Imre)
>  - Move the check for max dotclock inside the helper so that if dotclock
>    check fails for non DSC case for a given number of joined pipes, we
>    are able to fallback to the DSC mode. (Imre)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 93 ++++++++++++++++++++-----
>  1 file changed, 77 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 599965a6e1a6..f8986f0acc79 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2804,33 +2804,23 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
>  }
>  
>  static int
> -intel_dp_compute_link_config(struct intel_encoder *encoder,
> -			     struct intel_crtc_state *pipe_config,
> -			     struct drm_connector_state *conn_state,
> -			     bool respect_downstream_limits)
> +intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
> +				       struct intel_crtc_state *pipe_config,
> +				       struct drm_connector_state *conn_state,
> +				       bool respect_downstream_limits)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> +	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode =
>  		&pipe_config->hw.adjusted_mode;
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	struct link_config_limits limits;
>  	bool dsc_needed, joiner_needs_dsc;
> -	int num_joined_pipes;
>  	int ret = 0;
>  
> -	if (pipe_config->fec_enable &&
> -	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
> -		return -EINVAL;
> -
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     adjusted_mode->crtc_hdisplay,
> -						     adjusted_mode->crtc_clock);
> -	if (num_joined_pipes > 1)
> -		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
> -
>  	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
>  
>  	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
> @@ -2880,6 +2870,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			return ret;
>  	}
>  
> +	max_dotclk *= num_joined_pipes;
> +
> +	if (adjusted_mode->crtc_clock > max_dotclk)
> +		return -EINVAL;

When you make max_dotclk dependent on dsc vs. non-dsc mode later in the
patchset, this also needs to be checked for the non-dsc case as well
earlier in the function, falling back to dsc if crtc_clock is too high
for it (as for non-dsc max_dotclk may be lower than for dsc). I suppose
it's easier to move this check earlier already in this patch and later
change the error return to be a fallback, rechecking the clock for dsc
as well here.

> +
>  	drm_dbg_kms(display->drm,
>  		    "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
>  		    pipe_config->lane_count, pipe_config->port_clock,
> @@ -2893,6 +2888,72 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	return 0;
>  }
>  
> +static int
> +intel_dp_compute_link_config(struct intel_encoder *encoder,
> +			     struct intel_crtc_state *crtc_state,
> +			     struct drm_connector_state *conn_state,
> +			     bool respect_downstream_limits)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_connector *connector =
> +		to_intel_connector(conn_state->connector);
> +	const struct drm_display_mode *adjusted_mode =
> +		&crtc_state->hw.adjusted_mode;
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	int num_joined_pipes;
> +	int num_pipes;
> +	int ret = 0;
> +
> +	if (crtc_state->fec_enable &&
> +	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
> +		return -EINVAL;
> +

Even though num_pipes == 1 should always work, for clarity I initialize
ret to -EINVAL explicitly for the case where no pipes would work. Not
doing a fallback from a forced joined-pipe config would need this
anyway.

> +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		if (num_pipes == 0) {
> +			if (!connector->force_joined_pipes)
> +				continue;
> +			num_joined_pipes = connector->force_joined_pipes;
> +		} else {
> +			num_joined_pipes = num_pipes;
> +		}

As in the previous patch, I'd just skip the force_joined_pipes &&
num_pipes != force_joined_pipes case.

> +
> +		if (!intel_dp_can_join(display, num_joined_pipes))
> +			continue;
> +
> +		if (adjusted_mode->hdisplay >
> +		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +			continue;
> +
> +		/*
> +		 * NOTE:
> +		 * The crtc_state->joiner_pipes should have been set at the end
> +		 * only if all the conditions are met. However that would mean
> +		 * that num_joined_pipes is passed around to all helpers and
> +		 * make them use it instead of using crtc_state->joiner_pipes
> +		 * directly or indirectly (via intel_crtc_num_joined_pipes()).
> +		 *
> +		 * For now, setting crtc_state->joiner_pipes to the candidate
> +		 * value to avoid the above churn and resetting it to 0, in case
> +		 * no joiner candidate is found to be suitable for the given
> +		 * configuration.
> +		 */
> +		if (num_joined_pipes > 1)
> +			crtc_state->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
> +							   crtc->pipe);
> +
> +		ret = intel_dp_compute_link_for_joined_pipes(encoder, crtc_state, conn_state,
> +							     respect_downstream_limits);
> +		if (ret == 0)
> +			break;
> +	}
> +
> +	if (ret < 0)
> +		crtc_state->joiner_pipes = 0;
> +
> +	return ret;
> +}
> +
>  bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state)
>  {
> -- 
> 2.45.2
> 

Re: [PATCH 06/16] drm/i915/dp_mst: Move the check for dotclock at the end

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:26PM +0530, Ankit Nautiyal wrote:
> Refactor the mode_valid to have all joiner dependent stuff together and
> place the check for dotclock limit at the very end.
> 
> This will help in the following refactor to iterate over the joiner
> candidates and find the best joiner candidate that satisfy all checks
> and limits.
> 
> v2: Update status to MODE_CLOCK_HIGH if max_dotclock check fails. (Imre)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 ++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 24f8e60df9ac..24b0020acad0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1470,20 +1470,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	 *   corresponding link capabilities of the sink) in case the
>  	 *   stream is uncompressed for it by the last branch device.
>  	 */
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     mode->hdisplay, target_clock);
> -	max_dotclk *= num_joined_pipes;
> -
>  	ret = drm_modeset_lock(&mgr->base.lock, ctx);
>  	if (ret)
>  		return ret;
>  
> -	if (mode_rate > max_rate || mode->clock > max_dotclk ||
> +	if (mode_rate > max_rate ||
>  	    drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
>  		*status = MODE_CLOCK_HIGH;
>  		return 0;
>  	}
>  
> +	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> +						     mode->hdisplay, target_clock);
> +
>  	if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>  		/*
>  		 * TBD pass the connector BPC,
> @@ -1513,6 +1512,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	}
>  
>  	*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> +
> +	if (*status != MODE_OK)
> +		return 0;
> +
> +	max_dotclk *= num_joined_pipes;
> +
> +	if (mode->clock > max_dotclk) {
> +		*status = MODE_CLOCK_HIGH;
> +		return 0;
> +	}
> +
> +	*status = MODE_OK;

*status is guaranteed to be MODE_OK at this point, so the above could be
dropped (along with the return 0; in the mode->clock > max_dotclk case).
In any case:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
>  	return 0;
>  }
>  
> -- 
> 2.45.2
> 

✗ i915.CI.Full: failure for Account for DSC bubble overhead for horizontal slices (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 113053 bytes --]

== Series Details ==

Series: Account for DSC bubble overhead for horizontal slices (rev4)
URL   : https://patchwork.freedesktop.org/series/152804/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17900_full -> Patchwork_152804v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_152804v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_152804v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_152804v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rps@engine-order:
    - shard-mtlp:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-5/igt@i915_pm_rps@engine-order.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-5/igt@i915_pm_rps@engine-order.html

  * igt@kms_pipe_stress@stress-xrgb8888-untiled:
    - shard-mtlp:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-5/igt@kms_pipe_stress@stress-xrgb8888-untiled.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-5/igt@kms_pipe_stress@stress-xrgb8888-untiled.html

  
Known issues
------------

  Here are the changes found in Patchwork_152804v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#6230])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@api_intel_bb@crc32.html

  * igt@device_reset@cold-reset-bound:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@device_reset@cold-reset-bound.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu-1:       NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][8] ([i915#12392] / [i915#13356])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][9] ([i915#7697])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_eio@kms:
    - shard-tglu:         NOTRUN -> [DMESG-WARN][10] ([i915#13363])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@hog:
    - shard-dg2:          NOTRUN -> [SKIP][11] ([i915#4812])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@gem_exec_balancer@hog.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglu:         NOTRUN -> [SKIP][12] ([i915#4525])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][13] ([i915#4525])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglu-1:       NOTRUN -> [SKIP][14] ([i915#6344])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#3281]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][16] ([i915#2190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-glk:          NOTRUN -> [SKIP][17] ([i915#4613]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk9/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#4613])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-tglu:         NOTRUN -> [SKIP][19] ([i915#4613]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-tglu-1:       NOTRUN -> [SKIP][20] ([i915#4613]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#4613])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_mmap_wc@write-wc-read-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#4083])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@gem_mmap_wc@write-wc-read-gtt.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][23] ([i915#3282]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-tglu:         NOTRUN -> [SKIP][24] ([i915#13398])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#5190] / [i915#8428])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][26] +140 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#8411]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][28] ([i915#13809])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#3297]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][30] ([i915#3297]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen3_render_tiledy_blits:
    - shard-mtlp:         NOTRUN -> [SKIP][31] +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu:         NOTRUN -> [SKIP][32] ([i915#2527] / [i915#2856])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#2856])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#2527]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_drm_fdinfo@most-busy-check-all@bcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#14073]) +6 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@i915_drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu-1:       NOTRUN -> [SKIP][36] ([i915#8399])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#8399])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu-1:       NOTRUN -> [WARN][38] ([i915#13790] / [i915#2681]) +1 other test warn
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][39] ([i915#13356])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk6/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#4387])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][41] -> [SKIP][42] ([i915#7984])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-6/igt@i915_power@sanity.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-2/igt@i915_power@sanity.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#6188])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_selftest@live:
    - shard-mtlp:         [PASS][44] -> [DMESG-FAIL][45] ([i915#12061] / [i915#15560])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-5/igt@i915_selftest@live.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-5/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [PASS][46] -> [DMESG-FAIL][47] ([i915#12061])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-5/igt@i915_selftest@live@workarounds.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-5/igt@i915_selftest@live@workarounds.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-rkl:          [PASS][48] -> [INCOMPLETE][49] ([i915#4817])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#5286]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglu-1:       NOTRUN -> [SKIP][51] ([i915#5286]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#5286]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][53] -> [FAIL][54] ([i915#5138])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][55] +7 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - shard-dg1:          [PASS][56] -> [DMESG-WARN][57] ([i915#4423])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg1-19/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-18/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#10307] / [i915#6095]) +98 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][59] ([i915#6095]) +43 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#6095]) +151 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#6095]) +41 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][63] ([i915#6095]) +19 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#14098] / [i915#6095]) +23 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][65] ([i915#12805])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#6095]) +19 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-glk:          NOTRUN -> [INCOMPLETE][67] ([i915#15582]) +1 other test incomplete
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk6/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][68] ([i915#12313]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#14544] / [i915#6095]) +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#14098] / [i915#14544] / [i915#6095]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][71] ([i915#12313])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#13781]) +3 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-dg2:          NOTRUN -> [SKIP][73] +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#11151] / [i915#7828])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-tglu:         NOTRUN -> [SKIP][75] ([i915#11151] / [i915#7828]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#11151] / [i915#7828]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-5/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#11151] / [i915#7828]) +4 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_color@deep-color:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#12655] / [i915#3555])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-tglu-1:       NOTRUN -> [SKIP][79] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#15330])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-tglu:         NOTRUN -> [SKIP][81] ([i915#6944])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#6944] / [i915#9424])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][83] ([i915#6944])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_content_protection@suspend-resume.html

  * igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][84] ([i915#7173]) +2 other tests fail
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-3.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#13049])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#3555]) +2 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][87] ([i915#13566]) +2 other tests fail
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-8/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu-1:       NOTRUN -> [FAIL][88] ([i915#13566]) +1 other test fail
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#13049])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][90] -> [FAIL][91] ([i915#13566]) +3 other tests fail
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-tglu-6/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-6/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-tglu:         NOTRUN -> [SKIP][92] ([i915#4103])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#3804])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#13748])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#13748])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#13707])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#3840])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-rkl:          [PASS][98] -> [INCOMPLETE][99] ([i915#9878])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_fbcon_fbt@fbc-suspend.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@psr2:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#658])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#9934]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][102] ([i915#12745] / [i915#4839])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk9/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#9934])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][104] ([i915#4839])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk9/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#3637] / [i915#9934]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#3637] / [i915#9934]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#2672] / [i915#3555])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][108] ([i915#2587] / [i915#2672])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#2672] / [i915#3555]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#15573]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#2672]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#2587] / [i915#2672] / [i915#3555])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][113] ([i915#2587] / [i915#2672])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#2672] / [i915#3555])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#2672])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#15573]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][117] ([i915#1825])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][118] ([i915#15574]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][119] ([i915#10056])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk10/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#5439])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][121] ([i915#15102]) +7 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#15102]) +2 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][123] ([i915#15102]) +10 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] +31 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
    - shard-glk10:        NOTRUN -> [SKIP][125] +135 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-rte:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#1825]) +16 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][127] ([i915#15574])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#15102] / [i915#3458])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#15102] / [i915#3023]) +6 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#8708]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][131] +29 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#5354]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][133] ([i915#3555] / [i915#8228]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_hdr@bpc-switch-suspend.html
    - shard-dg2:          [PASS][134] -> [SKIP][135] ([i915#3555] / [i915#8228])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-11/igt@kms_hdr@bpc-switch-suspend.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#3555] / [i915#8228])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#3555] / [i915#8228])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#15459])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#15458])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#1839] / [i915#4816])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#15608] / [i915#8825]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier@pipe-a-plane-3:
    - shard-tglu:         NOTRUN -> [SKIP][142] ([i915#15608]) +8 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier@pipe-a-plane-3.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-5:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#15608]) +22 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#15608] / [i915#15609] / [i915#8825])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-0:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#15608]) +3 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#15609])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-b-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#15609] / [i915#8825])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#15608] / [i915#8825]) +3 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][149] ([i915#15608] / [i915#8825]) +5 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#15609]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-b-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][151] ([i915#15608]) +11 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-b-plane-5.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#13958])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          [PASS][153] -> [SKIP][154] ([i915#6953] / [i915#9423])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b:
    - shard-tglu-1:       NOTRUN -> [SKIP][155] ([i915#15329]) +4 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#9812])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#9685])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          NOTRUN -> [FAIL][158] ([i915#9295])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][159] ([i915#4281])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [PASS][160] -> [SKIP][161] ([i915#9340])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-4/igt@kms_pm_lpsp@kms-lpsp.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-tglu-1:       NOTRUN -> [SKIP][162] ([i915#3828])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          [PASS][163] -> [SKIP][164] ([i915#15073]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
    - shard-rkl:          [PASS][165] -> [SKIP][166] ([i915#15073]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg1:          [PASS][167] -> [SKIP][168] ([i915#15073])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-12/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-rkl:          [PASS][169] -> [INCOMPLETE][170] ([i915#14419])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_pm_rpm@system-suspend-modeset.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][171] ([i915#11520]) +4 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#11520]) +4 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][173] ([i915#11520]) +3 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-glk10:        NOTRUN -> [SKIP][174] ([i915#11520]) +3 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk10/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
    - shard-glk:          NOTRUN -> [SKIP][175] ([i915#11520]) +2 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk6/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglu:         NOTRUN -> [SKIP][176] ([i915#9683]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][177] ([i915#9732]) +9 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_psr@fbc-psr2-cursor-blt.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#9732]) +9 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-primary-blt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][179] ([i915#9688]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@kms_psr@fbc-psr2-primary-blt@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9732]) +6 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@fbc-psr2-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][181] ([i915#1072] / [i915#9732])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_psr@fbc-psr2-suspend.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          NOTRUN -> [INCOMPLETE][182] ([i915#15500])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk9/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-rkl:          NOTRUN -> [SKIP][183] ([i915#3555])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-tglu-1:       NOTRUN -> [SKIP][184] ([i915#3555]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#3555] / [i915#9906])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@kms_vrr@negative-basic.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#2435])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@perf@per-context-mode-unprivileged.html

  * igt@perf_pmu@module-unload:
    - shard-tglu:         NOTRUN -> [FAIL][187] ([i915#14433])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-8/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#3291] / [i915#3708])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#3708])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-4/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7:
    - shard-tglu-1:       NOTRUN -> [FAIL][190] ([i915#12910]) +9 other tests fail
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-tglu:         NOTRUN -> [FAIL][191] ([i915#12910])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-3/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][192] ([i915#12392] / [i915#13356]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-5/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [INCOMPLETE][194] ([i915#13356]) -> [PASS][195] +1 other test pass
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@gem_exec_suspend@basic-s0.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [ABORT][196] ([i915#14809]) -> [PASS][197] +1 other test pass
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-6/igt@gem_mmap_offset@clear-via-pagefault.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-4/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-rkl:          [INCOMPLETE][198] ([i915#13356]) -> [PASS][199]
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_workarounds@suspend-resume-fd.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_module_load@load:
    - shard-snb:          ([PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [SKIP][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223]) -> ([PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb4/igt@i915_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb4/igt@i915_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb4/igt@i915_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb7/igt@i915_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb7/igt@i915_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb4/igt@i915_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@i915_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb1/igt@i915_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb7/igt@i915_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb6/igt@i915_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@i915_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb1/igt@i915_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb4/igt@i915_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@i915_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb6/igt@i915_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb1/igt@i915_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb7/igt@i915_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@i915_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb6/igt@i915_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb7/igt@i915_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb1/igt@i915_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb1/igt@i915_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@i915_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb6/igt@i915_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@i915_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@i915_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@i915_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@i915_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@i915_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb4/igt@i915_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb4/igt@i915_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb4/igt@i915_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb4/igt@i915_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb4/igt@i915_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb5/igt@i915_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb5/igt@i915_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb5/igt@i915_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb5/igt@i915_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb5/igt@i915_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb6/igt@i915_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb6/igt@i915_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb6/igt@i915_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb6/igt@i915_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb6/igt@i915_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb7/igt@i915_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb7/igt@i915_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb7/igt@i915_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb7/igt@i915_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb7/igt@i915_module_load@load.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [FAIL][249] ([i915#5956]) -> [PASS][250] +1 other test pass
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][251] ([i915#15582]) -> [PASS][252] +1 other test pass
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-rkl:          [FAIL][253] ([i915#13566]) -> [PASS][254]
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-128x42.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][255] ([i915#13566]) -> [PASS][256] +1 other test pass
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-tglu-8/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-tglu-5/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         [FAIL][257] ([i915#2346]) -> [PASS][258]
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-mtlp-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          [SKIP][259] ([i915#3555]) -> [PASS][260]
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-snb:          [TIMEOUT][261] ([i915#14033] / [i915#14350]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1:
    - shard-snb:          [TIMEOUT][263] ([i915#14033]) -> [PASS][264]
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-snb5/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-snb1/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_hdr@bpc-switch:
    - shard-rkl:          [SKIP][265] ([i915#3555] / [i915#8228]) -> [PASS][266]
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_hdr@bpc-switch.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_hdr@bpc-switch.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [SKIP][267] ([i915#15459]) -> [PASS][268]
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
    - shard-rkl:          [INCOMPLETE][269] ([i915#14412]) -> [PASS][270] +1 other test pass
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          [SKIP][271] ([i915#15073]) -> [PASS][272]
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html
    - shard-rkl:          [SKIP][273] ([i915#15073]) -> [PASS][274] +1 other test pass
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-8/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg1:          [SKIP][275] ([i915#15073]) -> [PASS][276]
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-12/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_properties@connector-properties-legacy:
    - shard-dg2:          [FAIL][277] -> [PASS][278]
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-11/igt@kms_properties@connector-properties-legacy.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@kms_properties@connector-properties-legacy.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][279] ([i915#4349]) -> [PASS][280] +4 other tests pass
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-3/igt@perf_pmu@busy-double-start@vecs1.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][281] ([i915#11078] / [i915#14544]) -> [SKIP][282] ([i915#11078])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][283] ([i915#14544] / [i915#9323]) -> [SKIP][284] ([i915#9323])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][285] ([i915#13008] / [i915#14544]) -> [SKIP][286] ([i915#13008])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          [SKIP][287] ([i915#280]) -> [SKIP][288] ([i915#14544] / [i915#280])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@gem_ctx_sseu@engines.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_ctx_sseu@engines.html

  * igt@gem_eio@kms:
    - shard-rkl:          [DMESG-WARN][289] ([i915#13363]) -> [ABORT][290] ([i915#13363])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gem_eio@kms.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_eio@kms.html

  * igt@gem_exec_reloc@basic-concurrent0:
    - shard-rkl:          [SKIP][291] ([i915#3281]) -> [SKIP][292] ([i915#14544] / [i915#3281]) +3 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@gem_exec_reloc@basic-concurrent0.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_exec_reloc@basic-concurrent0.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-rkl:          [SKIP][293] ([i915#14544] / [i915#3281]) -> [SKIP][294] ([i915#3281]) +3 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_exec_reloc@basic-range-active.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][295] ([i915#4613] / [i915#7582]) -> [SKIP][296] ([i915#14544] / [i915#4613] / [i915#7582])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gem_lmem_evict@dontneed-evict-race.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@massive:
    - shard-rkl:          [SKIP][297] ([i915#14544] / [i915#4613]) -> [SKIP][298] ([i915#4613])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_lmem_swapping@massive.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_lmem_swapping@massive.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-rkl:          [SKIP][299] ([i915#4613]) -> [SKIP][300] ([i915#14544] / [i915#4613])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gem_lmem_swapping@verify-ccs.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_pread@display:
    - shard-rkl:          [SKIP][301] ([i915#3282]) -> [SKIP][302] ([i915#14544] / [i915#3282])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gem_pread@display.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_pread@display.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][303] ([i915#14544] / [i915#3282]) -> [SKIP][304] ([i915#3282]) +3 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          [SKIP][305] ([i915#14544] / [i915#3282] / [i915#3297]) -> [SKIP][306] ([i915#3282] / [i915#3297])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_userptr_blits@forbidden-operations.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
    - shard-rkl:          [SKIP][307] ([i915#3297]) -> [SKIP][308] ([i915#14544] / [i915#3297])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gem_userptr_blits@readonly-pwrite-unsync.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-rkl:          [SKIP][309] ([i915#14544] / [i915#3297]) -> [SKIP][310] ([i915#3297])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gem_userptr_blits@readonly-unsync.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-rkl:          [SKIP][311] ([i915#14544] / [i915#2527]) -> [SKIP][312] ([i915#2527]) +2 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@gen9_exec_parse@bb-secure.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-rkl:          [SKIP][313] ([i915#2527]) -> [SKIP][314] ([i915#14544] / [i915#2527])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@gen9_exec_parse@bb-start-far.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          [ABORT][315] ([i915#15131]) -> [INCOMPLETE][316] ([i915#4817])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@i915_suspend@debugfs-reader.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@i915_suspend@debugfs-reader.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          [SKIP][317] ([i915#14544] / [i915#7707]) -> [SKIP][318] ([i915#7707])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@intel_hwmon@hwmon-write.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@intel_hwmon@hwmon-write.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][319] ([i915#14544] / [i915#1769] / [i915#3555]) -> [SKIP][320] ([i915#1769] / [i915#3555])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-rkl:          [SKIP][321] ([i915#14544] / [i915#5286]) -> [SKIP][322] ([i915#5286])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-dg1:          [SKIP][323] ([i915#4423] / [i915#5286]) -> [SKIP][324] ([i915#5286])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-16/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [SKIP][325] ([i915#5286]) -> [SKIP][326] ([i915#14544] / [i915#5286]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-rkl:          [SKIP][327] ([i915#14544] / [i915#3638]) -> [SKIP][328] ([i915#3638]) +1 other test skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-90.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][329] ([i915#3638]) -> [SKIP][330] ([i915#14544] / [i915#3638])
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-rkl:          [SKIP][331] -> [SKIP][332] ([i915#14544]) +5 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          [SKIP][333] ([i915#14544]) -> [SKIP][334] +8 other tests skip
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][335] ([i915#14544] / [i915#6095]) -> [SKIP][336] ([i915#6095]) +13 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][337] ([i915#12313]) -> [SKIP][338] ([i915#12313] / [i915#14544])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][339] ([i915#6095]) -> [SKIP][340] ([i915#14544] / [i915#6095]) +6 other tests skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][341] ([i915#14098] / [i915#6095]) -> [SKIP][342] ([i915#14098] / [i915#14544] / [i915#6095]) +10 other tests skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][343] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][344] ([i915#14098] / [i915#6095]) +13 other tests skip
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-rkl:          [SKIP][345] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][346] ([i915#11151] / [i915#7828]) +3 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-rkl:          [SKIP][347] ([i915#11151] / [i915#7828]) -> [SKIP][348] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-rkl:          [SKIP][349] ([i915#14544] / [i915#6944]) -> [SKIP][350] ([i915#6944])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_content_protection@atomic-hdcp14.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          [FAIL][351] ([i915#7173]) -> [SKIP][352] ([i915#6944] / [i915#9424])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-3/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][353] ([i915#6944] / [i915#9424]) -> [SKIP][354] ([i915#14544] / [i915#6944] / [i915#9424])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_content_protection@mei-interface.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_content_protection@mei-interface.html
    - shard-dg1:          [SKIP][355] ([i915#9433]) -> [SKIP][356] ([i915#6944] / [i915#9424])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg1-13/igt@kms_content_protection@mei-interface.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg1-19/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          [SKIP][357] ([i915#6944] / [i915#7118]) -> [FAIL][358] ([i915#7173])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@kms_content_protection@srm.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-rkl:          [SKIP][359] ([i915#14544] / [i915#6944] / [i915#7118] / [i915#9424]) -> [SKIP][360] ([i915#6944] / [i915#7118] / [i915#9424])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_content_protection@uevent.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_content_protection@uevent.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-dg2:          [SKIP][361] ([i915#6944]) -> [FAIL][362] ([i915#7173]) +1 other test fail
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-1/igt@kms_content_protection@uevent-hdcp14.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-11/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          [SKIP][363] ([i915#13049] / [i915#14544]) -> [SKIP][364] ([i915#13049])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-rkl:          [SKIP][365] ([i915#14544] / [i915#3555]) -> [SKIP][366] ([i915#3555]) +1 other test skip
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-max-size.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][367] ([i915#4103]) -> [SKIP][368] ([i915#14544] / [i915#4103]) +1 other test skip
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          [SKIP][369] ([i915#14544] / [i915#9723]) -> [SKIP][370] ([i915#9723])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-rkl:          [SKIP][371] ([i915#13707] / [i915#14544]) -> [SKIP][372] ([i915#13707])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          [SKIP][373] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][374] ([i915#3555] / [i915#3840]) +1 other test skip
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_dsc@dsc-basic.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][375] ([i915#14544] / [i915#3955]) -> [SKIP][376] ([i915#3955])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          [SKIP][377] ([i915#1839]) -> [SKIP][378] ([i915#14544] / [i915#1839])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_feature_discovery@display-3x.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][379] ([i915#658]) -> [SKIP][380] ([i915#14544] / [i915#658])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_feature_discovery@psr1.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          [SKIP][381] ([i915#14544] / [i915#9934]) -> [SKIP][382] ([i915#9934]) +4 other tests skip
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_flip@2x-blocking-wf_vblank.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-rkl:          [SKIP][383] ([i915#9934]) -> [SKIP][384] ([i915#14544] / [i915#9934]) +2 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_flip@2x-flip-vs-modeset.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          [INCOMPLETE][385] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][386] ([i915#12745] / [i915#4839] / [i915#6113])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-glk6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-glk1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][387] ([i915#2672] / [i915#3555]) -> [SKIP][388] ([i915#14544] / [i915#2672] / [i915#3555])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][389] ([i915#2672]) -> [SKIP][390] ([i915#14544] / [i915#2672])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][391] ([i915#14544] / [i915#2672]) -> [SKIP][392] ([i915#2672]) +1 other test skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][393] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][394] ([i915#2672] / [i915#3555]) +1 other test skip
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-rkl:          [SKIP][395] ([i915#14544] / [i915#15574]) -> [SKIP][396] ([i915#15574]) +2 other tests skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][397] ([i915#15102] / [i915#3023]) -> [SKIP][398] ([i915#14544] / [i915#15102] / [i915#3023]) +3 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-rkl:          [SKIP][399] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][400] ([i915#15102] / [i915#3023]) +4 other tests skip
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
    - shard-dg2:          [SKIP][401] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][402] ([i915#15102] / [i915#3458])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-dg2:          [SKIP][403] ([i915#15102] / [i915#3458]) -> [SKIP][404] ([i915#10433] / [i915#15102] / [i915#3458]) +2 other tests skip
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          [SKIP][405] ([i915#14544] / [i915#5439]) -> [SKIP][406] ([i915#5439])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][407] ([i915#15102]) -> [SKIP][408] ([i915#14544] / [i915#15102])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][409] ([i915#14544] / [i915#15102]) -> [SKIP][410] ([i915#15102])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          [SKIP][411] ([i915#14544] / [i915#1825]) -> [SKIP][412] ([i915#1825]) +16 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
    - shard-rkl:          [SKIP][413] ([i915#1825]) -> [SKIP][414] ([i915#14544] / [i915#1825]) +11 other tests skip
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          [SKIP][415] ([i915#13688]) -> [SKIP][416] ([i915#13688] / [i915#14544])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_joiner@basic-max-non-joiner.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-rkl:          [SKIP][417] ([i915#14544] / [i915#14712]) -> [SKIP][418] ([i915#14712])
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-a-plane-0:
    - shard-rkl:          [SKIP][419] ([i915#15608]) -> [SKIP][420] ([i915#14544] / [i915#15608])
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-a-plane-0.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-a-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5:
    - shard-rkl:          [SKIP][421] ([i915#15608] / [i915#8825]) -> [SKIP][422] ([i915#14544] / [i915#15608] / [i915#8825]) +1 other test skip
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][423] ([i915#14544] / [i915#15608] / [i915#15609] / [i915#8825]) -> [SKIP][424] ([i915#15608] / [i915#15609] / [i915#8825])
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping.html
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-a-plane-0:
    - shard-rkl:          [SKIP][425] ([i915#14544] / [i915#15608]) -> [SKIP][426] ([i915#15608])
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-a-plane-0.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-a-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-b-plane-5:
    - shard-rkl:          [SKIP][427] ([i915#14544] / [i915#15609] / [i915#8825]) -> [SKIP][428] ([i915#15609] / [i915#8825])
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][429] ([i915#12343]) -> [SKIP][430] ([i915#12343] / [i915#14544])
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_pm_backlight@brightness-with-dpms.html
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          [SKIP][431] ([i915#14544] / [i915#5354]) -> [SKIP][432] ([i915#5354])
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_pm_backlight@fade-with-dpms.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          [SKIP][433] ([i915#3828]) -> [SKIP][434] ([i915#14544] / [i915#3828])
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_pm_dc@dc5-retention-flops.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-rkl:          [SKIP][435] ([i915#14544] / [i915#9685]) -> [SKIP][436] ([i915#9685])
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_pm_dc@dc6-psr.html
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][437] ([i915#9340]) -> [SKIP][438] ([i915#3828])
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-rkl:          [SKIP][439] ([i915#8430]) -> [SKIP][440] ([i915#14544] / [i915#8430])
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_pm_lpsp@screens-disabled.html
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@package-g7:
    - shard-rkl:          [SKIP][441] ([i915#14544] / [i915#15403]) -> [SKIP][442] ([i915#15403])
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_pm_rpm@package-g7.html
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          [SKIP][443] ([i915#11520]) -> [SKIP][444] ([i915#11520] / [i915#14544]) +3 other tests skip
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][445] ([i915#11520] / [i915#14544]) -> [SKIP][446] ([i915#11520]) +1 other test skip
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          [SKIP][447] ([i915#14544] / [i915#9683]) -> [SKIP][448] ([i915#9683])
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_psr2_su@page_flip-p010.html
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-primary-mmap-cpu:
    - shard-rkl:          [SKIP][449] ([i915#1072] / [i915#9732]) -> [SKIP][450] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_psr@fbc-pr-primary-mmap-cpu.html
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_psr@fbc-pr-primary-mmap-cpu.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-rkl:          [SKIP][451] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][452] ([i915#1072] / [i915#9732]) +8 other tests skip
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-3/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          [SKIP][453] ([i915#9685]) -> [SKIP][454] ([i915#14544] / [i915#9685])
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][455] ([i915#5289]) -> [SKIP][456] ([i915#14544] / [i915#5289])
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-rkl:          [SKIP][457] ([i915#3555]) -> [SKIP][458] ([i915#14544] / [i915#3555]) +1 other test skip
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_setmode@invalid-clone-single-crtc.html
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vrr@flip-dpms:
    - shard-rkl:          [SKIP][459] ([i915#14544] / [i915#15243] / [i915#3555]) -> [SKIP][460] ([i915#15243] / [i915#3555])
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-6/igt@kms_vrr@flip-dpms.html
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-7/igt@kms_vrr@flip-dpms.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][461] ([i915#11920]) -> [SKIP][462] ([i915#11920] / [i915#14544])
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-8/igt@kms_vrr@lobf.html
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          [SKIP][463] ([i915#9906]) -> [SKIP][464] ([i915#14544] / [i915#9906])
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17900/shard-rkl-4/igt@kms_vrr@max-min.html
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/shard-rkl-6/igt@kms_vrr@max-min.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13363]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13363
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14350]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14350
  [i915#14412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14412
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14809
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15500
  [i915#15560]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15560
  [i915#15573]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15573
  [i915#15574]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15574
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15609]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15609
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17900 -> Patchwork_152804v4

  CI-20190529: 20190529
  CI_DRM_17900: 8059f097e25f736bb3da09af6a9b283079abfd4f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_152804v4: 8059f097e25f736bb3da09af6a9b283079abfd4f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_152804v4/index.html

[-- Attachment #2: Type: text/html, Size: 152787 bytes --]

Re: [PATCH 15/16] drm/i915/display: Add upper limit check for pixel clock

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:35PM +0530, Ankit Nautiyal wrote:
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> 
> Add upper limit check for pixel clock for DISPLAY_VER >= 30.
> Limits don't apply when DSC is enabled.
> 
> The helper returns the upper limit for the platforms, capped to the
> max dotclock (khz).
> 
> For the currently supported versions of HDMI, pixel clock is already
> limited to 600Mhz so nothing needs to be done there as of now.
> 
> v2:
>  - Add this limit to the new helper.
> v3:
>  - Rename helper to intel_max_uncompressed_dotclock(). (Imre)
>  - Limit only for PTL and cap the limit to max_dotclock. (Imre)
> 
> BSpec: 49199, 68912
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_display.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c      |  3 +++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7491e00e3858..9cfeb5530fd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8001,6 +8001,17 @@ void intel_setup_outputs(struct intel_display *display)
>  	drm_helper_move_panel_connectors_to_head(display->drm);
>  }
>  
> +int intel_max_uncompressed_dotclock(struct intel_display *display)
> +{
> +	int max_dotclock = display->cdclk.max_dotclk_freq;
> +	int limit = max_dotclock;
> +
> +	if (DISPLAY_VER(display) >= 30)
> +		limit = 1350000;
> +
> +	return min(max_dotclock, limit);
> +}
> +
>  static int max_dotclock(struct intel_display *display)
>  {
>  	int max_dotclock = display->cdclk.max_dotclk_freq;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index f8e6e4e82722..0e9192da601d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -488,6 +488,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  				    struct intel_link_m_n *m_n);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
> +int intel_max_uncompressed_dotclock(struct intel_display *display);
>  enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9eba8f90bc90..6584e28ab2fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1465,6 +1465,9 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>  									 target_clock,
>  									 htotal,
>  									 dsc_slice_count);
> +	else
> +		effective_dotclk_limit =
> +			intel_max_uncompressed_dotclock(display) * num_joined_pipes;
>  
>  	return target_clock <= effective_dotclk_limit;
>  }
> -- 
> 2.45.2
> 

Re: [PATCH 16/16] drm/i915/display: Extend the max dotclock limit to WCL and pre PTL platforms

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:36PM +0530, Ankit Nautiyal wrote:
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> 
> Add upper limit check for pixel clock for WCL and pre PTL platforms.
> 
> BSpec: 49199, 68912
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

I'd like to ask to merge this one patch separately from the patchset
once it's clarified why the limits are not used in Windows for ICL-MTL.

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9cfeb5530fd8..2cd950b57918 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8006,8 +8006,14 @@ int intel_max_uncompressed_dotclock(struct intel_display *display)
>  	int max_dotclock = display->cdclk.max_dotclk_freq;
>  	int limit = max_dotclock;
>  
> -	if (DISPLAY_VER(display) >= 30)
> +	if (DISPLAY_VERx100(display) == 3002)
> +		limit = 937500;
> +	else if (DISPLAY_VER(display) >= 30)
>  		limit = 1350000;
> +	else if (DISPLAY_VER(display) >= 13)
> +		limit = 1200000;
> +	else
> +		limit = 1100000;
>  
>  	return min(max_dotclock, limit);
>  }
> -- 
> 2.45.2
> 

Re: [PATCH 08/16] drm/i915/dp_mst: Rework pipe joiner logic in mode_valid

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:28PM +0530, Ankit Nautiyal wrote:
> Refactor the logic to get the number of joined pipes. Start with a single
> pipe and incrementally try additional pipes only if needed. While DSC
> overhead is not yet computed here, this restructuring prepares the code to
> support that in follow-up changes.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     |  2 -
>  drivers/gpu/drm/i915/display/intel_dp.h     |  3 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 86 ++++++++++++---------
>  3 files changed, 52 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f8986f0acc79..9bbd37ebd2ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1371,7 +1371,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>  	return MODE_OK;
>  }
>  
> -static
>  int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
>  {
>  	return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
> @@ -1434,7 +1433,6 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
>  	return true;
>  }
>  
> -static
>  bool intel_dp_can_join(struct intel_display *display,
>  		       int num_joined_pipes)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 25bfbfd291b0..6d409c1998c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -225,5 +225,8 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
>  				 struct drm_connector_state *conn_state);
>  int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
>  			       bool assume_all_enabled);
> +int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
> +bool intel_dp_can_join(struct intel_display *display,
> +		       int num_joined_pipes);
>  
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f47bf45d0bce..664004600564 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1420,7 +1420,6 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;
>  	struct drm_dp_mst_port *port = connector->mst.port;
>  	const int min_bpp = 18;
> -	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>  	unsigned long bw_overhead_flags =
>  		DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK;
> @@ -1428,6 +1427,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	bool dsc = false;
>  	int target_clock = mode->clock;
>  	int num_joined_pipes;
> +	int num_pipes;
>  
>  	if (drm_connector_is_unregistered(&connector->base)) {
>  		*status = MODE_ERROR;
> @@ -1480,50 +1480,62 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  		return 0;
>  	}
>  
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     mode->hdisplay, target_clock);
> -
> -	if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> -		/*
> -		 * TBD pass the connector BPC,
> -		 * for now U8_MAX so that max BPC on that platform would be picked
> -		 */
> -		int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
> -
> -		if (!drm_dp_is_uhbr_rate(max_link_clock))
> -			bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> -
> -		dsc = intel_dp_mode_valid_with_dsc(connector,
> -						   max_link_clock, max_lanes,
> -						   target_clock, mode->hdisplay,
> -						   num_joined_pipes,
> -						   INTEL_OUTPUT_FORMAT_RGB, pipe_bpp,
> -						   bw_overhead_flags);
> -	}
> +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int max_dotclk = display->cdclk.max_dotclk_freq;
>  
> -	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
>  		*status = MODE_CLOCK_HIGH;
> -		return 0;
> -	}
>  
> -	if (mode_rate > max_rate && !dsc) {
> -		*status = MODE_CLOCK_HIGH;
> -		return 0;
> -	}
> +		if (num_pipes == 0) {
> +			if (!connector->force_joined_pipes)
> +				continue;
> +			num_joined_pipes = connector->force_joined_pipes;
> +		} else {
> +			num_joined_pipes = num_pipes;
> +		}

I'd skip here the force_joined_pipes && force_joined_pipes != num_pipes
case as mentioned earlier.

>  
> -	*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> +		if (!intel_dp_can_join(display, num_joined_pipes))
> +			continue;
>  
> -	if (*status != MODE_OK)
> -		return 0;
> +		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +			continue;
>  
> -	max_dotclk *= num_joined_pipes;
> +		if (intel_dp_has_dsc(connector) &&
> +		    drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> +			/*
> +			 * TBD pass the connector BPC,
> +			 * for now U8_MAX so that max BPC on that platform would be picked
> +			 */
> +			int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>  
> -	if (mode->clock > max_dotclk) {
> -		*status = MODE_CLOCK_HIGH;
> -		return 0;
> -	}
> +			if (!drm_dp_is_uhbr_rate(max_link_clock))
> +				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> +
> +			dsc = intel_dp_mode_valid_with_dsc(connector,
> +							   max_link_clock, max_lanes,
> +							   target_clock, mode->hdisplay,
> +							   num_joined_pipes,
> +							   INTEL_OUTPUT_FORMAT_RGB, pipe_bpp,
> +							   bw_overhead_flags);
> +		}
>  
> -	*status = MODE_OK;
> +		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
> +			continue;
> +
> +		if (mode_rate > max_rate && !dsc)
> +			continue;
> +
> +		*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> +
> +		if (*status != MODE_OK)
> +			continue;
> +
> +		max_dotclk *= num_joined_pipes;
> +
> +		if (mode->clock <= max_dotclk) {
> +			*status = MODE_OK;

*status stays MODE_OK if mode->clock > max_dotclk.

The "histogram" diff algorithm produces for this particular patch a more
readable output.

> +			break;
> +		}
> +	}
>  
>  	return 0;
>  }
> -- 
> 2.45.2
> 

Re: [PATCH 10/16] drm/i915/dp_mst: Rework pipe joiner logic in compute_config

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:30PM +0530, Ankit Nautiyal wrote:
> Similar to the DP SST, refactor `mst_stream_compute_config()` to iterate
> over joiner candidates and select the minimal joiner configuration that
> satisfies the mode requirements. This prepares the logic for future changes
> that will consider DSC slice overhead.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++----
>  1 file changed, 38 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 29ac7b2e1e9c..7a83af89ef03 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -687,6 +687,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	const struct drm_display_mode *adjusted_mode =
>  		&pipe_config->hw.adjusted_mode;
>  	int num_joined_pipes;
> +	int num_pipes;
>  	int ret = 0;
>  
>  	if (pipe_config->fec_enable &&
> @@ -700,17 +701,45 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	pipe_config->has_pch_encoder = false;
>  
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     adjusted_mode->crtc_hdisplay,
> -						     adjusted_mode->crtc_clock);
> +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int max_dotclk = display->cdclk.max_dotclk_freq;
>  
> -	if (num_joined_pipes > 1)
> -		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
> +		ret = -EINVAL;

I suppose in case no valid configuration is found the error code
propagated from this function should be either the error code returned
by the last mst_stream_compute_link_for_joined_pipes() call (which
should also handle the adjusted_mode->clock <= max_dotclk check
internally) for the last valid joined-pipe it was called, or -EINVAL if
there wasn't any valid joined-pipe candidate (and so
mst_stream_compute_link_for_joined_pipes() was never called). The above
ret = -EINVAL could overwrite ret which was set by the last call of
mst_stream_compute_link_for_joined_pipes(). To avoid that I'd init ret =
-EINVAL before the loop.

> +
> +		if (num_pipes == 0) {
> +			if (!connector->force_joined_pipes)
> +				continue;
> +			num_joined_pipes = connector->force_joined_pipes;
> +		} else {
> +			num_joined_pipes = num_pipes;
> +		}

I'd simplify the above as mentioned in earlier patches.

> +
> +		if (!intel_dp_can_join(display, num_joined_pipes))
> +			continue;
> +
> +		if (adjusted_mode->hdisplay >
> +		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +			continue;
> +
> +		if (num_joined_pipes > 1)
> +			pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
> +							    crtc->pipe);
> +
> +		ret = mst_stream_compute_link_for_joined_pipes(encoder,
> +							       pipe_config,
> +							       conn_state,
> +							       num_joined_pipes);
> +		if (ret)
> +			continue;
> +
> +		max_dotclk *= num_joined_pipes;
> +
> +		if (adjusted_mode->clock <= max_dotclk) {
> +			ret = 0;

ret stays 0 if adjusted_mode->clock > max_dotclk (and num_pipes ==
I915_MAX_PIPES - 1). Also, this max_dotclk check should be moved to
mst_stream_compute_link_for_joined_pipes() and checked for both non-dsc
and dsc (falling back to dsc if needed), similarly to the SST case.

> +			break;
> +		}
> +	}
>  
> -	ret = mst_stream_compute_link_for_joined_pipes(encoder,
> -						       pipe_config,
> -						       conn_state,
> -						       num_joined_pipes);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.45.2
> 

Re: [PATCH 10/16] drm/i915/dp_mst: Rework pipe joiner logic in compute_config

[Imre Deak]

On Thu, Jan 29, 2026 at 12:06:16AM +0200, Imre Deak wrote:
> On Wed, Jan 28, 2026 at 07:36:30PM +0530, Ankit Nautiyal wrote:
> > Similar to the DP SST, refactor `mst_stream_compute_config()` to iterate
> > over joiner candidates and select the minimal joiner configuration that
> > satisfies the mode requirements. This prepares the logic for future changes
> > that will consider DSC slice overhead.
> > 
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++----
> >  1 file changed, 38 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 29ac7b2e1e9c..7a83af89ef03 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -687,6 +687,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
> >  	const struct drm_display_mode *adjusted_mode =
> >  		&pipe_config->hw.adjusted_mode;
> >  	int num_joined_pipes;
> > +	int num_pipes;
> >  	int ret = 0;
> >  
> >  	if (pipe_config->fec_enable &&
> > @@ -700,17 +701,45 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
> >  	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >  	pipe_config->has_pch_encoder = false;
> >  
> > -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,

intel_dp_num_joined_pipes() is unused after this, so it can be removed.

> > -						     adjusted_mode->crtc_hdisplay,
> > -						     adjusted_mode->crtc_clock);
> > +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> > +		int max_dotclk = display->cdclk.max_dotclk_freq;
> >  
> > -	if (num_joined_pipes > 1)
> > -		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
> > +		ret = -EINVAL;
> 
> I suppose in case no valid configuration is found the error code
> propagated from this function should be either the error code returned
> by the last mst_stream_compute_link_for_joined_pipes() call (which
> should also handle the adjusted_mode->clock <= max_dotclk check
> internally) for the last valid joined-pipe it was called, or -EINVAL if
> there wasn't any valid joined-pipe candidate (and so
> mst_stream_compute_link_for_joined_pipes() was never called). The above
> ret = -EINVAL could overwrite ret which was set by the last call of
> mst_stream_compute_link_for_joined_pipes(). To avoid that I'd init ret =
> -EINVAL before the loop.
> 
> > +
> > +		if (num_pipes == 0) {
> > +			if (!connector->force_joined_pipes)
> > +				continue;
> > +			num_joined_pipes = connector->force_joined_pipes;
> > +		} else {
> > +			num_joined_pipes = num_pipes;
> > +		}
> 
> I'd simplify the above as mentioned in earlier patches.
> 
> > +
> > +		if (!intel_dp_can_join(display, num_joined_pipes))
> > +			continue;
> > +
> > +		if (adjusted_mode->hdisplay >
> > +		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> > +			continue;
> > +
> > +		if (num_joined_pipes > 1)
> > +			pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
> > +							    crtc->pipe);
> > +
> > +		ret = mst_stream_compute_link_for_joined_pipes(encoder,
> > +							       pipe_config,
> > +							       conn_state,
> > +							       num_joined_pipes);
> > +		if (ret)
> > +			continue;
> > +
> > +		max_dotclk *= num_joined_pipes;
> > +
> > +		if (adjusted_mode->clock <= max_dotclk) {
> > +			ret = 0;
> 
> ret stays 0 if adjusted_mode->clock > max_dotclk (and num_pipes ==
> I915_MAX_PIPES - 1). Also, this max_dotclk check should be moved to
> mst_stream_compute_link_for_joined_pipes() and checked for both non-dsc
> and dsc (falling back to dsc if needed), similarly to the SST case.
> 
> > +			break;
> > +		}
> > +	}
> >  
> > -	ret = mst_stream_compute_link_for_joined_pipes(encoder,
> > -						       pipe_config,
> > -						       conn_state,
> > -						       num_joined_pipes);
> >  	if (ret)
> >  		return ret;
> >  
> > -- 
> > 2.45.2
> > 

Re: [PATCH 11/16] drm/i915/dp: Introduce helper to check pixel rate against dotclock limits

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:31PM +0530, Ankit Nautiyal wrote:
> Add intel_dp_pixel_rate_fits_dotclk() helper, that checks the
      ^intel_dp_dotclk_valid()

> required pixel rate against platform dotclock limit.
> With joined pipes the effective dotclock limit depends upon the number
> of joined pipes.
> 
> Call the helper from the mode_valid phase and from the compute_config
> phase where we need to check the limits for the given target clock for a
> given joiner candidate.
> 
> v2: Rename the helper to intel_dp_dotclk_valid(). (Imre)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Rebased on moving the check from mst_stream_compute_config() to
mst_stream_compute_link_for_joined_pipes() and status/ret fixes
mentioned earlier:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 23 ++++++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_dp.h     |  3 +++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 ++++++-------
>  3 files changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9bbd37ebd2ea..655688c8e6ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1449,6 +1449,18 @@ bool intel_dp_can_join(struct intel_display *display,
>  	}
>  }
>  
> +bool intel_dp_dotclk_valid(struct intel_display *display,
> +			   int target_clock,
> +			   int num_joined_pipes)
> +{
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
> +	int effective_dotclk_limit;
> +
> +	effective_dotclk_limit = max_dotclk * num_joined_pipes;
> +
> +	return target_clock <= effective_dotclk_limit;
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid(struct drm_connector *_connector,
>  		    const struct drm_display_mode *mode)
> @@ -1511,7 +1523,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	 * over candidate pipe counts and evaluate each combination.
>  	 */
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> -		int max_dotclk = display->cdclk.max_dotclk_freq;
>  
>  		status = MODE_CLOCK_HIGH;
>  
> @@ -1582,9 +1593,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  		if (status != MODE_OK)
>  			continue;
>  
> -		max_dotclk *= num_joined_pipes;
> -
> -		if (target_clock <= max_dotclk) {
> +		if (intel_dp_dotclk_valid(display,
> +					  target_clock,
> +					  num_joined_pipes)) {
>  			status = MODE_OK;
>  			break;
>  		}
> @@ -2870,7 +2881,9 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
>  
>  	max_dotclk *= num_joined_pipes;
>  
> -	if (adjusted_mode->crtc_clock > max_dotclk)
> +	if (!intel_dp_dotclk_valid(display,
> +				   adjusted_mode->crtc_clock,
> +				   num_joined_pipes))
>  		return -EINVAL;
>  
>  	drm_dbg_kms(display->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6d409c1998c9..78fa8eaba4ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -228,5 +228,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
>  int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
>  bool intel_dp_can_join(struct intel_display *display,
>  		       int num_joined_pipes);
> +bool intel_dp_dotclk_valid(struct intel_display *display,
> +			   int target_clock,
> +			   int num_joined_pipes);
>  
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7a83af89ef03..f433a01dcfcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -702,7 +702,6 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	pipe_config->has_pch_encoder = false;
>  
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> -		int max_dotclk = display->cdclk.max_dotclk_freq;
>  
>  		ret = -EINVAL;
>  
> @@ -732,9 +731,9 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  		if (ret)
>  			continue;
>  
> -		max_dotclk *= num_joined_pipes;
> -
> -		if (adjusted_mode->clock <= max_dotclk) {
> +		if (intel_dp_dotclk_valid(display,
> +					  adjusted_mode->clock,
> +					  num_joined_pipes)) {
>  			ret = 0;
>  			break;
>  		}
> @@ -1532,7 +1531,6 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	}
>  
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> -		int max_dotclk = display->cdclk.max_dotclk_freq;
>  
>  		*status = MODE_CLOCK_HIGH;
>  
> @@ -1580,9 +1578,9 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  		if (*status != MODE_OK)
>  			continue;
>  
> -		max_dotclk *= num_joined_pipes;
> -
> -		if (mode->clock <= max_dotclk) {
> +		if (intel_dp_dotclk_valid(display,
> +					  mode->clock,
> +					  num_joined_pipes)) {
>  			*status = MODE_OK;
>  			break;
>  		}
> -- 
> 2.45.2
> 

Re: [PATCH 12/16] drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid()

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:32PM +0530, Ankit Nautiyal wrote:
> Make dsc_slice_count closer to the block where it is used and promote it
> from u8 to int. This aligns it with upcoming DSC bubble pixel-rate
> adjustments, where the slice count participates in wider arithmetic.
> 
> Currently, for non-eDP (DP/DP_MST) cases  the slice count is computed only
> inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC
> bubble handling is added, dp_mode_valid() will need access to its own local
> slice count for non-eDP cases as well.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 655688c8e6ef..0acb3b64cf27 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1473,7 +1473,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	int target_clock = mode->clock;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>  	u16 dsc_max_compressed_bpp = 0;
> -	u8 dsc_slice_count = 0;
>  	enum drm_mode_status status;
>  	bool dsc = false;
>  	int num_joined_pipes;
> @@ -1523,6 +1522,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	 * over candidate pipe counts and evaluate each combination.
>  	 */
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int dsc_slice_count = 0;
>  
>  		status = MODE_CLOCK_HIGH;
>  
> @@ -1547,6 +1547,11 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  		if (intel_dp_has_dsc(connector)) {
>  			int pipe_bpp;
>  
> +			dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> +								       target_clock,
> +								       mode->hdisplay,
> +								       num_joined_pipes);
> +
>  			/*
>  			 * TBD pass the connector BPC,
>  			 * for now U8_MAX so that max BPC on that platform would be picked
> @@ -1561,12 +1566,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  				dsc_max_compressed_bpp =
>  					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>  
> -				dsc_slice_count =
> -					intel_dp_dsc_get_slice_count(connector,
> -								     target_clock,
> -								     mode->hdisplay,
> -								     num_joined_pipes);
> -
>  				dsc = dsc_max_compressed_bpp && dsc_slice_count;
>  			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>  				unsigned long bw_overhead_flags = 0;
> -- 
> 2.45.2
> 

Re: [PATCH 13/16] drm/i915/dp: Account for DSC slice overhead

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:33PM +0530, Ankit Nautiyal wrote:
> Account for DSC slice overhead bubbles and adjust the pixel rate while
> checking the pixel rate against the max dotclock limits.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c   |  1 -
>  drivers/gpu/drm/i915/display/intel_vdsc.h   |  3 +++
>  5 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0acb3b64cf27..c1ff92367808 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1451,6 +1451,8 @@ bool intel_dp_can_join(struct intel_display *display,
>  
>  bool intel_dp_dotclk_valid(struct intel_display *display,
>  			   int target_clock,
> +			   int htotal,
> +			   int dsc_slice_count,
>  			   int num_joined_pipes)
>  {
>  	int max_dotclk = display->cdclk.max_dotclk_freq;
> @@ -1458,6 +1460,12 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>  
>  	effective_dotclk_limit = max_dotclk * num_joined_pipes;
>  
> +	if (dsc_slice_count)
> +		target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,
> +									 target_clock,
> +									 htotal,
> +									 dsc_slice_count);
> +
>  	return target_clock <= effective_dotclk_limit;
>  }
>  
> @@ -1592,8 +1600,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  		if (status != MODE_OK)
>  			continue;
>  
> +		if (!dsc)
> +			dsc_slice_count = 0;
> +
>  		if (intel_dp_dotclk_valid(display,
>  					  target_clock,
> +					  mode->htotal,
> +					  dsc_slice_count,
>  					  num_joined_pipes)) {
>  			status = MODE_OK;
>  			break;
> @@ -2827,6 +2840,7 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
>  	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	struct link_config_limits limits;
>  	bool dsc_needed, joiner_needs_dsc;
> +	int dsc_slice_count = 0;
>  	int ret = 0;
>  
>  	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
> @@ -2878,10 +2892,15 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
>  			return ret;
>  	}
>  
> +	if (pipe_config->dsc.compression_enable)
> +		dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
> +
>  	max_dotclk *= num_joined_pipes;
>  
>  	if (!intel_dp_dotclk_valid(display,
>  				   adjusted_mode->crtc_clock,
> +				   adjusted_mode->crtc_htotal,
> +				   dsc_slice_count,
>  				   num_joined_pipes))
>  		return -EINVAL;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 78fa8eaba4ac..beef480b7672 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -230,6 +230,8 @@ bool intel_dp_can_join(struct intel_display *display,
>  		       int num_joined_pipes);
>  bool intel_dp_dotclk_valid(struct intel_display *display,
>  			   int target_clock,
> +			   int htotal,
> +			   int dsc_slice_count,
>  			   int num_joined_pipes);
>  
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f433a01dcfcb..bdf2f09fa03e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -702,6 +702,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	pipe_config->has_pch_encoder = false;
>  
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int dsc_slice_count = 0;
>  
>  		ret = -EINVAL;
>  
> @@ -731,8 +732,12 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  		if (ret)
>  			continue;
>  
> +		dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, pipe_config);
> +
>  		if (intel_dp_dotclk_valid(display,
>  					  adjusted_mode->clock,
> +					  adjusted_mode->htotal,
> +					  dsc_slice_count,
>  					  num_joined_pipes)) {
>  			ret = 0;
>  			break;
> @@ -1531,6 +1536,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	}
>  
>  	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +		int dsc_slice_count = 0;
>  
>  		*status = MODE_CLOCK_HIGH;
>  
> @@ -1556,6 +1562,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  			 */
>  			int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>  
> +			dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> +								       mode->clock,
> +								       mode->hdisplay,
> +								       num_joined_pipes);
> +
>  			if (!drm_dp_is_uhbr_rate(max_link_clock))
>  				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>  
> @@ -1580,6 +1591,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  

The if (!dsc) dsc_slice_count = 0; part you added for SST is missing
from here.

>  		if (intel_dp_dotclk_valid(display,
>  					  mode->clock,
> +					  mode->htotal,
> +					  dsc_slice_count,
>  					  num_joined_pipes)) {
>  			*status = MODE_OK;
>  			break;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 642a89270d8e..7e53201b3cb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1104,7 +1104,6 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>  	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
>  }
>  
> -static
>  int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
>  					      int pixel_rate, int htotal,
>  					      int dsc_horizontal_slices)
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index aeb17670307b..f4d5b37293cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -41,5 +41,8 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>  			   const struct intel_crtc_state *crtc_state);
>  int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
>  unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state);
> +int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
> +					      int pixel_rate, int htotal,
> +					      int dsc_horizontal_slices);
>  
>  #endif /* __INTEL_VDSC_H__ */
> -- 
> 2.45.2
> 

Re: [PATCH 14/16] drm/i915/dp: Add helpers for joiner candidate loops

[Imre Deak]

On Wed, Jan 28, 2026 at 07:36:34PM +0530, Ankit Nautiyal wrote:
> Introduce for_each_joiner_candidate(), intel_dp_pick_joiner_candidate() and
> intel_dp_joiner_candidate_valid() to remove duplicated joiner enumeration
> and validity checks across DP SST and MST paths.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 37 ++++++++-------------
>  drivers/gpu/drm/i915/display/intel_dp.h     | 31 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 37 ++++++++-------------
>  3 files changed, 59 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c1ff92367808..9eba8f90bc90 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1529,23 +1529,19 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	 * Because of this dependency cycle, the only correct approach is to iterate
>  	 * over candidate pipe counts and evaluate each combination.
>  	 */
> -	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +	for_each_joiner_candidate(num_pipes) {
>  		int dsc_slice_count = 0;
>  
>  		status = MODE_CLOCK_HIGH;
>  
> -		if (num_pipes == 0) {
> -			if (!connector->force_joined_pipes)
> -				continue;
> -			num_joined_pipes = connector->force_joined_pipes;
> -		} else {
> -			num_joined_pipes = num_pipes;
> -		}
> -
> -		if (!intel_dp_can_join(display, num_joined_pipes))
> +		if (!intel_dp_pick_joiner_candidate(num_pipes,
> +						    connector->force_joined_pipes,
> +						    &num_joined_pipes))
>  			continue;
>  
> -		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +		if (!intel_dp_joiner_candidate_valid(display,
> +						     mode->hdisplay,
> +						     num_joined_pipes))
>  			continue;

By not allowing to fallback from a forced joined-pipe to a non-forced
one as mentioned earlier (and so you'd iterate num_pipes = 1 ..
I915_MAX_PIPES - 1) you could fold all the above into a
for_each_joiner_candidate(connector, mode, num_pipes) helper and with
that yes, the iterator would make sense simplifying things a lot.

>  
>  		status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
> @@ -2938,20 +2934,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
>  		return -EINVAL;
>  
> -	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> -		if (num_pipes == 0) {
> -			if (!connector->force_joined_pipes)
> -				continue;
> -			num_joined_pipes = connector->force_joined_pipes;
> -		} else {
> -			num_joined_pipes = num_pipes;
> -		}
> -
> -		if (!intel_dp_can_join(display, num_joined_pipes))
> +	for_each_joiner_candidate(num_pipes) {
> +		if (!intel_dp_pick_joiner_candidate(num_pipes,
> +						    connector->force_joined_pipes,
> +						    &num_joined_pipes))
>  			continue;
>  
> -		if (adjusted_mode->hdisplay >
> -		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +		if (!intel_dp_joiner_candidate_valid(display,
> +						     adjusted_mode->hdisplay,
> +						     num_joined_pipes))
>  			continue;
>  
>  		/*
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index beef480b7672..111a5d4b3992 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -234,4 +234,35 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>  			   int dsc_slice_count,
>  			   int num_joined_pipes);
>  
> +#define for_each_joiner_candidate(__num_pipes) \
> +	for ((__num_pipes) = 0; (__num_pipes) < (I915_MAX_PIPES); (__num_pipes)++)
> +
> +static inline bool intel_dp_pick_joiner_candidate(int num_pipes,
> +						  int force_joined_pipes,
> +						  int *num_joined_pipes)
> +{
> +	if (num_pipes == 0) {
> +		if (!force_joined_pipes)
> +			return false;
> +		*num_joined_pipes = force_joined_pipes;
> +	} else {
> +		*num_joined_pipes = num_pipes;
> +	}
> +
> +	return true;
> +}
> +
> +static inline bool intel_dp_joiner_candidate_valid(struct intel_display *display,
> +						   int hdisplay,
> +						   int num_joined_pipes)
> +{
> +	if (!intel_dp_can_join(display, num_joined_pipes))
> +		return false;
> +
> +	if (hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +		return false;
> +
> +	return true;
> +}
> +
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index bdf2f09fa03e..005efcb5d2bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -701,24 +701,19 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	pipe_config->has_pch_encoder = false;
>  
> -	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +	for_each_joiner_candidate(num_pipes) {
>  		int dsc_slice_count = 0;
>  
>  		ret = -EINVAL;
>  
> -		if (num_pipes == 0) {
> -			if (!connector->force_joined_pipes)
> -				continue;
> -			num_joined_pipes = connector->force_joined_pipes;
> -		} else {
> -			num_joined_pipes = num_pipes;
> -		}
> -
> -		if (!intel_dp_can_join(display, num_joined_pipes))
> +		if (!intel_dp_pick_joiner_candidate(num_pipes,
> +						    connector->force_joined_pipes,
> +						    &num_joined_pipes))
>  			continue;
>  
> -		if (adjusted_mode->hdisplay >
> -		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +		if (!intel_dp_joiner_candidate_valid(display,
> +						     adjusted_mode->hdisplay,
> +						     num_joined_pipes))
>  			continue;
>  
>  		if (num_joined_pipes > 1)
> @@ -1535,23 +1530,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  		return 0;
>  	}
>  
> -	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> +	for_each_joiner_candidate(num_pipes) {
>  		int dsc_slice_count = 0;
>  
>  		*status = MODE_CLOCK_HIGH;
>  
> -		if (num_pipes == 0) {
> -			if (!connector->force_joined_pipes)
> -				continue;
> -			num_joined_pipes = connector->force_joined_pipes;
> -		} else {
> -			num_joined_pipes = num_pipes;
> -		}
> -
> -		if (!intel_dp_can_join(display, num_joined_pipes))
> +		if (!intel_dp_pick_joiner_candidate(num_pipes,
> +						    connector->force_joined_pipes,
> +						    &num_joined_pipes))
>  			continue;
>  
> -		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +		if (!intel_dp_joiner_candidate_valid(display,
> +						     mode->hdisplay,
> +						     num_joined_pipes))
>  			continue;
>  
>  		if (intel_dp_has_dsc(connector) &&
> -- 
> 2.45.2
> 

Re: [PATCH 11/16] drm/i915/dp: Introduce helper to check pixel rate against dotclock limits

[kernel test robot]

Hi Ankit,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-i915/for-linux-next drm-i915/for-linux-next-fixes linus/master v6.19-rc7 next-20260128]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-i915-dp-Early-reject-bad-hdisplay-in-intel_dp_mode_valid/20260128-234512
base:   https://gitlab.freedesktop.org/drm/tip.git drm-tip
patch link:    https://lore.kernel.org/r/20260128140636.3527799-12-ankit.k.nautiyal%40intel.com
patch subject: [PATCH 11/16] drm/i915/dp: Introduce helper to check pixel rate against dotclock limits
config: i386-randconfig-004-20260129 (https://download.01.org/0day-ci/archive/20260129/202601291157.RJA0VVmb-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260129/202601291157.RJA0VVmb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601291157.RJA0VVmb-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_dp.c:2828:6: warning: variable 'max_dotclk' set but not used [-Wunused-but-set-variable]
    2828 |         int max_dotclk = display->cdclk.max_dotclk_freq;
         |             ^
   1 warning generated.


vim +/max_dotclk +2828 drivers/gpu/drm/i915/display/intel_dp.c

aa099402f98b1e drivers/gpu/drm/i915/display/intel_dp.c Ville Syrjälä         2024-04-05  2814  
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2815  static int
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2816  intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2817  				       struct intel_crtc_state *pipe_config,
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2818  				       struct drm_connector_state *conn_state,
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2819  				       bool respect_downstream_limits)
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2820  {
8146b9235fc2b3 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2024-12-13  2821  	struct intel_display *display = to_intel_display(encoder);
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2822  	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
e43b4f7980f860 drivers/gpu/drm/i915/display/intel_dp.c Ville Syrjälä         2024-04-05  2823  	struct intel_connector *connector =
36f579ffc69214 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-10-24  2824  		to_intel_connector(conn_state->connector);
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2825  	const struct drm_display_mode *adjusted_mode =
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2826  		&pipe_config->hw.adjusted_mode;
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2827  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28 @2828  	int max_dotclk = display->cdclk.max_dotclk_freq;
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2829  	struct link_config_limits limits;
aa099402f98b1e drivers/gpu/drm/i915/display/intel_dp.c Ville Syrjälä         2024-04-05  2830  	bool dsc_needed, joiner_needs_dsc;
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2831  	int ret = 0;
72b2d2a6f178b9 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2832  
5d1bbfba0f39cf drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2024-12-13  2833  	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
1dedcdd0336c35 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2022-03-30  2834  
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2835  	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
ba49a4643cf53c drivers/gpu/drm/i915/display/intel_dp.c Chaitanya Kumar Borah 2025-07-30  2836  		     !intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2837  						     respect_downstream_limits,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2838  						     false,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2839  						     &limits);
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2840  
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2841  	if (!dsc_needed) {
3acd115d08f706 drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-04-26  2842  		/*
acca7762eb71bc drivers/gpu/drm/i915/display/intel_dp.c Kai-Heng Feng         2021-04-21  2843  		 * Optimize for slow and wide for everything, because there are some
acca7762eb71bc drivers/gpu/drm/i915/display/intel_dp.c Kai-Heng Feng         2021-04-21  2844  		 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
3acd115d08f706 drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-04-26  2845  		 */
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2846  		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2847  							conn_state, &limits);
ef0a0757bbeac9 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-03  2848  		if (!ret && intel_dp_is_uhbr(pipe_config))
ef0a0757bbeac9 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-03  2849  			ret = intel_dp_mtp_tu_compute_config(intel_dp,
ef0a0757bbeac9 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-03  2850  							     pipe_config,
bb322c6fa16f97 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-29  2851  							     conn_state,
67782bf6e8a628 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-31  2852  							     fxp_q4_from_int(pipe_config->pipe_bpp),
67782bf6e8a628 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-31  2853  							     fxp_q4_from_int(pipe_config->pipe_bpp),
ef0a0757bbeac9 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-03  2854  							     0, false);
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2855  		if (ret)
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2856  			dsc_needed = true;
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2857  	}
a4a157777c807d drivers/gpu/drm/i915/intel_dp.c         Manasi Navare         2018-11-28  2858  
939bc3e4d996ba drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2025-01-03  2859  	if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {
939bc3e4d996ba drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2025-01-03  2860  		drm_dbg_kms(display->drm, "DSC required but not available\n");
939bc3e4d996ba drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2025-01-03  2861  		return -EINVAL;
939bc3e4d996ba drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2025-01-03  2862  	}
939bc3e4d996ba drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2025-01-03  2863  
7d0f2f68b661e5 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2864  	if (dsc_needed) {
8146b9235fc2b3 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2024-12-13  2865  		drm_dbg_kms(display->drm,
8146b9235fc2b3 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2024-12-13  2866  			    "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1dedcdd0336c35 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2022-03-30  2867  			    str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1dedcdd0336c35 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2022-03-30  2868  			    str_yes_no(intel_dp->force_dsc_en));
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2869  
ba49a4643cf53c drivers/gpu/drm/i915/display/intel_dp.c Chaitanya Kumar Borah 2025-07-30  2870  		if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2871  						    respect_downstream_limits,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2872  						    true,
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2873  						    &limits))
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2874  			return -EINVAL;
78015e27b7d75e drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2023-09-21  2875  
204474a6b859ff drivers/gpu/drm/i915/intel_dp.c         Lyude Paul            2019-01-15  2876  		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2056f0ad806272 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2025-01-31  2877  						  conn_state, &limits, 64);
204474a6b859ff drivers/gpu/drm/i915/intel_dp.c         Lyude Paul            2019-01-15  2878  		if (ret < 0)
204474a6b859ff drivers/gpu/drm/i915/intel_dp.c         Lyude Paul            2019-01-15  2879  			return ret;
7769db5883841b drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-09-05  2880  	}
3600836585e3fd drivers/gpu/drm/i915/intel_dp.c         Simona Vetter         2013-03-27  2881  
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2882  	max_dotclk *= num_joined_pipes;
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2883  
d98b5ca9b08780 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2884  	if (!intel_dp_dotclk_valid(display,
d98b5ca9b08780 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2885  				   adjusted_mode->crtc_clock,
d98b5ca9b08780 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2886  				   num_joined_pipes))
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2887  		return -EINVAL;
0d71b594bb8132 drivers/gpu/drm/i915/display/intel_dp.c Ankit Nautiyal        2026-01-28  2888  
8146b9235fc2b3 drivers/gpu/drm/i915/display/intel_dp.c Jani Nikula           2024-12-13  2889  	drm_dbg_kms(display->drm,
2796b7ceec95bd drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2024-08-05  2890  		    "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
a4a157777c807d drivers/gpu/drm/i915/intel_dp.c         Manasi Navare         2018-11-28  2891  		    pipe_config->lane_count, pipe_config->port_clock,
a4a157777c807d drivers/gpu/drm/i915/intel_dp.c         Manasi Navare         2018-11-28  2892  		    pipe_config->pipe_bpp,
2796b7ceec95bd drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2024-08-05  2893  		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
e35cce9371fe1d drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2024-02-20  2894  		    intel_dp_config_required_rate(pipe_config),
a4ea61b7482f56 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2024-02-20  2895  		    intel_dp_max_link_data_rate(intel_dp,
a4ea61b7482f56 drivers/gpu/drm/i915/display/intel_dp.c Imre Deak             2024-02-20  2896  						pipe_config->port_clock,
a4a157777c807d drivers/gpu/drm/i915/intel_dp.c         Manasi Navare         2018-11-28  2897  						pipe_config->lane_count));
3acd115d08f706 drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-04-26  2898  
204474a6b859ff drivers/gpu/drm/i915/intel_dp.c         Lyude Paul            2019-01-15  2899  	return 0;
981a63eb2725ec drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-04-26  2900  }
981a63eb2725ec drivers/gpu/drm/i915/intel_dp.c         Jani Nikula           2018-04-26  2901  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Nautiyal, Ankit K]

On 1/28/2026 10:16 PM, Imre Deak wrote:
> On Wed, Jan 28, 2026 at 07:36:24PM +0530, Ankit Nautiyal wrote:
>> Currently in intel_dp_mode_valid(), we compute the number of joined pipes
>> required before deciding whether DSC is needed. This ordering prevents us
>> from accounting for DSC-related overhead when determining pipe
>> requirements.
>>
>> It is not possible to first decide whether DSC is needed and then compute
>> the required number of joined pipes, because the two depend on each other:
>>
>>   - DSC need is a function of the pipe count (e.g., 4‑pipe always requires
>>     DSC; 2‑pipe may require it if uncompressed joiner is unavailable).
>>
>>   - Whether a given pipe‑join configuration is sufficient depends on
>>     effective bandwidth, which itself changes when DSC is used.
>>
>> As a result, the only correct approach is to iterate candidate pipe counts.
>>
>> So, refactor the logic to start with a single pipe and incrementally try
>> additional pipes only if needed. While DSC overhead is not yet computed
>> here, this restructuring prepares the code to support that in a follow-up
>> changes.
>>
>> Additionally, if a forced joiner configuration is present, we first check
>> whether it satisfies the bandwidth and timing constraints. If it does not,
>> we fall back to evaluating configurations with 1, 2, or 4 pipes joined
>> and prune or keep the mode accordingly.
>>
>> v2:
>>   - Iterate over number of pipes to be joined instead of joiner
>>     candidates. (Jani)
>>   - Document the rationale of iterating over number of joined pipes.
>>     (Imre)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 158 +++++++++++++++---------
>>   1 file changed, 103 insertions(+), 55 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4c3a1b6d0015..599965a6e1a6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
>>   	return true;
>>   }
>>   
>> +static
>> +bool intel_dp_can_join(struct intel_display *display,
>> +		       int num_joined_pipes)
>> +{
>> +	switch (num_joined_pipes) {
>> +	case 1:
>> +		return true;
>> +	case 2:
>> +		return HAS_BIGJOINER(display) ||
>> +		       HAS_UNCOMPRESSED_JOINER(display);
>> +	case 4:
>> +		return HAS_ULTRAJOINER(display);
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>>   static enum drm_mode_status
>>   intel_dp_mode_valid(struct drm_connector *_connector,
>>   		    const struct drm_display_mode *mode)
>> @@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>>   	const struct drm_display_mode *fixed_mode;
>>   	int target_clock = mode->clock;
>>   	int max_rate, mode_rate, max_lanes, max_link_clock;
>> -	int max_dotclk = display->cdclk.max_dotclk_freq;
>>   	u16 dsc_max_compressed_bpp = 0;
>>   	u8 dsc_slice_count = 0;
>>   	enum drm_mode_status status;
>>   	bool dsc = false;
>>   	int num_joined_pipes;
>>   	int link_bpp_x16;
>> +	int num_pipes;
>>   
>>   	status = intel_cpu_transcoder_mode_valid(display, mode);
>>   	if (status != MODE_OK)
>> @@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>>   					   target_clock, mode->hdisplay,
>>   					   link_bpp_x16, 0);
>>   
>> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
>> -						     mode->hdisplay, target_clock);
>> -	max_dotclk *= num_joined_pipes;
>> -
>> -	if (target_clock > max_dotclk)
>> -		return MODE_CLOCK_HIGH;
>> -
>> -	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
>> -	if (status != MODE_OK)
>> -		return status;
>> -
>> -	if (intel_dp_has_dsc(connector)) {
>> -		int pipe_bpp;
>> -
>> -		/*
>> -		 * TBD pass the connector BPC,
>> -		 * for now U8_MAX so that max BPC on that platform would be picked
>> -		 */
>> -		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>> -
>> -		/*
>> -		 * Output bpp is stored in 6.4 format so right shift by 4 to get the
>> -		 * integer value since we support only integer values of bpp.
>> -		 */
>> -		if (intel_dp_is_edp(intel_dp)) {
>> -			dsc_max_compressed_bpp =
>> -				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>> -
>> -			dsc_slice_count =
>> -				intel_dp_dsc_get_slice_count(connector,
>> -							     target_clock,
>> -							     mode->hdisplay,
>> -							     num_joined_pipes);
>> -
>> -			dsc = dsc_max_compressed_bpp && dsc_slice_count;
>> -		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>> -			unsigned long bw_overhead_flags = 0;
>> -
>> -			if (!drm_dp_is_uhbr_rate(max_link_clock))
>> -				bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>> -
>> -			dsc = intel_dp_mode_valid_with_dsc(connector,
>> -							   max_link_clock, max_lanes,
>> -							   target_clock, mode->hdisplay,
>> -							   num_joined_pipes,
>> -							   output_format, pipe_bpp,
>> -							   bw_overhead_flags);
>> +	/*
>> +	 * We cannot determine the required pipe‑join count before knowing whether
>> +	 * DSC is needed, nor can we determine DSC need without knowing the pipe
>> +	 * count.
>> +	 * Because of this dependency cycle, the only correct approach is to iterate
>> +	 * over candidate pipe counts and evaluate each combination.
>> +	 */
>> +	for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
>> +		int max_dotclk = display->cdclk.max_dotclk_freq;
>> +
>> +		status = MODE_CLOCK_HIGH;
>> +
>> +		if (num_pipes == 0) {
>> +			if (!connector->force_joined_pipes)
>> +				continue;
>> +			num_joined_pipes = connector->force_joined_pipes;
>> +		} else {
>> +			num_joined_pipes = num_pipes;
>> +		}
> The current way is to try connector->force_joined_pipes and fail the
> commit if that doesn't work. Here you'd change that to fall back trying
> non-forced pipe-joined configs in that case. If that's needed (not sure
> if that's a good idea, since then the user wouldn't know which case
> succeeded or failed), it should be a separate change. Here it could be
> simply an if (forced_joined_pipes && num_pipes != forced_joined_pipes)
> continue and then use num_pipes instead of num_joined_pipes later in the
> loop.


Hmm Yeah the initial thought process was to try force joiner thing 
first, if succeed well and good, if not we do our usual thing.

But I see your point. I think we can just fail the commit if forced 
joiner doesn't work.

This will also help simplify the loop and will allow to have an iterator 
macro as you have mentioned in the later patch.


>
>> +
>> +		if (!intel_dp_can_join(display, num_joined_pipes))
>> +			continue;
>> +
>> +		if (mode->hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
>> +			continue;
>> +
>> +		status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
>> +		if (status != MODE_OK)
>> +			continue;
>> +
>> +		if (intel_dp_has_dsc(connector)) {
>> +			int pipe_bpp;
>> +
>> +			/*
>> +			 * TBD pass the connector BPC,
>> +			 * for now U8_MAX so that max BPC on that platform would be picked
>> +			 */
>> +			pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>> +
>> +			/*
>> +			 * Output bpp is stored in 6.4 format so right shift by 4 to get the
>> +			 * integer value since we support only integer values of bpp.
>> +			 */
>> +			if (intel_dp_is_edp(intel_dp)) {
>> +				dsc_max_compressed_bpp =
>> +					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>> +
>> +				dsc_slice_count =
>> +					intel_dp_dsc_get_slice_count(connector,
>> +								     target_clock,
>> +								     mode->hdisplay,
>> +								     num_joined_pipes);
>> +
>> +				dsc = dsc_max_compressed_bpp && dsc_slice_count;
>> +			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>> +				unsigned long bw_overhead_flags = 0;
>> +
>> +				if (!drm_dp_is_uhbr_rate(max_link_clock))
>> +					bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>> +
>> +				dsc = intel_dp_mode_valid_with_dsc(connector,
>> +								   max_link_clock, max_lanes,
>> +								   target_clock, mode->hdisplay,
>> +								   num_joined_pipes,
>> +								   output_format, pipe_bpp,
>> +								   bw_overhead_flags);
>> +			}
>> +		}
>> +
>> +		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
>> +			continue;
>> +
>> +		if (mode_rate > max_rate && !dsc)
>> +			continue;
>> +
>> +		status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
>> +		if (status != MODE_OK)
>> +			continue;
>> +
>> +		max_dotclk *= num_joined_pipes;
>> +
>> +		if (target_clock <= max_dotclk) {
>> +			status = MODE_OK;
> status stays MODE_OK if target_clock > max_dotclk.

Oh yes.. will fix this.


>
>> +			break;
>>   		}
>>   	}
>>   
>> -	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
>> -		return MODE_CLOCK_HIGH;
>> -
>> -	status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
>>   	if (status != MODE_OK)
>>   		return status;
>>   
>> -	if (mode_rate > max_rate && !dsc)
>> -		return MODE_CLOCK_HIGH;
>> -
>>   	return intel_dp_mode_valid_downstream(connector, mode, target_clock);
>> +
> Extra w/s.

Will drop this extra line.


Thanks & Regards,

Ankit

>>   }
>>   
>>   bool intel_dp_source_supports_tps3(struct intel_display *display)
>> -- 
>> 2.45.2
>>

Re: [PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Nautiyal, Ankit K]

On 1/29/2026 10:51 AM, Nautiyal, Ankit K wrote:
>
> On 1/28/2026 10:16 PM, Imre Deak wrote:
>> On Wed, Jan 28, 2026 at 07:36:24PM +0530, Ankit Nautiyal wrote:
>>> Currently in intel_dp_mode_valid(), we compute the number of joined 
>>> pipes
>>> required before deciding whether DSC is needed. This ordering 
>>> prevents us
>>> from accounting for DSC-related overhead when determining pipe
>>> requirements.
>>>
>>> It is not possible to first decide whether DSC is needed and then 
>>> compute
>>> the required number of joined pipes, because the two depend on each 
>>> other:
>>>
>>>   - DSC need is a function of the pipe count (e.g., 4‑pipe always 
>>> requires
>>>     DSC; 2‑pipe may require it if uncompressed joiner is unavailable).
>>>
>>>   - Whether a given pipe‑join configuration is sufficient depends on
>>>     effective bandwidth, which itself changes when DSC is used.
>>>
>>> As a result, the only correct approach is to iterate candidate pipe 
>>> counts.
>>>
>>> So, refactor the logic to start with a single pipe and incrementally 
>>> try
>>> additional pipes only if needed. While DSC overhead is not yet computed
>>> here, this restructuring prepares the code to support that in a 
>>> follow-up
>>> changes.
>>>
>>> Additionally, if a forced joiner configuration is present, we first 
>>> check
>>> whether it satisfies the bandwidth and timing constraints. If it 
>>> does not,
>>> we fall back to evaluating configurations with 1, 2, or 4 pipes joined
>>> and prune or keep the mode accordingly.
>>>
>>> v2:
>>>   - Iterate over number of pipes to be joined instead of joiner
>>>     candidates. (Jani)
>>>   - Document the rationale of iterating over number of joined pipes.
>>>     (Imre)
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_dp.c | 158 
>>> +++++++++++++++---------
>>>   1 file changed, 103 insertions(+), 55 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 4c3a1b6d0015..599965a6e1a6 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct 
>>> intel_connector *connector)
>>>       return true;
>>>   }
>>>   +static
>>> +bool intel_dp_can_join(struct intel_display *display,
>>> +               int num_joined_pipes)
>>> +{
>>> +    switch (num_joined_pipes) {
>>> +    case 1:
>>> +        return true;
>>> +    case 2:
>>> +        return HAS_BIGJOINER(display) ||
>>> +               HAS_UNCOMPRESSED_JOINER(display);
>>> +    case 4:
>>> +        return HAS_ULTRAJOINER(display);
>>> +    default:
>>> +        return false;
>>> +    }
>>> +}
>>> +
>>>   static enum drm_mode_status
>>>   intel_dp_mode_valid(struct drm_connector *_connector,
>>>               const struct drm_display_mode *mode)
>>> @@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector 
>>> *_connector,
>>>       const struct drm_display_mode *fixed_mode;
>>>       int target_clock = mode->clock;
>>>       int max_rate, mode_rate, max_lanes, max_link_clock;
>>> -    int max_dotclk = display->cdclk.max_dotclk_freq;
>>>       u16 dsc_max_compressed_bpp = 0;
>>>       u8 dsc_slice_count = 0;
>>>       enum drm_mode_status status;
>>>       bool dsc = false;
>>>       int num_joined_pipes;
>>>       int link_bpp_x16;
>>> +    int num_pipes;
>>>         status = intel_cpu_transcoder_mode_valid(display, mode);
>>>       if (status != MODE_OK)
>>> @@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector 
>>> *_connector,
>>>                          target_clock, mode->hdisplay,
>>>                          link_bpp_x16, 0);
>>>   -    num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, 
>>> connector,
>>> -                             mode->hdisplay, target_clock);
>>> -    max_dotclk *= num_joined_pipes;
>>> -
>>> -    if (target_clock > max_dotclk)
>>> -        return MODE_CLOCK_HIGH;
>>> -
>>> -    status = intel_pfit_mode_valid(display, mode, output_format, 
>>> num_joined_pipes);
>>> -    if (status != MODE_OK)
>>> -        return status;
>>> -
>>> -    if (intel_dp_has_dsc(connector)) {
>>> -        int pipe_bpp;
>>> -
>>> -        /*
>>> -         * TBD pass the connector BPC,
>>> -         * for now U8_MAX so that max BPC on that platform would be 
>>> picked
>>> -         */
>>> -        pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>>> -
>>> -        /*
>>> -         * Output bpp is stored in 6.4 format so right shift by 4 
>>> to get the
>>> -         * integer value since we support only integer values of bpp.
>>> -         */
>>> -        if (intel_dp_is_edp(intel_dp)) {
>>> -            dsc_max_compressed_bpp =
>>> - drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>>> -
>>> -            dsc_slice_count =
>>> -                intel_dp_dsc_get_slice_count(connector,
>>> -                                 target_clock,
>>> -                                 mode->hdisplay,
>>> -                                 num_joined_pipes);
>>> -
>>> -            dsc = dsc_max_compressed_bpp && dsc_slice_count;
>>> -        } else if 
>>> (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>>> -            unsigned long bw_overhead_flags = 0;
>>> -
>>> -            if (!drm_dp_is_uhbr_rate(max_link_clock))
>>> -                bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>>> -
>>> -            dsc = intel_dp_mode_valid_with_dsc(connector,
>>> -                               max_link_clock, max_lanes,
>>> -                               target_clock, mode->hdisplay,
>>> -                               num_joined_pipes,
>>> -                               output_format, pipe_bpp,
>>> -                               bw_overhead_flags);
>>> +    /*
>>> +     * We cannot determine the required pipe‑join count before 
>>> knowing whether
>>> +     * DSC is needed, nor can we determine DSC need without knowing 
>>> the pipe
>>> +     * count.
>>> +     * Because of this dependency cycle, the only correct approach 
>>> is to iterate
>>> +     * over candidate pipe counts and evaluate each combination.
>>> +     */
>>> +    for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
>>> +        int max_dotclk = display->cdclk.max_dotclk_freq;
>>> +
>>> +        status = MODE_CLOCK_HIGH;
>>> +
>>> +        if (num_pipes == 0) {
>>> +            if (!connector->force_joined_pipes)
>>> +                continue;
>>> +            num_joined_pipes = connector->force_joined_pipes;
>>> +        } else {
>>> +            num_joined_pipes = num_pipes;
>>> +        }
>> The current way is to try connector->force_joined_pipes and fail the
>> commit if that doesn't work. Here you'd change that to fall back trying
>> non-forced pipe-joined configs in that case. If that's needed (not sure
>> if that's a good idea, since then the user wouldn't know which case
>> succeeded or failed), it should be a separate change. Here it could be
>> simply an if (forced_joined_pipes && num_pipes != forced_joined_pipes)
>> continue and then use num_pipes instead of num_joined_pipes later in the
>> loop.
>
>
> Hmm Yeah the initial thought process was to try force joiner thing 
> first, if succeed well and good, if not we do our usual thing.
>
> But I see your point. I think we can just fail the commit if forced 
> joiner doesn't work.
>
> This will also help simplify the loop and will allow to have an 
> iterator macro as you have mentioned in the later patch.


For mode_valid phase can there be a corner case where force joiner is 
set to some high value with which all modes somehow fail?

Can hdisplay/htotal or clock  for a mode go below some acceptable value 
if joiner is used?

Regards,

Ankit

>
>
>>
>>> +
>>> +        if (!intel_dp_can_join(display, num_joined_pipes))
>>> +            continue;
>>> +
>>> +        if (mode->hdisplay > num_joined_pipes * 
>>> intel_dp_max_hdisplay_per_pipe(display))
>>> +            continue;
>>> +
>>> +        status = intel_pfit_mode_valid(display, mode, 
>>> output_format, num_joined_pipes);
>>> +        if (status != MODE_OK)
>>> +            continue;
>>> +
>>> +        if (intel_dp_has_dsc(connector)) {
>>> +            int pipe_bpp;
>>> +
>>> +            /*
>>> +             * TBD pass the connector BPC,
>>> +             * for now U8_MAX so that max BPC on that platform 
>>> would be picked
>>> +             */
>>> +            pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, 
>>> U8_MAX);
>>> +
>>> +            /*
>>> +             * Output bpp is stored in 6.4 format so right shift by 
>>> 4 to get the
>>> +             * integer value since we support only integer values 
>>> of bpp.
>>> +             */
>>> +            if (intel_dp_is_edp(intel_dp)) {
>>> +                dsc_max_compressed_bpp =
>>> + drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>>> +
>>> +                dsc_slice_count =
>>> +                    intel_dp_dsc_get_slice_count(connector,
>>> +                                     target_clock,
>>> +                                     mode->hdisplay,
>>> +                                     num_joined_pipes);
>>> +
>>> +                dsc = dsc_max_compressed_bpp && dsc_slice_count;
>>> +            } else if 
>>> (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>>> +                unsigned long bw_overhead_flags = 0;
>>> +
>>> +                if (!drm_dp_is_uhbr_rate(max_link_clock))
>>> +                    bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>>> +
>>> +                dsc = intel_dp_mode_valid_with_dsc(connector,
>>> +                                   max_link_clock, max_lanes,
>>> +                                   target_clock, mode->hdisplay,
>>> +                                   num_joined_pipes,
>>> +                                   output_format, pipe_bpp,
>>> +                                   bw_overhead_flags);
>>> +            }
>>> +        }
>>> +
>>> +        if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && 
>>> !dsc)
>>> +            continue;
>>> +
>>> +        if (mode_rate > max_rate && !dsc)
>>> +            continue;
>>> +
>>> +        status = intel_mode_valid_max_plane_size(display, mode, 
>>> num_joined_pipes);
>>> +        if (status != MODE_OK)
>>> +            continue;
>>> +
>>> +        max_dotclk *= num_joined_pipes;
>>> +
>>> +        if (target_clock <= max_dotclk) {
>>> +            status = MODE_OK;
>> status stays MODE_OK if target_clock > max_dotclk.
>
> Oh yes.. will fix this.
>
>
>>
>>> +            break;
>>>           }
>>>       }
>>>   -    if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && 
>>> !dsc)
>>> -        return MODE_CLOCK_HIGH;
>>> -
>>> -    status = intel_mode_valid_max_plane_size(display, mode, 
>>> num_joined_pipes);
>>>       if (status != MODE_OK)
>>>           return status;
>>>   -    if (mode_rate > max_rate && !dsc)
>>> -        return MODE_CLOCK_HIGH;
>>> -
>>>       return intel_dp_mode_valid_downstream(connector, mode, 
>>> target_clock);
>>> +
>> Extra w/s.
>
> Will drop this extra line.
>
>
> Thanks & Regards,
>
> Ankit
>
>>>   }
>>>     bool intel_dp_source_supports_tps3(struct intel_display *display)
>>> -- 
>>> 2.45.2
>>>

Re: [PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Imre Deak]

On Thu, Jan 29, 2026 at 11:18:28AM +0530, Nautiyal, Ankit K wrote:
> 
> On 1/29/2026 10:51 AM, Nautiyal, Ankit K wrote:
> > 
> > On 1/28/2026 10:16 PM, Imre Deak wrote:
> > > On Wed, Jan 28, 2026 at 07:36:24PM +0530, Ankit Nautiyal wrote:
> > > > Currently in intel_dp_mode_valid(), we compute the number of
> > > > joined pipes
> > > > required before deciding whether DSC is needed. This ordering
> > > > prevents us
> > > > from accounting for DSC-related overhead when determining pipe
> > > > requirements.
> > > > 
> > > > It is not possible to first decide whether DSC is needed and
> > > > then compute
> > > > the required number of joined pipes, because the two depend on
> > > > each other:
> > > > 
> > > >   - DSC need is a function of the pipe count (e.g., 4‑pipe
> > > > always requires
> > > >     DSC; 2‑pipe may require it if uncompressed joiner is unavailable).
> > > > 
> > > >   - Whether a given pipe‑join configuration is sufficient depends on
> > > >     effective bandwidth, which itself changes when DSC is used.
> > > > 
> > > > As a result, the only correct approach is to iterate candidate
> > > > pipe counts.
> > > > 
> > > > So, refactor the logic to start with a single pipe and
> > > > incrementally try
> > > > additional pipes only if needed. While DSC overhead is not yet computed
> > > > here, this restructuring prepares the code to support that in a
> > > > follow-up
> > > > changes.
> > > > 
> > > > Additionally, if a forced joiner configuration is present, we
> > > > first check
> > > > whether it satisfies the bandwidth and timing constraints. If it
> > > > does not,
> > > > we fall back to evaluating configurations with 1, 2, or 4 pipes joined
> > > > and prune or keep the mode accordingly.
> > > > 
> > > > v2:
> > > >   - Iterate over number of pipes to be joined instead of joiner
> > > >     candidates. (Jani)
> > > >   - Document the rationale of iterating over number of joined pipes.
> > > >     (Imre)
> > > > 
> > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/i915/display/intel_dp.c | 158
> > > > +++++++++++++++---------
> > > >   1 file changed, 103 insertions(+), 55 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 4c3a1b6d0015..599965a6e1a6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct
> > > > intel_connector *connector)
> > > >       return true;
> > > >   }
> > > >   +static
> > > > +bool intel_dp_can_join(struct intel_display *display,
> > > > +               int num_joined_pipes)
> > > > +{
> > > > +    switch (num_joined_pipes) {
> > > > +    case 1:
> > > > +        return true;
> > > > +    case 2:
> > > > +        return HAS_BIGJOINER(display) ||
> > > > +               HAS_UNCOMPRESSED_JOINER(display);
> > > > +    case 4:
> > > > +        return HAS_ULTRAJOINER(display);
> > > > +    default:
> > > > +        return false;
> > > > +    }
> > > > +}
> > > > +
> > > >   static enum drm_mode_status
> > > >   intel_dp_mode_valid(struct drm_connector *_connector,
> > > >               const struct drm_display_mode *mode)
> > > > @@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector
> > > > *_connector,
> > > >       const struct drm_display_mode *fixed_mode;
> > > >       int target_clock = mode->clock;
> > > >       int max_rate, mode_rate, max_lanes, max_link_clock;
> > > > -    int max_dotclk = display->cdclk.max_dotclk_freq;
> > > >       u16 dsc_max_compressed_bpp = 0;
> > > >       u8 dsc_slice_count = 0;
> > > >       enum drm_mode_status status;
> > > >       bool dsc = false;
> > > >       int num_joined_pipes;
> > > >       int link_bpp_x16;
> > > > +    int num_pipes;
> > > >         status = intel_cpu_transcoder_mode_valid(display, mode);
> > > >       if (status != MODE_OK)
> > > > @@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector
> > > > *_connector,
> > > >                          target_clock, mode->hdisplay,
> > > >                          link_bpp_x16, 0);
> > > >   -    num_joined_pipes = intel_dp_num_joined_pipes(intel_dp,
> > > > connector,
> > > > -                             mode->hdisplay, target_clock);
> > > > -    max_dotclk *= num_joined_pipes;
> > > > -
> > > > -    if (target_clock > max_dotclk)
> > > > -        return MODE_CLOCK_HIGH;
> > > > -
> > > > -    status = intel_pfit_mode_valid(display, mode,
> > > > output_format, num_joined_pipes);
> > > > -    if (status != MODE_OK)
> > > > -        return status;
> > > > -
> > > > -    if (intel_dp_has_dsc(connector)) {
> > > > -        int pipe_bpp;
> > > > -
> > > > -        /*
> > > > -         * TBD pass the connector BPC,
> > > > -         * for now U8_MAX so that max BPC on that platform
> > > > would be picked
> > > > -         */
> > > > -        pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
> > > > -
> > > > -        /*
> > > > -         * Output bpp is stored in 6.4 format so right shift by
> > > > 4 to get the
> > > > -         * integer value since we support only integer values of bpp.
> > > > -         */
> > > > -        if (intel_dp_is_edp(intel_dp)) {
> > > > -            dsc_max_compressed_bpp =
> > > > - drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
> > > > -
> > > > -            dsc_slice_count =
> > > > -                intel_dp_dsc_get_slice_count(connector,
> > > > -                                 target_clock,
> > > > -                                 mode->hdisplay,
> > > > -                                 num_joined_pipes);
> > > > -
> > > > -            dsc = dsc_max_compressed_bpp && dsc_slice_count;
> > > > -        } else if
> > > > (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> > > > -            unsigned long bw_overhead_flags = 0;
> > > > -
> > > > -            if (!drm_dp_is_uhbr_rate(max_link_clock))
> > > > -                bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> > > > -
> > > > -            dsc = intel_dp_mode_valid_with_dsc(connector,
> > > > -                               max_link_clock, max_lanes,
> > > > -                               target_clock, mode->hdisplay,
> > > > -                               num_joined_pipes,
> > > > -                               output_format, pipe_bpp,
> > > > -                               bw_overhead_flags);
> > > > +    /*
> > > > +     * We cannot determine the required pipe‑join count before
> > > > knowing whether
> > > > +     * DSC is needed, nor can we determine DSC need without
> > > > knowing the pipe
> > > > +     * count.
> > > > +     * Because of this dependency cycle, the only correct
> > > > approach is to iterate
> > > > +     * over candidate pipe counts and evaluate each combination.
> > > > +     */
> > > > +    for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
> > > > +        int max_dotclk = display->cdclk.max_dotclk_freq;
> > > > +
> > > > +        status = MODE_CLOCK_HIGH;
> > > > +
> > > > +        if (num_pipes == 0) {
> > > > +            if (!connector->force_joined_pipes)
> > > > +                continue;
> > > > +            num_joined_pipes = connector->force_joined_pipes;
> > > > +        } else {
> > > > +            num_joined_pipes = num_pipes;
> > > > +        }
> > > The current way is to try connector->force_joined_pipes and fail the
> > > commit if that doesn't work. Here you'd change that to fall back trying
> > > non-forced pipe-joined configs in that case. If that's needed (not sure
> > > if that's a good idea, since then the user wouldn't know which case
> > > succeeded or failed), it should be a separate change. Here it could be
> > > simply an if (forced_joined_pipes && num_pipes != forced_joined_pipes)
> > > continue and then use num_pipes instead of num_joined_pipes later in the
> > > loop.
> > 
> > Hmm Yeah the initial thought process was to try force joiner thing
> > first, if succeed well and good, if not we do our usual thing.
> > 
> > But I see your point. I think we can just fail the commit if forced
> > joiner doesn't work.
> > 
> > This will also help simplify the loop and will allow to have an iterator
> > macro as you have mentioned in the later patch.
> 
> For mode_valid phase can there be a corner case where force joiner is set to
> some high value with which all modes somehow fail?
> 
> Can hdisplay/htotal or clock  for a mode go below some acceptable value if
> joiner is used?

I.e. hdisplay/htotal/clock per-pipe becoming too low, right? I don't
recall that the driver would check for these anywhere. The mode timing
itself is checked and then (for instance) MODE_CLOCK_LOW is returned,
but that's not a per-pipe thing. One thing that can fail is the DSC
slice count, which can get too high for the sink.

In any case there's not much we can do about any such failure scenario,
just fail the commit?

> Regards,
> 
> Ankit
> 
> > 
> > 
> > > 
> > > > +
> > > > +        if (!intel_dp_can_join(display, num_joined_pipes))
> > > > +            continue;
> > > > +
> > > > +        if (mode->hdisplay > num_joined_pipes *
> > > > intel_dp_max_hdisplay_per_pipe(display))
> > > > +            continue;
> > > > +
> > > > +        status = intel_pfit_mode_valid(display, mode,
> > > > output_format, num_joined_pipes);
> > > > +        if (status != MODE_OK)
> > > > +            continue;
> > > > +
> > > > +        if (intel_dp_has_dsc(connector)) {
> > > > +            int pipe_bpp;
> > > > +
> > > > +            /*
> > > > +             * TBD pass the connector BPC,
> > > > +             * for now U8_MAX so that max BPC on that platform
> > > > would be picked
> > > > +             */
> > > > +            pipe_bpp = intel_dp_dsc_compute_max_bpp(connector,
> > > > U8_MAX);
> > > > +
> > > > +            /*
> > > > +             * Output bpp is stored in 6.4 format so right
> > > > shift by 4 to get the
> > > > +             * integer value since we support only integer
> > > > values of bpp.
> > > > +             */
> > > > +            if (intel_dp_is_edp(intel_dp)) {
> > > > +                dsc_max_compressed_bpp =
> > > > + drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
> > > > +
> > > > +                dsc_slice_count =
> > > > +                    intel_dp_dsc_get_slice_count(connector,
> > > > +                                     target_clock,
> > > > +                                     mode->hdisplay,
> > > > +                                     num_joined_pipes);
> > > > +
> > > > +                dsc = dsc_max_compressed_bpp && dsc_slice_count;
> > > > +            } else if
> > > > (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
> > > > +                unsigned long bw_overhead_flags = 0;
> > > > +
> > > > +                if (!drm_dp_is_uhbr_rate(max_link_clock))
> > > > +                    bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
> > > > +
> > > > +                dsc = intel_dp_mode_valid_with_dsc(connector,
> > > > +                                   max_link_clock, max_lanes,
> > > > +                                   target_clock, mode->hdisplay,
> > > > +                                   num_joined_pipes,
> > > > +                                   output_format, pipe_bpp,
> > > > +                                   bw_overhead_flags);
> > > > +            }
> > > > +        }
> > > > +
> > > > +        if (intel_dp_joiner_needs_dsc(display,
> > > > num_joined_pipes) && !dsc)
> > > > +            continue;
> > > > +
> > > > +        if (mode_rate > max_rate && !dsc)
> > > > +            continue;
> > > > +
> > > > +        status = intel_mode_valid_max_plane_size(display, mode,
> > > > num_joined_pipes);
> > > > +        if (status != MODE_OK)
> > > > +            continue;
> > > > +
> > > > +        max_dotclk *= num_joined_pipes;
> > > > +
> > > > +        if (target_clock <= max_dotclk) {
> > > > +            status = MODE_OK;
> > > status stays MODE_OK if target_clock > max_dotclk.
> > 
> > Oh yes.. will fix this.
> > 
> > 
> > > 
> > > > +            break;
> > > >           }
> > > >       }
> > > >   -    if (intel_dp_joiner_needs_dsc(display, num_joined_pipes)
> > > > && !dsc)
> > > > -        return MODE_CLOCK_HIGH;
> > > > -
> > > > -    status = intel_mode_valid_max_plane_size(display, mode,
> > > > num_joined_pipes);
> > > >       if (status != MODE_OK)
> > > >           return status;
> > > >   -    if (mode_rate > max_rate && !dsc)
> > > > -        return MODE_CLOCK_HIGH;
> > > > -
> > > >       return intel_dp_mode_valid_downstream(connector, mode,
> > > > target_clock);
> > > > +
> > > Extra w/s.
> > 
> > Will drop this extra line.
> > 
> > 
> > Thanks & Regards,
> > 
> > Ankit
> > 
> > > >   }
> > > >     bool intel_dp_source_supports_tps3(struct intel_display *display)
> > > > -- 
> > > > 2.45.2
> > > > 

Re: [PATCH 04/16] drm/i915/dp: Rework pipe joiner logic in mode_valid

[Nautiyal, Ankit K]

On 1/29/2026 2:54 PM, Imre Deak wrote:
> On Thu, Jan 29, 2026 at 11:18:28AM +0530, Nautiyal, Ankit K wrote:
>> On 1/29/2026 10:51 AM, Nautiyal, Ankit K wrote:
>>> On 1/28/2026 10:16 PM, Imre Deak wrote:
>>>> On Wed, Jan 28, 2026 at 07:36:24PM +0530, Ankit Nautiyal wrote:
>>>>> Currently in intel_dp_mode_valid(), we compute the number of
>>>>> joined pipes
>>>>> required before deciding whether DSC is needed. This ordering
>>>>> prevents us
>>>>> from accounting for DSC-related overhead when determining pipe
>>>>> requirements.
>>>>>
>>>>> It is not possible to first decide whether DSC is needed and
>>>>> then compute
>>>>> the required number of joined pipes, because the two depend on
>>>>> each other:
>>>>>
>>>>>    - DSC need is a function of the pipe count (e.g., 4‑pipe
>>>>> always requires
>>>>>      DSC; 2‑pipe may require it if uncompressed joiner is unavailable).
>>>>>
>>>>>    - Whether a given pipe‑join configuration is sufficient depends on
>>>>>      effective bandwidth, which itself changes when DSC is used.
>>>>>
>>>>> As a result, the only correct approach is to iterate candidate
>>>>> pipe counts.
>>>>>
>>>>> So, refactor the logic to start with a single pipe and
>>>>> incrementally try
>>>>> additional pipes only if needed. While DSC overhead is not yet computed
>>>>> here, this restructuring prepares the code to support that in a
>>>>> follow-up
>>>>> changes.
>>>>>
>>>>> Additionally, if a forced joiner configuration is present, we
>>>>> first check
>>>>> whether it satisfies the bandwidth and timing constraints. If it
>>>>> does not,
>>>>> we fall back to evaluating configurations with 1, 2, or 4 pipes joined
>>>>> and prune or keep the mode accordingly.
>>>>>
>>>>> v2:
>>>>>    - Iterate over number of pipes to be joined instead of joiner
>>>>>      candidates. (Jani)
>>>>>    - Document the rationale of iterating over number of joined pipes.
>>>>>      (Imre)
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/display/intel_dp.c | 158
>>>>> +++++++++++++++---------
>>>>>    1 file changed, 103 insertions(+), 55 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> index 4c3a1b6d0015..599965a6e1a6 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> @@ -1434,6 +1434,23 @@ bool intel_dp_has_dsc(const struct
>>>>> intel_connector *connector)
>>>>>        return true;
>>>>>    }
>>>>>    +static
>>>>> +bool intel_dp_can_join(struct intel_display *display,
>>>>> +               int num_joined_pipes)
>>>>> +{
>>>>> +    switch (num_joined_pipes) {
>>>>> +    case 1:
>>>>> +        return true;
>>>>> +    case 2:
>>>>> +        return HAS_BIGJOINER(display) ||
>>>>> +               HAS_UNCOMPRESSED_JOINER(display);
>>>>> +    case 4:
>>>>> +        return HAS_ULTRAJOINER(display);
>>>>> +    default:
>>>>> +        return false;
>>>>> +    }
>>>>> +}
>>>>> +
>>>>>    static enum drm_mode_status
>>>>>    intel_dp_mode_valid(struct drm_connector *_connector,
>>>>>                const struct drm_display_mode *mode)
>>>>> @@ -1445,13 +1462,13 @@ intel_dp_mode_valid(struct drm_connector
>>>>> *_connector,
>>>>>        const struct drm_display_mode *fixed_mode;
>>>>>        int target_clock = mode->clock;
>>>>>        int max_rate, mode_rate, max_lanes, max_link_clock;
>>>>> -    int max_dotclk = display->cdclk.max_dotclk_freq;
>>>>>        u16 dsc_max_compressed_bpp = 0;
>>>>>        u8 dsc_slice_count = 0;
>>>>>        enum drm_mode_status status;
>>>>>        bool dsc = false;
>>>>>        int num_joined_pipes;
>>>>>        int link_bpp_x16;
>>>>> +    int num_pipes;
>>>>>          status = intel_cpu_transcoder_mode_valid(display, mode);
>>>>>        if (status != MODE_OK)
>>>>> @@ -1488,67 +1505,98 @@ intel_dp_mode_valid(struct drm_connector
>>>>> *_connector,
>>>>>                           target_clock, mode->hdisplay,
>>>>>                           link_bpp_x16, 0);
>>>>>    -    num_joined_pipes = intel_dp_num_joined_pipes(intel_dp,
>>>>> connector,
>>>>> -                             mode->hdisplay, target_clock);
>>>>> -    max_dotclk *= num_joined_pipes;
>>>>> -
>>>>> -    if (target_clock > max_dotclk)
>>>>> -        return MODE_CLOCK_HIGH;
>>>>> -
>>>>> -    status = intel_pfit_mode_valid(display, mode,
>>>>> output_format, num_joined_pipes);
>>>>> -    if (status != MODE_OK)
>>>>> -        return status;
>>>>> -
>>>>> -    if (intel_dp_has_dsc(connector)) {
>>>>> -        int pipe_bpp;
>>>>> -
>>>>> -        /*
>>>>> -         * TBD pass the connector BPC,
>>>>> -         * for now U8_MAX so that max BPC on that platform
>>>>> would be picked
>>>>> -         */
>>>>> -        pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
>>>>> -
>>>>> -        /*
>>>>> -         * Output bpp is stored in 6.4 format so right shift by
>>>>> 4 to get the
>>>>> -         * integer value since we support only integer values of bpp.
>>>>> -         */
>>>>> -        if (intel_dp_is_edp(intel_dp)) {
>>>>> -            dsc_max_compressed_bpp =
>>>>> - drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>>>>> -
>>>>> -            dsc_slice_count =
>>>>> -                intel_dp_dsc_get_slice_count(connector,
>>>>> -                                 target_clock,
>>>>> -                                 mode->hdisplay,
>>>>> -                                 num_joined_pipes);
>>>>> -
>>>>> -            dsc = dsc_max_compressed_bpp && dsc_slice_count;
>>>>> -        } else if
>>>>> (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>>>>> -            unsigned long bw_overhead_flags = 0;
>>>>> -
>>>>> -            if (!drm_dp_is_uhbr_rate(max_link_clock))
>>>>> -                bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>>>>> -
>>>>> -            dsc = intel_dp_mode_valid_with_dsc(connector,
>>>>> -                               max_link_clock, max_lanes,
>>>>> -                               target_clock, mode->hdisplay,
>>>>> -                               num_joined_pipes,
>>>>> -                               output_format, pipe_bpp,
>>>>> -                               bw_overhead_flags);
>>>>> +    /*
>>>>> +     * We cannot determine the required pipe‑join count before
>>>>> knowing whether
>>>>> +     * DSC is needed, nor can we determine DSC need without
>>>>> knowing the pipe
>>>>> +     * count.
>>>>> +     * Because of this dependency cycle, the only correct
>>>>> approach is to iterate
>>>>> +     * over candidate pipe counts and evaluate each combination.
>>>>> +     */
>>>>> +    for (num_pipes = 0; num_pipes < I915_MAX_PIPES; num_pipes++) {
>>>>> +        int max_dotclk = display->cdclk.max_dotclk_freq;
>>>>> +
>>>>> +        status = MODE_CLOCK_HIGH;
>>>>> +
>>>>> +        if (num_pipes == 0) {
>>>>> +            if (!connector->force_joined_pipes)
>>>>> +                continue;
>>>>> +            num_joined_pipes = connector->force_joined_pipes;
>>>>> +        } else {
>>>>> +            num_joined_pipes = num_pipes;
>>>>> +        }
>>>> The current way is to try connector->force_joined_pipes and fail the
>>>> commit if that doesn't work. Here you'd change that to fall back trying
>>>> non-forced pipe-joined configs in that case. If that's needed (not sure
>>>> if that's a good idea, since then the user wouldn't know which case
>>>> succeeded or failed), it should be a separate change. Here it could be
>>>> simply an if (forced_joined_pipes && num_pipes != forced_joined_pipes)
>>>> continue and then use num_pipes instead of num_joined_pipes later in the
>>>> loop.
>>> Hmm Yeah the initial thought process was to try force joiner thing
>>> first, if succeed well and good, if not we do our usual thing.
>>>
>>> But I see your point. I think we can just fail the commit if forced
>>> joiner doesn't work.
>>>
>>> This will also help simplify the loop and will allow to have an iterator
>>> macro as you have mentioned in the later patch.
>> For mode_valid phase can there be a corner case where force joiner is set to
>> some high value with which all modes somehow fail?
>>
>> Can hdisplay/htotal or clock  for a mode go below some acceptable value if
>> joiner is used?
> I.e. hdisplay/htotal/clock per-pipe becoming too low, right? I don't
> recall that the driver would check for these anywhere. The mode timing
> itself is checked and then (for instance) MODE_CLOCK_LOW is returned,
> but that's not a per-pipe thing. One thing that can fail is the DSC
> slice count, which can get too high for the sink.
>
> In any case there's not much we can do about any such failure scenario,
> just fail the commit?


Hmm makes sense. I have already started working on this, will send the 
next revision with this change and other suggested changes soon.

Regards,

Ankit

>
>> Regards,
>>
>> Ankit
>>
>>>
>>>>> +
>>>>> +        if (!intel_dp_can_join(display, num_joined_pipes))
>>>>> +            continue;
>>>>> +
>>>>> +        if (mode->hdisplay > num_joined_pipes *
>>>>> intel_dp_max_hdisplay_per_pipe(display))
>>>>> +            continue;
>>>>> +
>>>>> +        status = intel_pfit_mode_valid(display, mode,
>>>>> output_format, num_joined_pipes);
>>>>> +        if (status != MODE_OK)
>>>>> +            continue;
>>>>> +
>>>>> +        if (intel_dp_has_dsc(connector)) {
>>>>> +            int pipe_bpp;
>>>>> +
>>>>> +            /*
>>>>> +             * TBD pass the connector BPC,
>>>>> +             * for now U8_MAX so that max BPC on that platform
>>>>> would be picked
>>>>> +             */
>>>>> +            pipe_bpp = intel_dp_dsc_compute_max_bpp(connector,
>>>>> U8_MAX);
>>>>> +
>>>>> +            /*
>>>>> +             * Output bpp is stored in 6.4 format so right
>>>>> shift by 4 to get the
>>>>> +             * integer value since we support only integer
>>>>> values of bpp.
>>>>> +             */
>>>>> +            if (intel_dp_is_edp(intel_dp)) {
>>>>> +                dsc_max_compressed_bpp =
>>>>> + drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
>>>>> +
>>>>> +                dsc_slice_count =
>>>>> +                    intel_dp_dsc_get_slice_count(connector,
>>>>> +                                     target_clock,
>>>>> +                                     mode->hdisplay,
>>>>> +                                     num_joined_pipes);
>>>>> +
>>>>> +                dsc = dsc_max_compressed_bpp && dsc_slice_count;
>>>>> +            } else if
>>>>> (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
>>>>> +                unsigned long bw_overhead_flags = 0;
>>>>> +
>>>>> +                if (!drm_dp_is_uhbr_rate(max_link_clock))
>>>>> +                    bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC;
>>>>> +
>>>>> +                dsc = intel_dp_mode_valid_with_dsc(connector,
>>>>> +                                   max_link_clock, max_lanes,
>>>>> +                                   target_clock, mode->hdisplay,
>>>>> +                                   num_joined_pipes,
>>>>> +                                   output_format, pipe_bpp,
>>>>> +                                   bw_overhead_flags);
>>>>> +            }
>>>>> +        }
>>>>> +
>>>>> +        if (intel_dp_joiner_needs_dsc(display,
>>>>> num_joined_pipes) && !dsc)
>>>>> +            continue;
>>>>> +
>>>>> +        if (mode_rate > max_rate && !dsc)
>>>>> +            continue;
>>>>> +
>>>>> +        status = intel_mode_valid_max_plane_size(display, mode,
>>>>> num_joined_pipes);
>>>>> +        if (status != MODE_OK)
>>>>> +            continue;
>>>>> +
>>>>> +        max_dotclk *= num_joined_pipes;
>>>>> +
>>>>> +        if (target_clock <= max_dotclk) {
>>>>> +            status = MODE_OK;
>>>> status stays MODE_OK if target_clock > max_dotclk.
>>> Oh yes.. will fix this.
>>>
>>>
>>>>> +            break;
>>>>>            }
>>>>>        }
>>>>>    -    if (intel_dp_joiner_needs_dsc(display, num_joined_pipes)
>>>>> && !dsc)
>>>>> -        return MODE_CLOCK_HIGH;
>>>>> -
>>>>> -    status = intel_mode_valid_max_plane_size(display, mode,
>>>>> num_joined_pipes);
>>>>>        if (status != MODE_OK)
>>>>>            return status;
>>>>>    -    if (mode_rate > max_rate && !dsc)
>>>>> -        return MODE_CLOCK_HIGH;
>>>>> -
>>>>>        return intel_dp_mode_valid_downstream(connector, mode,
>>>>> target_clock);
>>>>> +
>>>> Extra w/s.
>>> Will drop this extra line.
>>>
>>>
>>> Thanks & Regards,
>>>
>>> Ankit
>>>
>>>>>    }
>>>>>      bool intel_dp_source_supports_tps3(struct intel_display *display)
>>>>> -- 
>>>>> 2.45.2
>>>>>

[PATCH 10/16] drm/i915/dp_mst: Rework pipe joiner logic in compute_config

[Ankit Nautiyal]

Similar to the DP SST, refactor mst_stream_compute_config() to iterate
over joiner candidates and select the minimal joiner configuration that
satisfies the mode requirements. This prepares the logic for future changes
that will consider DSC slice overhead.

v2:
 - Move the check for dotclock in the new helper and check for both DSC and
   non-DSC case. In case the check fails for non-DSC, fallback to DSC
   configuration. (Imre)
 - Propagate the return value from the core helper:
   mst_stream_compute_link_for_joined_pipes(). (Imre)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 46 ++++++++++++++++-----
 1 file changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 55b2ccb45e43..c0d854b107b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -602,12 +602,16 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_dp *intel_dp = to_primary_dp(encoder);
+	const struct drm_display_mode *adjusted_mode =
+		&pipe_config->hw.adjusted_mode;
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
+	int max_dotclk = display->cdclk.max_dotclk_freq;
 	struct link_config_limits limits;
 	bool dsc_needed, joiner_needs_dsc;
 	int ret = 0;
 
+	max_dotclk *= num_joined_pipes;
 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
@@ -621,7 +625,7 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
 		if (ret == -EDEADLK)
 			return ret;
 
-		if (ret)
+		if (ret || adjusted_mode->clock > max_dotclk)
 			dsc_needed = true;
 	}
 
@@ -664,6 +668,9 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
 						  pipe_config->dp_m_n.tu);
 		if (ret)
 			return ret;
+
+		if (adjusted_mode->clock > max_dotclk)
+			return -EINVAL;
 	}
 
 	if (ret)
@@ -689,7 +696,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->hw.adjusted_mode;
 	int num_joined_pipes;
-	int ret = 0;
+	int num_pipes;
+	int ret = -EINVAL;
 
 	if (pipe_config->fec_enable &&
 	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
@@ -702,16 +710,32 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	pipe_config->has_pch_encoder = false;
 
-	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
-						     adjusted_mode->crtc_hdisplay,
-						     adjusted_mode->crtc_clock);
-	if (num_joined_pipes > 1)
-		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
+	for (num_pipes = 1; num_pipes <= I915_MAX_PIPES; num_pipes++) {
+		if (connector->force_joined_pipes &&
+		    num_pipes != connector->force_joined_pipes)
+			continue;
+
+		num_joined_pipes = num_pipes;
+
+		if (!intel_dp_can_join(display, num_joined_pipes))
+			continue;
+
+		if (adjusted_mode->hdisplay >
+		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
+			continue;
+
+		if (num_joined_pipes > 1)
+			pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
+							    crtc->pipe);
+
+		ret = mst_stream_compute_link_for_joined_pipes(encoder,
+							       pipe_config,
+							       conn_state,
+							       num_joined_pipes);
+		if (!ret)
+			break;
+	}
 
-	ret = mst_stream_compute_link_for_joined_pipes(encoder,
-						       pipe_config,
-						       conn_state,
-						       num_joined_pipes);
 	if (ret)
 		return ret;
 
-- 
2.45.2

Re: [PATCH 10/16] drm/i915/dp_mst: Rework pipe joiner logic in compute_config

[Imre Deak]

On Thu, Jan 29, 2026 at 10:41:48PM +0530, Ankit Nautiyal wrote:
> Similar to the DP SST, refactor mst_stream_compute_config() to iterate
> over joiner candidates and select the minimal joiner configuration that
> satisfies the mode requirements. This prepares the logic for future changes
> that will consider DSC slice overhead.
> 
> v2:
>  - Move the check for dotclock in the new helper and check for both DSC and
>    non-DSC case. In case the check fails for non-DSC, fallback to DSC
>    configuration. (Imre)
>  - Propagate the return value from the core helper:
>    mst_stream_compute_link_for_joined_pipes(). (Imre)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 46 ++++++++++++++++-----
>  1 file changed, 35 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 55b2ccb45e43..c0d854b107b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -602,12 +602,16 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_dp *intel_dp = to_primary_dp(encoder);
> +	const struct drm_display_mode *adjusted_mode =
> +		&pipe_config->hw.adjusted_mode;
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	struct link_config_limits limits;
>  	bool dsc_needed, joiner_needs_dsc;
>  	int ret = 0;
>  
> +	max_dotclk *= num_joined_pipes;
>  	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
>  
>  	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
> @@ -621,7 +625,7 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
>  		if (ret == -EDEADLK)
>  			return ret;
>  
> -		if (ret)
> +		if (ret || adjusted_mode->clock > max_dotclk)
>  			dsc_needed = true;
>  	}
>  
> @@ -664,6 +668,9 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
>  						  pipe_config->dp_m_n.tu);
>  		if (ret)
>  			return ret;
> +
> +		if (adjusted_mode->clock > max_dotclk)
> +			return -EINVAL;
>  	}
>  
>  	if (ret)
> @@ -689,7 +696,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	const struct drm_display_mode *adjusted_mode =
>  		&pipe_config->hw.adjusted_mode;
>  	int num_joined_pipes;
> -	int ret = 0;
> +	int num_pipes;
> +	int ret = -EINVAL;
>  
>  	if (pipe_config->fec_enable &&
>  	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))
> @@ -702,16 +710,32 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
>  	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	pipe_config->has_pch_encoder = false;
>  
> -	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
> -						     adjusted_mode->crtc_hdisplay,
> -						     adjusted_mode->crtc_clock);
> -	if (num_joined_pipes > 1)
> -		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
> +	for (num_pipes = 1; num_pipes <= I915_MAX_PIPES; num_pipes++) {
> +		if (connector->force_joined_pipes &&
> +		    num_pipes != connector->force_joined_pipes)
> +			continue;
> +
> +		num_joined_pipes = num_pipes;

No need for two variables, fixing that:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +		if (!intel_dp_can_join(display, num_joined_pipes))
> +			continue;
> +
> +		if (adjusted_mode->hdisplay >
> +		    num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
> +			continue;
> +
> +		if (num_joined_pipes > 1)
> +			pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
> +							    crtc->pipe);
> +
> +		ret = mst_stream_compute_link_for_joined_pipes(encoder,
> +							       pipe_config,
> +							       conn_state,
> +							       num_joined_pipes);
> +		if (!ret)
> +			break;
> +	}
>  
> -	ret = mst_stream_compute_link_for_joined_pipes(encoder,
> -						       pipe_config,
> -						       conn_state,
> -						       num_joined_pipes);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.45.2
>