[PATCH 1/2] drm/i915: PPGTT Cacheability Override

[PATCH 1/2] drm/i915: PPGTT Cacheability Override

[Rodrigo Vivi]

Override Cacheability to WB in LLC/eLLC - Aged 3 1000
for better performance.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d091fec..b0fd5ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6186,7 +6186,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
 	ilk_init_lp_watermarks(dev);
 
 	/* WaSwitchSolVfFArbitrationPriority:bdw */
-	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL |
+		   ECOCHK_PPGTT_WB_HSW);
 
 	/* WaPsrDPAMaskVBlankInSRD:bdw */
 	I915_WRITE(CHICKEN_PAR1_1,
-- 
2.1.0

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[PATCH 2/2] drm/i915/bdw: WaGttCachingOffByDefault: bdw

[Rodrigo Vivi]

Due to RTL Bug, GAM does not support enabling GTT cache when
big pages are also turned on. This leads to GAM reporting
incorrect data and address.
For A0 let the register GTT_CACHE_EN use the default value[0x00000000].
For B0 onwards enable the GTT cache by setting the GTT_CACHE_EN[04024h]
to value 0xF0007FFF instead of default value[0x000000].

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f72c0e..13474f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -157,6 +157,9 @@
 #define   GEN8_RPCS_EU_MIN_SHIFT	0
 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
 
+#define GEN8_GTT_CACHE_EN		0x4024
+#define   GEN8_GTT_CACHE_DEFAULT	0xf0007fff
+
 #define GAM_ECOCHK			0x4090
 #define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
 #define   ECOCHK_SNB_BIT		(1<<10)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0fd5ec..dbb7059 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6285,6 +6285,9 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
 
+	/* WaGttCachingOffByDefault:bdw */
+	I915_WRITE(GEN8_GTT_CACHE_EN, GEN8_GTT_CACHE_DEFAULT);
+
 	lpt_init_clock_gating(dev);
 }
 
-- 
2.1.0

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Re: [PATCH 2/2] drm/i915/bdw: WaGttCachingOffByDefault: bdw

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6548
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 2/2] drm/i915/bdw: WaGttCachingOffByDefault: bdw

[Damien Lespiau]

On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote:
> Due to RTL Bug, GAM does not support enabling GTT cache when
> big pages are also turned on. This leads to GAM reporting
> incorrect data and address.

We don't use big pages, so we can leave GTT caching enabled until we
support them (which may be never?).

-- 
Damien

> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f72c0e..13474f3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -157,6 +157,9 @@
>  #define   GEN8_RPCS_EU_MIN_SHIFT	0
>  #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
>  
> +#define GEN8_GTT_CACHE_EN		0x4024
> +#define   GEN8_GTT_CACHE_DEFAULT	0xf0007fff
> +
>  #define GAM_ECOCHK			0x4090
>  #define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
>  #define   ECOCHK_SNB_BIT		(1<<10)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b0fd5ec..dbb7059 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6285,6 +6285,9 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(CHICKEN_PAR1_1,
>  		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
>  
> +	/* WaGttCachingOffByDefault:bdw */
> +	I915_WRITE(GEN8_GTT_CACHE_EN, GEN8_GTT_CACHE_DEFAULT);
> +
>  	lpt_init_clock_gating(dev);
>  }
>  
> -- 
> 2.1.0
> 
> _______________________________________________
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Re: [PATCH 2/2] drm/i915/bdw: WaGttCachingOffByDefault: bdw

[Chris Wilson]

On Mon, Jun 08, 2015 at 08:20:48PM +0100, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote:
> > Due to RTL Bug, GAM does not support enabling GTT cache when
> > big pages are also turned on. This leads to GAM reporting
> > incorrect data and address.
> 
> We don't use big pages, so we can leave GTT caching enabled until we
> support them (which may be never?).
> 
Also useful to leave a clue here for our future selves.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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