[PATCH 0/7] updated ppgtt patches

[PATCH 0/7] updated ppgtt patches

[Daniel Vetter]

Hi all,

I've rebased and updated my ppgtt patches. Only changes are somewhat improved
commit messages (especially for the final patch that actually enables ppgtt) and
an added module option in the last patch to please Chris.

Assuming nothing pops up I plan to merge this in 1-2 days.

Cheers, Daniel

Daniel Vetter (7):
  agp/intel-gtt: export the scratch page dma address
  agp/intel-gtt: export the gtt pagetable iomapping
  drm/i915: initialization/teardown for the aliasing ppgtt
  drm/i915: ppgtt binding/unbinding support
  drm/i915: ppgtt register definitions
  drm/i915: ppgtt debugfs info
  drm/i915: enable ppgtt

 drivers/char/agp/intel-gtt.c               |   10 +-
 drivers/gpu/drm/i915/i915_debugfs.c        |   38 ++++
 drivers/gpu/drm/i915/i915_dma.c            |   41 +++-
 drivers/gpu/drm/i915/i915_drv.c            |    7 +
 drivers/gpu/drm/i915/i915_drv.h            |   27 +++
 drivers/gpu/drm/i915/i915_gem.c            |   50 +++++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |    9 +
 drivers/gpu/drm/i915/i915_gem_gtt.c        |  273 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |   34 ++++
 include/drm/intel-gtt.h                    |    4 +
 10 files changed, 477 insertions(+), 16 deletions(-)

-- 
1.7.8.2

[PATCH 1/7] agp/intel-gtt: export the scratch page dma address

[Daniel Vetter]

To implement a PPGTT for drm/i915 that fully aliases the GTT, we also
need to properly alias the scratch page.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/char/agp/intel-gtt.c |    9 ++++-----
 include/drm/intel-gtt.h      |    2 ++
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index c92424c..0a305ac 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -76,7 +76,6 @@ static struct _intel_private {
 	struct resource ifp_resource;
 	int resource_valid;
 	struct page *scratch_page;
-	dma_addr_t scratch_page_dma;
 } intel_private;
 
 #define INTEL_GTT_GEN	intel_private.driver->gen
@@ -306,9 +305,9 @@ static int intel_gtt_setup_scratch_page(void)
 		if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 			return -EINVAL;
 
-		intel_private.scratch_page_dma = dma_addr;
+		intel_private.base.scratch_page_dma = dma_addr;
 	} else
-		intel_private.scratch_page_dma = page_to_phys(page);
+		intel_private.base.scratch_page_dma = page_to_phys(page);
 
 	intel_private.scratch_page = page;
 
@@ -631,7 +630,7 @@ static unsigned int intel_gtt_mappable_entries(void)
 static void intel_gtt_teardown_scratch_page(void)
 {
 	set_pages_wb(intel_private.scratch_page, 1);
-	pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
+	pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
 		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 	put_page(intel_private.scratch_page);
 	__free_page(intel_private.scratch_page);
@@ -975,7 +974,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 	unsigned int i;
 
 	for (i = first_entry; i < (first_entry + num_entries); i++) {
-		intel_private.driver->write_entry(intel_private.scratch_page_dma,
+		intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
 						  i, 0);
 	}
 	readl(intel_private.gtt+i-1);
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index b174620..6d4c77a 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -15,6 +15,8 @@ const struct intel_gtt {
 	unsigned int needs_dmar : 1;
 	/* Whether we idle the gpu before mapping/unmapping */
 	unsigned int do_idle_maps : 1;
+	/* Share the scratch page dma with ppgtts. */
+	dma_addr_t scratch_page_dma;
 } *intel_gtt_get(void);
 
 void intel_gtt_chipset_flush(void);
-- 
1.7.8.2

[PATCH 2/7] agp/intel-gtt: export the gtt pagetable iomapping

[Daniel Vetter]

We need this because ppgtt page directory entries need to be in the
global gtt pagetable.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/char/agp/intel-gtt.c |    1 +
 include/drm/intel-gtt.h      |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0a305ac..5cf47ac 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -680,6 +680,7 @@ static int intel_gtt_init(void)
 		iounmap(intel_private.registers);
 		return -ENOMEM;
 	}
+	intel_private.base.gtt = intel_private.gtt;
 
 	global_cache_flush();   /* FIXME: ? */
 
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index 6d4c77a..0a0001b 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -17,6 +17,8 @@ const struct intel_gtt {
 	unsigned int do_idle_maps : 1;
 	/* Share the scratch page dma with ppgtts. */
 	dma_addr_t scratch_page_dma;
+	/* for ppgtt PDE access */
+	u32 __iomem *gtt;
 } *intel_gtt_get(void);
 
 void intel_gtt_chipset_flush(void);
-- 
1.7.8.2

[PATCH 3/7] drm/i915: initialization/teardown for the aliasing ppgtt

[Daniel Vetter]

This just adds the setup and teardown code for the ppgtt PDE and the
last-level pagetables, which are fixed for the entire lifetime, at
least for the moment.

v2: Kill the stray debug printk noted by and improve the pte
definitions as suggested by Chris Wilson.

v3: Clean up the aperture stealing code as noted by Ben Widawsky.

v4: Paint the init code in a more pleasing colour as suggest by Chris
Wilson.

v5: Explain the magic numbers noticed by Ben Widawsky.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_dma.c     |   41 ++++++++---
 drivers/gpu/drm/i915/i915_drv.h     |   18 +++++
 drivers/gpu/drm/i915/i915_gem_gtt.c |  139 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |   16 ++++
 4 files changed, 203 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index cdcdef2..1186032 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1196,22 +1196,39 @@ static int i915_load_gem_init(struct drm_device *dev)
 	/* Basic memrange allocator for stolen space */
 	drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 
-	/* Let GEM Manage all of the aperture.
-	 *
-	 * However, leave one page at the end still bound to the scratch page.
-	 * There are a number of places where the hardware apparently
-	 * prefetches past the end of the object, and we've seen multiple
-	 * hangs with the GPU head pointer stuck in a batchbuffer bound
-	 * at the last page of the aperture.  One page should be enough to
-	 * keep any prefetching inside of the aperture.
-	 */
-	i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
+	if (HAS_ALIASING_PPGTT(dev)) {
+		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
+		 * aperture accordingly when using aliasing ppgtt. */
+		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
+		/* For paranoia keep the guard page in between. */
+		gtt_size -= PAGE_SIZE;
+
+		i915_gem_do_init(dev, 0, mappable_size, gtt_size);
+
+		ret = i915_gem_init_aliasing_ppgtt(dev);
+		if (ret)
+			return ret;
+	} else {
+		/* Let GEM Manage all of the aperture.
+		 *
+		 * However, leave one page at the end still bound to the scratch
+		 * page.  There are a number of places where the hardware
+		 * apparently prefetches past the end of the object, and we've
+		 * seen multiple hangs with the GPU head pointer stuck in a
+		 * batchbuffer bound at the last page of the aperture.  One page
+		 * should be enough to keep any prefetching inside of the
+		 * aperture.
+		 */
+		i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
+	}
 
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_gem_init_hw(dev);
 	mutex_unlock(&dev->struct_mutex);
-	if (ret)
+	if (ret) {
+		i915_gem_cleanup_aliasing_ppgtt(dev);
 		return ret;
+	}
 
 	/* Try to set up FBC with a reasonable compressed buffer size */
 	if (I915_HAS_FBC(dev) && i915_powersave) {
@@ -1298,6 +1315,7 @@ cleanup_gem:
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_cleanup_ringbuffer(dev);
 	mutex_unlock(&dev->struct_mutex);
+	i915_gem_cleanup_aliasing_ppgtt(dev);
 cleanup_vga_switcheroo:
 	vga_switcheroo_unregister_client(dev->pdev);
 cleanup_vga_client:
@@ -2185,6 +2203,7 @@ int i915_driver_unload(struct drm_device *dev)
 		i915_gem_free_all_phys_object(dev);
 		i915_gem_cleanup_ringbuffer(dev);
 		mutex_unlock(&dev->struct_mutex);
+		i915_gem_cleanup_aliasing_ppgtt(dev);
 		if (I915_HAS_FBC(dev) && i915_powersave)
 			i915_cleanup_compression(dev);
 		drm_mm_takedown(&dev_priv->mm.stolen);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c10d56f..b79991e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -263,6 +263,16 @@ struct intel_device_info {
 	u8 has_llc:1;
 };
 
+#define I915_PPGTT_PD_ENTRIES 512
+#define I915_PPGTT_PT_ENTRIES 1024
+struct i915_hw_ppgtt {
+	unsigned num_pd_entries;
+	struct page **pt_pages;
+	uint32_t pd_offset;
+	dma_addr_t *pt_dma_addr;
+	dma_addr_t scratch_page_dma_addr;
+};
+
 enum no_fbc_reason {
 	FBC_NO_OUTPUT, /* no outputs enabled to compress */
 	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
@@ -593,6 +603,9 @@ typedef struct drm_i915_private {
 		struct io_mapping *gtt_mapping;
 		int gtt_mtrr;
 
+		/** PPGTT used for aliasing the PPGTT with the GTT */
+		struct i915_hw_ppgtt *aliasing_ppgtt;
+
 		struct shrinker inactive_shrinker;
 
 		/**
@@ -986,6 +999,8 @@ struct drm_i915_file_private {
 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
+#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >=6)
+
 #define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
 
@@ -1248,6 +1263,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 				    enum i915_cache_level cache_level);
 
 /* i915_gem_gtt.c */
+int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
+void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
+
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 11bddd5..f408f8c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -29,6 +29,145 @@
 #include "i915_trace.h"
 #include "intel_drv.h"
 
+/* PPGTT support for Sandybdrige/Gen6 and later */
+static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
+				   unsigned first_entry,
+				   unsigned num_entries)
+{
+	int i, j;
+	uint32_t *pt_vaddr;
+	uint32_t scratch_pte;
+
+	scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
+	scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;
+
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		pt_vaddr = kmap_atomic(ppgtt->pt_pages[i]);
+
+		for (j = 0; j < I915_PPGTT_PT_ENTRIES; j++)
+			pt_vaddr[j] = scratch_pte;
+
+		kunmap_atomic(pt_vaddr);
+	}
+
+}
+
+int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_hw_ppgtt *ppgtt;
+	uint32_t pd_entry;
+	unsigned first_pd_entry_in_global_pt;
+	uint32_t __iomem *pd_addr;
+	int i;
+	int ret = -ENOMEM;
+
+	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
+	 * entries. For aliasing ppgtt support we just steal them at the end for
+	 * now. */
+	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ret;
+
+	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
+	ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
+				  GFP_KERNEL);
+	if (!ppgtt->pt_pages)
+		goto err_ppgtt;
+
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
+		if (!ppgtt->pt_pages[i])
+			goto err_pt_alloc;
+	}
+
+	if (dev_priv->mm.gtt->needs_dmar) {
+		ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
+						*ppgtt->num_pd_entries,
+					     GFP_KERNEL);
+		if (!ppgtt->pt_dma_addr)
+			goto err_pt_alloc;
+	}
+
+	pd_addr = dev_priv->mm.gtt->gtt + first_pd_entry_in_global_pt;
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		dma_addr_t pt_addr;
+		if (dev_priv->mm.gtt->needs_dmar) {
+			pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
+					       0, 4096,
+					       PCI_DMA_BIDIRECTIONAL);
+
+			if (pci_dma_mapping_error(dev->pdev,
+						  pt_addr)) {
+				ret = -EIO;
+				goto err_pd_pin;
+
+			}
+			ppgtt->pt_dma_addr[i] = pt_addr;
+		} else
+			pt_addr = page_to_phys(ppgtt->pt_pages[i]);
+
+		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
+		pd_entry |= GEN6_PDE_VALID;
+
+		writel(pd_entry, pd_addr + i);
+	}
+	readl(pd_addr);
+
+	ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
+
+	i915_ppgtt_clear_range(ppgtt, 0,
+			       ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
+
+	ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t);
+
+	dev_priv->mm.aliasing_ppgtt = ppgtt;
+
+	return 0;
+
+err_pd_pin:
+	if (ppgtt->pt_dma_addr) {
+		for (i--; i >= 0; i--)
+			pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
+				       4096, PCI_DMA_BIDIRECTIONAL);
+	}
+err_pt_alloc:
+	kfree(ppgtt->pt_dma_addr);
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		if (ppgtt->pt_pages[i])
+			__free_page(ppgtt->pt_pages[i]);
+	}
+	kfree(ppgtt->pt_pages);
+err_ppgtt:
+	kfree(ppgtt);
+
+	return ret;
+}
+
+void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int i;
+
+	if (!ppgtt)
+		return;
+
+	if (ppgtt->pt_dma_addr) {
+		for (i = 0; i < ppgtt->num_pd_entries; i++)
+			pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
+				       4096, PCI_DMA_BIDIRECTIONAL);
+	}
+
+	kfree(ppgtt->pt_dma_addr);
+	for (i = 0; i < ppgtt->num_pd_entries; i++)
+		__free_page(ppgtt->pt_pages[i]);
+	kfree(ppgtt->pt_pages);
+	kfree(ppgtt);
+}
+
 /* XXX kill agp_type! */
 static unsigned int cache_level_to_agp_type(struct drm_device *dev,
 					    enum i915_cache_level cache_level)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 89816fe..92eb404 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -92,6 +92,22 @@
 #define  GEN6_GRDOM_MEDIA		(1 << 2)
 #define  GEN6_GRDOM_BLT			(1 << 3)
 
+/* PPGTT stuff */
+#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
+
+#define GEN6_PDE_VALID			(1 << 0)
+#define GEN6_PDE_LARGE_PAGE		(2 << 0) /* use 32kb pages */
+/* gen6+ has bit 11-4 for physical addr bit 39-32 */
+#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+
+#define GEN6_PTE_VALID			(1 << 0)
+#define GEN6_PTE_UNCACHED		(1 << 1)
+#define GEN6_PTE_CACHE_LLC		(2 << 1)
+#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
+#define GEN6_PTE_CACHE_BITS		(3 << 1)
+#define GEN6_PTE_GFDT			(1 << 3)
+#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+
 /* VGA stuff */
 
 #define VGA_ST01_MDA 0x3ba
-- 
1.7.8.2

[PATCH 4/7] drm/i915: ppgtt binding/unbinding support

[Daniel Vetter]

This adds support to bind/unbind objects and wires it up. Objects are
only put into the ppgtt when necessary, i.e. at execbuf time.

Objects are still unconditionally put into the global gtt.

v2: Kill the quick hack and explicitly pass cache_level to ppgtt_bind
like for the global gtt function. Noticed by Chris Wilson.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h            |    7 ++
 drivers/gpu/drm/i915/i915_gem.c            |   11 ++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |    9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c        |  146 ++++++++++++++++++++++++++-
 4 files changed, 167 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b79991e..14b8e1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -863,6 +863,8 @@ struct drm_i915_gem_object {
 
 	unsigned int cache_level:2;
 
+	unsigned int has_aliasing_ppgtt_mapping:1;
+
 	struct page **pages;
 
 	/**
@@ -1265,6 +1267,11 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 /* i915_gem_gtt.c */
 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
+void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
+			    struct drm_i915_gem_object *obj,
+			    enum i915_cache_level cache_level);
+void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
+			      struct drm_i915_gem_object *obj);
 
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 168a298..23c6bf1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2018,6 +2018,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
 int
 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
 {
+	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 	int ret = 0;
 
 	if (obj->gtt_space == NULL)
@@ -2062,6 +2063,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
 	trace_i915_gem_object_unbind(obj);
 
 	i915_gem_gtt_unbind_object(obj);
+	if (obj->has_aliasing_ppgtt_mapping) {
+		i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
+		obj->has_aliasing_ppgtt_mapping = 0;
+	}
+
 	i915_gem_object_put_pages_gtt(obj);
 
 	list_del_init(&obj->gtt_list);
@@ -2880,6 +2886,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 				    enum i915_cache_level cache_level)
 {
+	struct drm_device *dev = obj->base.dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
 	int ret;
 
 	if (obj->cache_level == cache_level)
@@ -2908,6 +2916,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 		}
 
 		i915_gem_gtt_rebind_object(obj, cache_level);
+		if (obj->has_aliasing_ppgtt_mapping)
+			i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
+					       obj, cache_level);
 	}
 
 	if (cache_level == I915_CACHE_NONE) {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 83f4c19..58b2b41 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -531,6 +531,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 			    struct drm_file *file,
 			    struct list_head *objects)
 {
+	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	int ret, retry;
 	bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
@@ -637,6 +638,14 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 			}
 
 			i915_gem_object_unpin(obj);
+
+			/* ... and ensure ppgtt mapping exist if needed. */
+			if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
+				i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
+						       obj, obj->cache_level);
+
+				obj->has_aliasing_ppgtt_mapping = 1;
+			}
 		}
 
 		if (ret != -ENOSPC || retry > 1)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f408f8c..2eacd78 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -34,22 +34,31 @@ static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 				   unsigned first_entry,
 				   unsigned num_entries)
 {
-	int i, j;
 	uint32_t *pt_vaddr;
 	uint32_t scratch_pte;
+	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
+	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+	unsigned last_pte, i;
 
 	scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
 	scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;
 
-	for (i = 0; i < ppgtt->num_pd_entries; i++) {
-		pt_vaddr = kmap_atomic(ppgtt->pt_pages[i]);
+	while (num_entries) {
+		last_pte = first_pte + num_entries;
+		if (last_pte > I915_PPGTT_PT_ENTRIES)
+			last_pte = I915_PPGTT_PT_ENTRIES;
+
+		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 
-		for (j = 0; j < I915_PPGTT_PT_ENTRIES; j++)
-			pt_vaddr[j] = scratch_pte;
+		for (i = first_pte; i < last_pte; i++)
+			pt_vaddr[i] = scratch_pte;
 
 		kunmap_atomic(pt_vaddr);
-	}
 
+		num_entries -= last_pte - first_pte;
+		first_pte = 0;
+		act_pd++;
+	}
 }
 
 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
@@ -168,6 +177,131 @@ void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 	kfree(ppgtt);
 }
 
+static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
+					 struct scatterlist *sg_list,
+					 unsigned sg_len,
+					 unsigned first_entry,
+					 uint32_t pte_flags)
+{
+	uint32_t *pt_vaddr, pte;
+	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
+	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+	unsigned i, j, m, segment_len;
+	dma_addr_t page_addr;
+	struct scatterlist *sg;
+
+	/* init sg walking */
+	sg = sg_list;
+	i = 0;
+	segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
+	m = 0;
+
+	while (i < sg_len) {
+		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
+
+		for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
+			page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
+			pte = GEN6_PTE_ADDR_ENCODE(page_addr);
+			pt_vaddr[j] = pte | pte_flags;
+
+			/* grab the next page */
+			m++;
+			if (m == segment_len) {
+				sg = sg_next(sg);
+				i++;
+				if (i == sg_len)
+					break;
+
+				segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
+				m = 0;
+			}
+		}
+
+		kunmap_atomic(pt_vaddr);
+
+		first_pte = 0;
+		act_pd++;
+	}
+}
+
+static void i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt,
+				    unsigned first_entry, unsigned num_entries,
+				    struct page **pages, uint32_t pte_flags)
+{
+	uint32_t *pt_vaddr, pte;
+	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
+	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+	unsigned last_pte, i;
+	dma_addr_t page_addr;
+
+	while (num_entries) {
+		last_pte = first_pte + num_entries;
+		last_pte = min_t(unsigned, last_pte, I915_PPGTT_PT_ENTRIES);
+
+		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
+
+		for (i = first_pte; i < last_pte; i++) {
+			page_addr = page_to_phys(*pages);
+			pte = GEN6_PTE_ADDR_ENCODE(page_addr);
+			pt_vaddr[i] = pte | pte_flags;
+
+			pages++;
+		}
+
+		kunmap_atomic(pt_vaddr);
+
+		num_entries -= last_pte - first_pte;
+		first_pte = 0;
+		act_pd++;
+	}
+}
+
+void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
+			    struct drm_i915_gem_object *obj,
+			    enum i915_cache_level cache_level)
+{
+	struct drm_device *dev = obj->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t pte_flags = GEN6_PTE_VALID;
+
+	switch (cache_level) {
+	case I915_CACHE_LLC_MLC:
+		pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
+		break;
+	case I915_CACHE_LLC:
+		pte_flags |= GEN6_PTE_CACHE_LLC;
+		break;
+	case I915_CACHE_NONE:
+		pte_flags |= GEN6_PTE_UNCACHED;
+		break;
+	default:
+		BUG();
+	}
+
+	if (dev_priv->mm.gtt->needs_dmar) {
+		BUG_ON(!obj->sg_list);
+
+		i915_ppgtt_insert_sg_entries(ppgtt,
+					     obj->sg_list,
+					     obj->num_sg,
+					     obj->gtt_space->start >> PAGE_SHIFT,
+					     pte_flags);
+	} else
+		i915_ppgtt_insert_pages(ppgtt,
+					obj->gtt_space->start >> PAGE_SHIFT,
+					obj->base.size >> PAGE_SHIFT,
+					obj->pages,
+					pte_flags);
+}
+
+void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
+			      struct drm_i915_gem_object *obj)
+{
+	i915_ppgtt_clear_range(ppgtt,
+			       obj->gtt_space->start >> PAGE_SHIFT,
+			       obj->base.size >> PAGE_SHIFT);
+}
+
 /* XXX kill agp_type! */
 static unsigned int cache_level_to_agp_type(struct drm_device *dev,
 					    enum i915_cache_level cache_level)
-- 
1.7.8.2

[PATCH 5/7] drm/i915: ppgtt register definitions

[Daniel Vetter]

Split out for easier cross-checking of the boring pieces with bspec.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92eb404..341ce44 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -86,6 +86,13 @@
 #define   GEN6_MBC_SNPCR_LOW	(2<<21)
 #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
 
+#define GEN6_MBCTL		0x0907c
+#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
+#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
+#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
+#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
+#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
+
 #define GEN6_GDRST	0x941c
 #define  GEN6_GRDOM_FULL		(1 << 0)
 #define  GEN6_GRDOM_RENDER		(1 << 1)
@@ -108,6 +115,16 @@
 #define GEN6_PTE_GFDT			(1 << 3)
 #define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 
+#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
+#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
+#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
+#define   PP_DIR_DCLV_2G		0xffffffff
+
+#define GAM_ECOCHK			0x4090
+#define   ECOCHK_SNB_BIT		(1<<10)
+#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
+#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
+
 /* VGA stuff */
 
 #define VGA_ST01_MDA 0x3ba
@@ -422,6 +439,7 @@
 
 #define GFX_MODE	0x02520
 #define GFX_MODE_GEN7	0x0229c
+#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
 #define   GFX_RUN_LIST_ENABLE		(1<<15)
 #define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
 #define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
-- 
1.7.8.2

[PATCH 6/7] drm/i915: ppgtt debugfs info

[Daniel Vetter]

This was pretty usefull for debugging, might be useful for diagnosing
issues.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c |   38 +++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 214b5b3..c55e12c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1454,6 +1454,43 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_ppgtt_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	int i, ret;
+
+
+	ret = mutex_lock_interruptible(&dev->struct_mutex);
+	if (ret)
+		return ret;
+	if (INTEL_INFO(dev)->gen == 6)
+		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
+
+	for (i = 0; i < I915_NUM_RINGS; i++) {
+		ring = &dev_priv->ring[i];
+
+		seq_printf(m, "%s\n", ring->name);
+		if (INTEL_INFO(dev)->gen == 7)
+			seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
+		seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
+		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
+		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
+	}
+	if (dev_priv->mm.aliasing_ppgtt) {
+		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+
+		seq_printf(m, "aliasing PPGTT:\n");
+		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
+	}
+	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
+	mutex_unlock(&dev->struct_mutex);
+
+	return 0;
+}
+
 static int
 i915_debugfs_common_open(struct inode *inode,
 			 struct file *filp)
@@ -1855,6 +1892,7 @@ static struct drm_info_list i915_debugfs_list[] = {
 	{"i915_context_status", i915_context_status, 0},
 	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
 	{"i915_swizzle_info", i915_swizzle_info, 0},
+	{"i915_ppgtt_info", i915_ppgtt_info, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
 
-- 
1.7.8.2

[PATCH 7/7] drm/i915: enable ppgtt

[Daniel Vetter]

We want to unconditionally enable ppgtt for two reasons:
- Windows uses this on snb and later.
- We need the basic hw support to work before we can think about real
  per-process address spaces and other cool features we want.

But Chris Wilson was complaining all over irc and intel-gfx that this
will blow up if we don't have a module option to disable it. Hence add
one, to prevent this.

ppgtt support seems to slightly change the timings and make crashy
things slightly more or less crashy. Now in my testing and the testing
this got on troublesome snb machines, it seems to have improved things
only. But on ivb it makes quite a few crashes happen much more often,
see

https://bugs.freedesktop.org/show_bug.cgi?id=41353

Luckily Eugeni Dodonov seems to have a set of workarounds that fix
this issue.

v2: Don't try to enable ppgtt on pre-snb.

v3: Pimp commit message and make Chris Wilson less grumpy by adding a
module option.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c |    7 +++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 drivers/gpu/drm/i915/i915_gem.c |   39 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1537d46..891b862 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -103,6 +103,11 @@ MODULE_PARM_DESC(enable_hangcheck,
 		"WARNING: Disabling this can cause system wide hangs. "
 		"(default: true)");
 
+bool i915_enable_ppgtt __read_mostly = 1;
+module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
+MODULE_PARM_DESC(i915_enable_ppgtt,
+		"Enable PPGTT (default: true)");
+
 static struct drm_driver driver;
 extern int intel_agp_enabled;
 
@@ -702,6 +707,8 @@ int i915_reset(struct drm_device *dev, u8 flags)
 		if (HAS_BLT(dev))
 		    dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 
+		i915_gem_init_ppgtt(dev);
+
 		mutex_unlock(&dev->struct_mutex);
 		drm_irq_uninstall(dev);
 		drm_mode_config_reset(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14b8e1f..60a2f53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1045,6 +1045,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly;
 extern int i915_enable_rc6 __read_mostly;
 extern int i915_enable_fbc __read_mostly;
 extern bool i915_enable_hangcheck __read_mostly;
+extern bool i915_enable_ppgtt __read_mostly;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
@@ -1224,6 +1225,7 @@ int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
 void i915_gem_init_swizzling(struct drm_device *dev);
+void i915_gem_init_ppgtt(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 void i915_gem_do_init(struct drm_device *dev,
 		      unsigned long start,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 23c6bf1..b924351 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3713,6 +3713,43 @@ void i915_gem_init_swizzling(struct drm_device *dev)
 	else
 		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 }
+
+void i915_gem_init_ppgtt(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t pd_offset;
+	struct intel_ring_buffer *ring;
+	int i;
+
+	if (i915_enable_ppgtt && !HAS_ALIASING_PPGTT(dev))
+		return;
+
+	pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset;
+	pd_offset /= 64; /* in cachelines, */
+	pd_offset <<= 16;
+
+	if (INTEL_INFO(dev)->gen == 6) {
+		uint32_t ecochk = I915_READ(GAM_ECOCHK);
+		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
+				       ECOCHK_PPGTT_CACHE64B);
+		I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
+	} else if (INTEL_INFO(dev)->gen >= 7) {
+		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
+		/* GFX_MODE is per-ring on gen7+ */
+	}
+
+	for (i = 0; i < I915_NUM_RINGS; i++) {
+		ring = &dev_priv->ring[i];
+
+		if (INTEL_INFO(dev)->gen >= 7)
+			I915_WRITE(RING_MODE_GEN7(ring),
+				   GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
+
+		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
+	}
+}
+
 int
 i915_gem_init_hw(struct drm_device *dev)
 {
@@ -3739,6 +3776,8 @@ i915_gem_init_hw(struct drm_device *dev)
 
 	dev_priv->next_seqno = 1;
 
+	i915_gem_init_ppgtt(dev);
+
 	return 0;
 
 cleanup_bsd_ring:
-- 
1.7.8.2

Re: [PATCH 7/7] drm/i915: enable ppgtt

[Chris Wilson]

On Thu,  9 Feb 2012 17:15:50 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> v3: Pimp commit message and make Chris Wilson less grumpy by adding a
> module option.

> +void i915_gem_init_ppgtt(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	uint32_t pd_offset;
> +	struct intel_ring_buffer *ring;
> +	int i;
> +
> +	if (i915_enable_ppgtt && !HAS_ALIASING_PPGTT(dev))
> +		return;
> +

This is quite a late check since we have already partitioned the
aperture and run i915_gem_init_aliasing_ppgtt. I think the enable check
should be done earlier and this check reduced to
  if (!dev_priv->mm.aliasing_ppgtt)
    return;

Bah humbug!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 7/7] drm/i915: enable ppgtt

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 1160 bytes --]

On Thu, Feb 9, 2012 at 14:39, Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Thu,  9 Feb 2012 17:15:50 +0100, Daniel Vetter <daniel.vetter@ffwll.ch>
> wrote:
> > v3: Pimp commit message and make Chris Wilson less grumpy by adding a
> > module option.
>
> > +void i915_gem_init_ppgtt(struct drm_device *dev)
> > +{
> > +     drm_i915_private_t *dev_priv = dev->dev_private;
> > +     uint32_t pd_offset;
> > +     struct intel_ring_buffer *ring;
> > +     int i;
> > +
> > +     if (i915_enable_ppgtt && !HAS_ALIASING_PPGTT(dev))
> > +             return;
> > +
>
> This is quite a late check since we have already partitioned the
> aperture and run i915_gem_init_aliasing_ppgtt. I think the enable check
> should be done earlier and this check reduced to
>  if (!dev_priv->mm.aliasing_ppgtt)
>    return;
>

I think we need to keep the enable check here, because this can be called
from within i915_reset as well.

To fix this and prevent clash between i915_gem_init_ppgtt and
i915_gem_init_ppgtt, I guess you could add the 'i915_enable_ppgtt && '
check to the i915_gem_init_ppgtt call in Patch3 as well.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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[PATCH] drm/i915: enable ppgtt

[Daniel Vetter]

We want to unconditionally enable ppgtt for two reasons:
- Windows uses this on snb and later.
- We need the basic hw support to work before we can think about real
  per-process address spaces and other cool features we want.

But Chris Wilson was complaining all over irc and intel-gfx that this
will blow up if we don't have a module option to disable it. Hence add
one, to prevent this.

ppgtt support seems to slightly change the timings and make crashy
things slightly more or less crashy. Now in my testing and the testing
this got on troublesome snb machines, it seems to have improved things
only. But on ivb it makes quite a few crashes happen much more often,
see

https://bugs.freedesktop.org/show_bug.cgi?id=41353

Luckily Eugeni Dodonov seems to have a set of workarounds that fix
this issue.

v2: Don't try to enable ppgtt on pre-snb.

v3: Pimp commit message and make Chris Wilson less grumpy by adding a
module option.

v4: New try at making Chris Wilson happy.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_dma.c |    2 +-
 drivers/gpu/drm/i915/i915_drv.c |    7 +++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 drivers/gpu/drm/i915/i915_gem.c |   39 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1186032..38dfcf9 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1196,7 +1196,7 @@ static int i915_load_gem_init(struct drm_device *dev)
 	/* Basic memrange allocator for stolen space */
 	drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 
-	if (HAS_ALIASING_PPGTT(dev)) {
+	if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) {
 		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
 		 * aperture accordingly when using aliasing ppgtt. */
 		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1537d46..891b862 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -103,6 +103,11 @@ MODULE_PARM_DESC(enable_hangcheck,
 		"WARNING: Disabling this can cause system wide hangs. "
 		"(default: true)");
 
+bool i915_enable_ppgtt __read_mostly = 1;
+module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
+MODULE_PARM_DESC(i915_enable_ppgtt,
+		"Enable PPGTT (default: true)");
+
 static struct drm_driver driver;
 extern int intel_agp_enabled;
 
@@ -702,6 +707,8 @@ int i915_reset(struct drm_device *dev, u8 flags)
 		if (HAS_BLT(dev))
 		    dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 
+		i915_gem_init_ppgtt(dev);
+
 		mutex_unlock(&dev->struct_mutex);
 		drm_irq_uninstall(dev);
 		drm_mode_config_reset(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14b8e1f..60a2f53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1045,6 +1045,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly;
 extern int i915_enable_rc6 __read_mostly;
 extern int i915_enable_fbc __read_mostly;
 extern bool i915_enable_hangcheck __read_mostly;
+extern bool i915_enable_ppgtt __read_mostly;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
@@ -1224,6 +1225,7 @@ int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
 void i915_gem_init_swizzling(struct drm_device *dev);
+void i915_gem_init_ppgtt(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 void i915_gem_do_init(struct drm_device *dev,
 		      unsigned long start,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 23c6bf1..10a4ae6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3713,6 +3713,43 @@ void i915_gem_init_swizzling(struct drm_device *dev)
 	else
 		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 }
+
+void i915_gem_init_ppgtt(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t pd_offset;
+	struct intel_ring_buffer *ring;
+	int i;
+
+	if (!dev_priv->mm.aliasing_ppgtt)
+		return;
+
+	pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset;
+	pd_offset /= 64; /* in cachelines, */
+	pd_offset <<= 16;
+
+	if (INTEL_INFO(dev)->gen == 6) {
+		uint32_t ecochk = I915_READ(GAM_ECOCHK);
+		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
+				       ECOCHK_PPGTT_CACHE64B);
+		I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
+	} else if (INTEL_INFO(dev)->gen >= 7) {
+		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
+		/* GFX_MODE is per-ring on gen7+ */
+	}
+
+	for (i = 0; i < I915_NUM_RINGS; i++) {
+		ring = &dev_priv->ring[i];
+
+		if (INTEL_INFO(dev)->gen >= 7)
+			I915_WRITE(RING_MODE_GEN7(ring),
+				   GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
+
+		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
+	}
+}
+
 int
 i915_gem_init_hw(struct drm_device *dev)
 {
@@ -3739,6 +3776,8 @@ i915_gem_init_hw(struct drm_device *dev)
 
 	dev_priv->next_seqno = 1;
 
+	i915_gem_init_ppgtt(dev);
+
 	return 0;
 
 cleanup_bsd_ring:
-- 
1.7.8.2

Re: Television turns greenish after stand-by

[Angela Schmid]

Hello

I have Linux 3.3-rc2 with daniels interlace patches. When the television turns off (dpms) and after turning on, the blacks are
green. This is highly reproducable, however I don't know exactly which conditions have to exist.
Restarting X, putting television once again to stand-by and turning on does not work. I have to shut down the television for a
while.

Is it a television problem or eventually produced by the driver ?
Any help appreciated.

Angela

Re: Television turns greenish after stand-by

[John Obaterspok]

Hello,

Isn't this the same thing as:
- https://bugs.freedesktop.org/show_bug.cgi?id=33760
- https://bugzilla.kernel.org/show_bug.cgi?id=25732
- https://bugs.freedesktop.org/show_bug.cgi?id=42795

Didn't you experience this problem with earlier kernels?

I get away with the green colors if I lower the resolution. If I up
the resolution again to 1080p I get the green tint back. Once rebooted
the 1080p has correct colors.

-- John

2012/2/10 Angela Schmid <angela.schmid@wolke7.net>:
> Hello
>
> I have Linux 3.3-rc2 with daniels interlace patches. When the television turns off (dpms) and after turning on, the blacks are
> green. This is highly reproducable, however I don't know exactly which conditions have to exist.
> Restarting X, putting television once again to stand-by and turning on does not work. I have to shut down the television for a
> while.
>
> Is it a television problem or eventually produced by the driver ?
> Any help appreciated.
>
> Angela
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: Television turns greenish after stand-by

[Daniel Vetter]

On Fri, Feb 10, 2012 at 08:27:27AM +0100, Angela Schmid wrote:
> Hello
> 
> I have Linux 3.3-rc2 with daniels interlace patches. When the television turns off (dpms) and after turning on, the blacks are
> green. This is highly reproducable, however I don't know exactly which conditions have to exist.
> Restarting X, putting television once again to stand-by and turning on does not work. I have to shut down the television for a
> while.
> 
> Is it a television problem or eventually produced by the driver ?
> Any help appreciated.

Driver is the likely culprit. Can you enable 1080i output, check that it
works and grab the output of intel_reg_dumper from intel-gpu-tools. Then
please do whatever dance is required to break it, and again grab the
output of intel_reg_dumper. Hopefully there's some funky register we've
forgotten to set up again correctly.

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: Television turns greenish after stand-by

[Angela Schmid]

Hello Daniel

There is no difference with intel_reg_dumper. I took a probe during correct display (1080i), after 2 days, when I moved the
television out of stand-by (display is green) and after a shutdown/start during a correct display. See below.

Also dmesg at start and when coming out of stand-by is the same.


I have seen messages from Paulo Zanoni:
[Intel-gfx] [PATCH 1/2] drm/i915: set interlaced bits for TRANSCONF
Are they eventually needed in my case ? Could you incorporate these in your git interlace tree or otherwise tell me where to find
them.
As I reread the messages, there seem to be occasions that when HDMI is only connected the display can't come up correct. I have also
only HDMI connected, but never have seen any misbehavior, it comes up in 1080i.

What can I do to isolate the problem.

Angela

[    9.527763] HDMI hot plug event: Codec=3 Pin=7 Presence_Detect=1 ELD_Valid=1
[    9.527845] HDMI status: Codec=3 Pin=7 Presence_Detect=1 ELD_Valid=1
[    9.527885] HDMI status: Codec=3 Pin=7 Presence_Detect=1 ELD_Valid=1
[    9.534461] HDMI: detected monitor Philips FTV at connection type HDMI
[    9.534462] HDMI: available speakers: FL/FR
[    9.534464] HDMI: supports coding type LPCM: channels = 2, rates = 32000 44100 48000 96000 176400, bits = 16 20 24
[    9.534466] HDMI: supports coding type AC-3: channels = 6, rates = 32000 44100 48000, max bitrate = 640000
[    9.534468] HDMI: supports coding type MPEG1: channels = 2, rates = 32000 44100 48000, max bitrate = 1072000

[374280.746752] HDMI hot plug event: Codec=3 Pin=7 Presence_Detect=1 ELD_Valid=1
[374280.746799] HDMI status: Codec=3 Pin=7 Presence_Detect=1 ELD_Valid=1
[374280.750481] HDMI: detected monitor Philips FTV at connection type HDMI
[374280.750483] HDMI: available speakers: FL/FR
[374280.750486] HDMI: supports coding type LPCM: channels = 2, rates = 32000 44100 48000 96000 176400, bits = 16 20 24
[374280.750489] HDMI: supports coding type AC-3: channels = 6, rates = 32000 44100 48000, max bitrate = 640000
[374280.750491] HDMI: supports coding type MPEG1: channels = 2, rates = 32000 44100 48000, max bitrate = 1072000

                    PGETBL_CTL: 0x00000000
               GEN6_INSTDONE_1: 0xfffffffe
               GEN6_INSTDONE_2: 0xffffffff
                  CPU_VGACNTRL: 0x80000000 (disabled)
    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
                     RR_HW_CTL: 0x00000000 (low 0, high 0)
                FDI_PLL_BIOS_0: 0xffffffff
                FDI_PLL_BIOS_1: 0xffffffff
                FDI_PLL_BIOS_2: 0xffffffff
       DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
       DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
       DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
              FDI_PLL_FREQ_CTL: 0xffffffff
                     PIPEACONF: 0xc0600000 (enabled, active, 8bpc)
                      HTOTAL_A: 0x0a4f077f (1920 active, 2640 total)
                      HBLANK_A: 0x0a4f077f (1920 start, 2640 end)
                       HSYNC_A: 0x09bb098f (2448 start, 2492 end)
                      VTOTAL_A: 0x04630437 (1080 active, 1124 total)
                      VBLANK_A: 0x04630437 (1080 start, 1124 end)
                       VSYNC_A: 0x0445043b (1084 start, 1094 end)
                  VSYNCSHIFT_A: 0x00000468
                      PIPEASRC: 0x077f0437 (1920, 1080)
                 PIPEA_DATA_M1: 0x7e1b30f0 (TU 64, val 0x1b30f0 1782000)
                 PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
                 PIPEA_LINK_M1: 0x0001220a (val 0x1220a 74250)
                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
                      DSPACNTR: 0xd8004400 (enabled)
                      DSPABASE: 0x00000000
                    DSPASTRIDE: 0x00001e00 (120)
                      DSPASURF: 0x0084d000
                   DSPATILEOFF: 0x00000000 (0, 0)
                     PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
                      HTOTAL_B: 0x00000000 (1 active, 1 total)
                      HBLANK_B: 0x00000000 (1 start, 1 end)
                       HSYNC_B: 0x00000000 (1 start, 1 end)
                      VTOTAL_B: 0x00000000 (1 active, 1 total)
                      VBLANK_B: 0x00000000 (1 start, 1 end)
                       VSYNC_B: 0x00000000 (1 start, 1 end)
                  VSYNCSHIFT_B: 0x00000000
                      DSPBCNTR: 0x00004000 (disabled)
                      DSPBBASE: 0x00000000
                    DSPBSTRIDE: 0x00000000 (0)
                      DSPBSURF: 0x00000000
                   DSPBTILEOFF: 0x00000000 (0, 0)
                      PIPEBSRC: 0x00000000 (1, 1)
                 PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
                 PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
                 PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
                 PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least,
filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
                     PFA_CTL_2: 0x00007ef2 (vscale 0.991760)
                     PFA_CTL_3: 0x00003f79 (vscale initial phase 0.495880)
                     PFA_CTL_4: 0x00007c40 (hscale 0.970703)
                   PFA_WIN_POS: 0x00000000 (0, 0)
                  PFA_WIN_SIZE: 0x00000000 (0, 0)
                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least,
filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
                     PFB_CTL_2: 0x00000000 (vscale 0.000000)
                     PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
                     PFB_CTL_4: 0x00000000 (hscale 0.000000)
                   PFB_WIN_POS: 0x00000000 (0, 0)
                  PFB_WIN_SIZE: 0x00000000 (0, 0)
              PCH_DREF_CONTROL: 0x00000400 (cpu source disable, ssc_source disable, nonspread_source enable, superspread_source
disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
              PCH_DPLL_TMR_CFG: 0x0271186a
                PCH_SSC4_PARMS: 0x01204860
            PCH_SSC4_AUX_PARMS: 0x000029c5
                  PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
           PCH_DPLL_ANALOG_CTL: 0x00008000
                    PCH_DPLL_A: 0xc4080008 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 4, FPA1 P1 4, refclk
default 120Mhz, sdvo/hdmi mul 1)
                    PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk
default 120Mhz, sdvo/hdmi mul 1)
                      PCH_FPA0: 0x00021007 (n = 2, m1 = 16, m2 = 7)
                      PCH_FPA1: 0x00021007 (n = 2, m1 = 16, m2 = 7)
                      PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
                      PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
                TRANS_HTOTAL_A: 0x0a4f077f (1920 active, 2640 total)
                TRANS_HBLANK_A: 0x0a4f077f (1920 start, 2640 end)
                 TRANS_HSYNC_A: 0x09bb098f (2448 start, 2492 end)
                TRANS_VTOTAL_A: 0x04630437 (1080 active, 1124 total)
                TRANS_VBLANK_A: 0x04630437 (1080 start, 1124 end)
                 TRANS_VSYNC_A: 0x0445043b (1084 start, 1094 end)
                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
                TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
                TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
                 TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
                TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
                TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
                 TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
                TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
                    TRANSACONF: 0xc0600000 (enable, active)
                    TRANSBCONF: 0x00000000 (disable, inactive)
                    TRANSCCONF: 0x00000000 (disable, inactive)
                   FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X1,
enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
                   FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1,
enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1,
enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
                   FDI_RXA_CTL: 0x80002350 (enable, train pattern not train, port width X1, 8bpc,link_reverse_strap_overwrite no,
dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable,
enhanced framing enable, PCDClk)
                   FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no,
dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable,
enhanced framing enable, RawClk)
                   FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no,
dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable,
enhanced framing enable, RawClk)
                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
                  FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
               FDI_RXA_TUSIZE1: 0x7e000000
               FDI_RXA_TUSIZE2: 0x7e000000
               FDI_RXB_TUSIZE1: 0x7e000000
               FDI_RXB_TUSIZE2: 0x7e000000
               FDI_RXC_TUSIZE1: 0x7e000000
               FDI_RXC_TUSIZE2: 0x7e000000
                 FDI_PLL_CTL_1: 0x7e000000
                 FDI_PLL_CTL_2: 0x7e000000
                   FDI_RXA_IIR: 0x00000000
                   FDI_RXA_IMR: 0x000008ff
                   FDI_RXB_IIR: 0x00000000
                   FDI_RXB_IMR: 0x000008ff
                      PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
                         HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
                         HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
                         HDMID: 0x80000adc (enabled pipe A 8bpc TMDS HDMI audio enabled +vsync +hsync detected)
                      PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                     CPU_eDP_A: 0x00000018
                      PCH_DP_B: 0x00000004
                      PCH_DP_C: 0x00000004
                      PCH_DP_D: 0x00000004
                TRANS_DP_CTL_A: 0x60000018 (disable port none 8bpc +vsync +hsync)
                TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
                TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
              BLC_PWM_CPU_CTL2: 0x00000000
               BLC_PWM_CPU_CTL: 0x00000000
              BLC_PWM_PCH_CTL1: 0x00000000
              BLC_PWM_PCH_CTL2: 0x00000000
                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
                PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off)
              PCH_PP_ON_DELAYS: 0x00000000
             PCH_PP_OFF_DELAYS: 0x00000000
                PCH_PP_DIVISOR: 0x00186904


> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: 10 February 2012 16:45
> To: Angela Schmid
> Cc: 'Intel Graphics Development'; 'Daniel Vetter'
> Subject: Re: [Intel-gfx] Television turns greenish after stand-by
> 
> On Fri, Feb 10, 2012 at 08:27:27AM +0100, Angela Schmid wrote:
> > Hello
> >
> > I have Linux 3.3-rc2 with daniels interlace patches. When the television turns off (dpms) and after turning
> on, the blacks are
> > green. This is highly reproducable, however I don't know exactly which conditions have to exist.
> > Restarting X, putting television once again to stand-by and turning on does not work. I have to shut down the
> television for a
> > while.
> >
> > Is it a television problem or eventually produced by the driver ?
> > Any help appreciated.
> 
> Driver is the likely culprit. Can you enable 1080i output, check that it
> works and grab the output of intel_reg_dumper from intel-gpu-tools. Then
> please do whatever dance is required to break it, and again grab the
> output of intel_reg_dumper. Hopefully there's some funky register we've
> forgotten to set up again correctly.
> 
> Yours, Daniel
> --
> Daniel Vetter
> Mail: daniel@ffwll.ch
> Mobile: +41 (0)79 365 57 48

Re: Television turns greenish after stand-by

[Daniel Vetter]

On Mon, Feb 13, 2012 at 08:33:22AM +0100, Angela Schmid wrote:
> There is no difference with intel_reg_dumper. I took a probe during correct display (1080i), after 2 days, when I moved the
> television out of stand-by (display is green) and after a shutdown/start during a correct display. See below.
> 
> Also dmesg at start and when coming out of stand-by is the same.
> 
> 
> I have seen messages from Paulo Zanoni:
> [Intel-gfx] [PATCH 1/2] drm/i915: set interlaced bits for TRANSCONF
> Are they eventually needed in my case ? Could you incorporate these in your git interlace tree or otherwise tell me where to find
> them.

All interlaced patches including the TRANSCONF patch from Paulo have been
merged to drm-intel-next-queued in my official drm-intel repo at:

http://cgit.freedesktop.org/~danvet/drm-intel/

> As I reread the messages, there seem to be occasions that when HDMI is only connected the display can't come up correct. I have also
> only HDMI connected, but never have seen any misbehavior, it comes up in 1080i.

Iirc that issue was only when the BIOS has set up the output in interlaced
mode and the kernel tried to use progressive, but failed to correctly
clear all interlaced bits. The patch to fix this is also merged (and on
track to get merged to 3.3 as a bugfix).

> What can I do to isolate the problem.

I don't have an idea right away. Can you please file a bug report on
bugs.freedeskopt.org so that we don't lose sight of this issue here?

Thanks, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: Television turns greenish after stand-by

[Angela Schmid]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: 13 February 2012 09:32
> 
> All interlaced patches including the TRANSCONF patch from Paulo have been
> merged to drm-intel-next-queued in my official drm-intel repo at:
> 
> http://cgit.freedesktop.org/~danvet/drm-intel/
> 

Hello Daniel

I can't fetch from the repository.

git remote -v
daniel  git://people.freedesktop.org/~danvet/drm (fetch)
daniel  git://people.freedesktop.org/~danvet/drm (push)
drm-intel       http://cgit.freedesktop.org/~danvet/drm-intel (fetch)
drm-intel       http://cgit.freedesktop.org/~danvet/drm-intel (push)
origin  git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git (fetch)
origin  git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git (push)

git fetch drm-intel
error: Unable to find 396ee23db6b76354e487fd2cfdacbd989442f81d under http://cgit.freedesktop.org/~danvet/drm-intel
Cannot obtain needed object 396ee23db6b76354e487fd2cfdacbd989442f81d
error: Fetch failed.

And with
git clone http://cgit.freedesktop.org/~danvet/drm-intel
Cloning into drm-intel...
warning: remote HEAD refers to nonexistent ref, unable to checkout.

What is wrong ?

Angela

Re: Television turns greenish after stand-by

[Daniel Vetter]

On Tue, Feb 14, 2012 at 08:09:45AM +0100, Angela Schmid wrote:
> > -----Original Message-----
> > From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> > Sent: 13 February 2012 09:32
> > 
> > All interlaced patches including the TRANSCONF patch from Paulo have been
> > merged to drm-intel-next-queued in my official drm-intel repo at:
> > 
> > http://cgit.freedesktop.org/~danvet/drm-intel/
> > 
> 
> Hello Daniel
> 
> I can't fetch from the repository.
> 
> git remote -v
> daniel  git://people.freedesktop.org/~danvet/drm (fetch)
> daniel  git://people.freedesktop.org/~danvet/drm (push)
> drm-intel       http://cgit.freedesktop.org/~danvet/drm-intel (fetch)
> drm-intel       http://cgit.freedesktop.org/~danvet/drm-intel (push)
> origin  git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git (fetch)
> origin  git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git (push)

Oops, that's just the link to the cgit webinterface to my drm-intel repo. The
git path is

git://people.freedesktop.org/~danvet/drm-intel

Cheers, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 0/7] updated ppgtt patches

[Chris Wilson]

On Thu,  9 Feb 2012 17:15:43 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Hi all,
> 
> I've rebased and updated my ppgtt patches. Only changes are somewhat improved
> commit messages (especially for the final patch that actually enables ppgtt) and
> an added module option in the last patch to please Chris.
> 
> Assuming nothing pops up I plan to merge this in 1-2 days.
> 
> Cheers, Daniel
> 
> Daniel Vetter (7):
>   agp/intel-gtt: export the scratch page dma address
>   agp/intel-gtt: export the gtt pagetable iomapping
>   drm/i915: initialization/teardown for the aliasing ppgtt
>   drm/i915: ppgtt binding/unbinding support
>   drm/i915: ppgtt register definitions
>   drm/i915: ppgtt debugfs info
>   drm/i915: enable ppgtt

Other than the new module option which does not really affect the series
that much, I've been using these for a few months on snb and non-snb
machines.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 0/7] updated ppgtt patches

[Eugeni Dodonov]

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On Thu, Feb 9, 2012 at 14:15, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> Hi all,
>
> I've rebased and updated my ppgtt patches. Only changes are somewhat
> improved
> commit messages (especially for the final patch that actually enables
> ppgtt) and
> an added module option in the last patch to please Chris.
>
> Assuming nothing pops up I plan to merge this in 1-2 days.
>
> Cheers, Daniel
>
> Daniel Vetter (7):
>  agp/intel-gtt: export the scratch page dma address
>  agp/intel-gtt: export the gtt pagetable iomapping
>  drm/i915: initialization/teardown for the aliasing ppgtt
>  drm/i915: ppgtt binding/unbinding support
>  drm/i915: ppgtt register definitions
>  drm/i915: ppgtt debugfs info
>  drm/i915: enable ppgtt
>

I was under impression that I've sent a r-b for the series some time ago,
but perhaps it got missing in action. I have a small suggestion for the
module parameter patch (Patch7), but other than that, for the series:
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com<eugeni.dodonov@gmail.com>
>

Also, I was using this pretty extensively for the past few months, on
different SNB and IVB machines, so you can add the:
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

as well.

-- 
Eugeni Dodonov
 <http://eugeni.dodonov.net/>

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Re: [PATCH 0/7] updated ppgtt patches

[Daniel Vetter]

On Thu, Feb 09, 2012 at 04:21:31PM -0200, Eugeni Dodonov wrote:
> On Thu, Feb 9, 2012 at 14:15, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > Hi all,
> >
> > I've rebased and updated my ppgtt patches. Only changes are somewhat
> > improved
> > commit messages (especially for the final patch that actually enables
> > ppgtt) and
> > an added module option in the last patch to please Chris.
> >
> > Assuming nothing pops up I plan to merge this in 1-2 days.
> >
> > Cheers, Daniel
> >
> > Daniel Vetter (7):
> >  agp/intel-gtt: export the scratch page dma address
> >  agp/intel-gtt: export the gtt pagetable iomapping
> >  drm/i915: initialization/teardown for the aliasing ppgtt
> >  drm/i915: ppgtt binding/unbinding support
> >  drm/i915: ppgtt register definitions
> >  drm/i915: ppgtt debugfs info
> >  drm/i915: enable ppgtt
> >
> 
> I was under impression that I've sent a r-b for the series some time ago,
> but perhaps it got missing in action. I have a small suggestion for the
> module parameter patch (Patch7), but other than that, for the series:
> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com<eugeni.dodonov@gmail.com>
> >
> 
> Also, I was using this pretty extensively for the past few months, on
> different SNB and IVB machines, so you can add the:
> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Slurped this in with v4 for the last patch, thanks for the review and
testing.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48