[PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Jouni Högander]

We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
since we started configuring LFPS sending. According to Bspec Configuring
LFPS sending is needed only when using AUXLess ALPM. This patch avoids
these failures by configuring LFPS sending only when using AUXLess ALPM.

Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ed8e640b96b0..9cfc3187aeab 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
-	bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
-						  crtc_state);
+	u8 owned_lane_mask;
 	int i;
 
-	if (DISPLAY_VER(display) < 20)
+	if (DISPLAY_VER(display) < 20 ||
+	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
 		return;
 
+	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
 		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
@@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 
 		intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
 			      CONTROL0_MAC_TRANSMIT_LFPS,
-			      enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
-			      MB_WRITE_COMMITTED);
+			      CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
 	}
 }
 
-- 
2.43.0

✓ CI.KUnit: success for drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Patchwork]

== Series Details ==

Series: drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM
URL   : https://patchwork.freedesktop.org/series/151739/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:14:26] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:14:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:15:04] Starting KUnit Kernel (1/1)...
[07:15:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:15:05] ================== guc_buf (11 subtests) ===================
[07:15:05] [PASSED] test_smallest
[07:15:05] [PASSED] test_largest
[07:15:05] [PASSED] test_granular
[07:15:05] [PASSED] test_unique
[07:15:05] [PASSED] test_overlap
[07:15:05] [PASSED] test_reusable
[07:15:05] [PASSED] test_too_big
[07:15:05] [PASSED] test_flush
[07:15:05] [PASSED] test_lookup
[07:15:05] [PASSED] test_data
[07:15:05] [PASSED] test_class
[07:15:05] ===================== [PASSED] guc_buf =====================
[07:15:05] =================== guc_dbm (7 subtests) ===================
[07:15:05] [PASSED] test_empty
[07:15:05] [PASSED] test_default
[07:15:05] ======================== test_size  ========================
[07:15:05] [PASSED] 4
[07:15:05] [PASSED] 8
[07:15:05] [PASSED] 32
[07:15:05] [PASSED] 256
[07:15:05] ==================== [PASSED] test_size ====================
[07:15:05] ======================= test_reuse  ========================
[07:15:05] [PASSED] 4
[07:15:05] [PASSED] 8
[07:15:05] [PASSED] 32
[07:15:05] [PASSED] 256
[07:15:05] =================== [PASSED] test_reuse ====================
[07:15:05] =================== test_range_overlap  ====================
[07:15:05] [PASSED] 4
[07:15:05] [PASSED] 8
[07:15:05] [PASSED] 32
[07:15:05] [PASSED] 256
[07:15:05] =============== [PASSED] test_range_overlap ================
[07:15:05] =================== test_range_compact  ====================
[07:15:05] [PASSED] 4
[07:15:05] [PASSED] 8
[07:15:05] [PASSED] 32
[07:15:05] [PASSED] 256
[07:15:05] =============== [PASSED] test_range_compact ================
[07:15:05] ==================== test_range_spare  =====================
[07:15:05] [PASSED] 4
[07:15:05] [PASSED] 8
[07:15:05] [PASSED] 32
[07:15:05] [PASSED] 256
[07:15:05] ================ [PASSED] test_range_spare =================
[07:15:05] ===================== [PASSED] guc_dbm =====================
[07:15:05] =================== guc_idm (6 subtests) ===================
[07:15:05] [PASSED] bad_init
[07:15:05] [PASSED] no_init
[07:15:05] [PASSED] init_fini
[07:15:05] [PASSED] check_used
[07:15:05] [PASSED] check_quota
[07:15:05] [PASSED] check_all
[07:15:05] ===================== [PASSED] guc_idm =====================
[07:15:05] ================== no_relay (3 subtests) ===================
[07:15:05] [PASSED] xe_drops_guc2pf_if_not_ready
[07:15:05] [PASSED] xe_drops_guc2vf_if_not_ready
[07:15:05] [PASSED] xe_rejects_send_if_not_ready
[07:15:05] ==================== [PASSED] no_relay =====================
[07:15:05] ================== pf_relay (14 subtests) ==================
[07:15:05] [PASSED] pf_rejects_guc2pf_too_short
[07:15:05] [PASSED] pf_rejects_guc2pf_too_long
[07:15:05] [PASSED] pf_rejects_guc2pf_no_payload
[07:15:05] [PASSED] pf_fails_no_payload
[07:15:05] [PASSED] pf_fails_bad_origin
[07:15:05] [PASSED] pf_fails_bad_type
[07:15:05] [PASSED] pf_txn_reports_error
[07:15:05] [PASSED] pf_txn_sends_pf2guc
[07:15:05] [PASSED] pf_sends_pf2guc
[07:15:05] [SKIPPED] pf_loopback_nop
[07:15:05] [SKIPPED] pf_loopback_echo
[07:15:05] [SKIPPED] pf_loopback_fail
[07:15:05] [SKIPPED] pf_loopback_busy
[07:15:05] [SKIPPED] pf_loopback_retry
[07:15:05] ==================== [PASSED] pf_relay =====================
[07:15:05] ================== vf_relay (3 subtests) ===================
[07:15:05] [PASSED] vf_rejects_guc2vf_too_short
[07:15:05] [PASSED] vf_rejects_guc2vf_too_long
[07:15:05] [PASSED] vf_rejects_guc2vf_no_payload
[07:15:05] ==================== [PASSED] vf_relay =====================
[07:15:05] ===================== lmtt (1 subtest) =====================
[07:15:05] ======================== test_ops  =========================
[07:15:05] [PASSED] 2-level
[07:15:05] [PASSED] multi-level
[07:15:05] ==================== [PASSED] test_ops =====================
[07:15:05] ====================== [PASSED] lmtt =======================
[07:15:05] ================= pf_service (11 subtests) =================
[07:15:05] [PASSED] pf_negotiate_any
[07:15:05] [PASSED] pf_negotiate_base_match
[07:15:05] [PASSED] pf_negotiate_base_newer
[07:15:05] [PASSED] pf_negotiate_base_next
[07:15:05] [SKIPPED] pf_negotiate_base_older
[07:15:05] [PASSED] pf_negotiate_base_prev
[07:15:05] [PASSED] pf_negotiate_latest_match
[07:15:05] [PASSED] pf_negotiate_latest_newer
[07:15:05] [PASSED] pf_negotiate_latest_next
[07:15:05] [SKIPPED] pf_negotiate_latest_older
[07:15:05] [SKIPPED] pf_negotiate_latest_prev
[07:15:05] =================== [PASSED] pf_service ====================
[07:15:05] =================== xe_mocs (2 subtests) ===================
[07:15:05] ================ xe_live_mocs_kernel_kunit  ================
[07:15:05] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:15:05] ================ xe_live_mocs_reset_kunit  =================
[07:15:05] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:15:05] ==================== [SKIPPED] xe_mocs =====================
[07:15:05] ================= xe_migrate (2 subtests) ==================
[07:15:05] ================= xe_migrate_sanity_kunit  =================
[07:15:05] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:15:05] ================== xe_validate_ccs_kunit  ==================
[07:15:05] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:15:05] =================== [SKIPPED] xe_migrate ===================
[07:15:05] ================== xe_dma_buf (1 subtest) ==================
[07:15:05] ==================== xe_dma_buf_kunit  =====================
[07:15:05] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:15:05] =================== [SKIPPED] xe_dma_buf ===================
[07:15:05] ================= xe_bo_shrink (1 subtest) =================
[07:15:05] =================== xe_bo_shrink_kunit  ====================
[07:15:05] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:15:05] ================== [SKIPPED] xe_bo_shrink ==================
[07:15:05] ==================== xe_bo (2 subtests) ====================
[07:15:05] ================== xe_ccs_migrate_kunit  ===================
[07:15:05] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:15:05] ==================== xe_bo_evict_kunit  ====================
[07:15:05] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:15:05] ===================== [SKIPPED] xe_bo ======================
[07:15:05] ==================== args (11 subtests) ====================
[07:15:05] [PASSED] count_args_test
[07:15:05] [PASSED] call_args_example
[07:15:05] [PASSED] call_args_test
[07:15:05] [PASSED] drop_first_arg_example
[07:15:05] [PASSED] drop_first_arg_test
[07:15:05] [PASSED] first_arg_example
[07:15:05] [PASSED] first_arg_test
[07:15:05] [PASSED] last_arg_example
[07:15:05] [PASSED] last_arg_test
[07:15:05] [PASSED] pick_arg_example
[07:15:05] [PASSED] sep_comma_example
[07:15:05] ====================== [PASSED] args =======================
[07:15:05] =================== xe_pci (3 subtests) ====================
[07:15:05] ==================== check_graphics_ip  ====================
[07:15:05] [PASSED] 12.70 Xe_LPG
[07:15:05] [PASSED] 12.71 Xe_LPG
[07:15:05] [PASSED] 12.74 Xe_LPG+
[07:15:05] [PASSED] 20.01 Xe2_HPG
[07:15:05] [PASSED] 20.02 Xe2_HPG
[07:15:05] [PASSED] 20.04 Xe2_LPG
[07:15:05] [PASSED] 30.00 Xe3_LPG
[07:15:05] [PASSED] 30.01 Xe3_LPG
[07:15:05] [PASSED] 30.03 Xe3_LPG
[07:15:05] ================ [PASSED] check_graphics_ip ================
[07:15:05] ===================== check_media_ip  ======================
[07:15:05] [PASSED] 13.00 Xe_LPM+
[07:15:05] [PASSED] 13.01 Xe2_HPM
[07:15:05] [PASSED] 20.00 Xe2_LPM
[07:15:05] [PASSED] 30.00 Xe3_LPM
[07:15:05] [PASSED] 30.02 Xe3_LPM
[07:15:05] ================= [PASSED] check_media_ip ==================
[07:15:05] ================= check_platform_gt_count  =================
[07:15:05] [PASSED] 0x9A60 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A68 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A70 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A40 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A49 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A59 (TIGERLAKE)
[07:15:05] [PASSED] 0x9A78 (TIGERLAKE)
[07:15:05] [PASSED] 0x9AC0 (TIGERLAKE)
[07:15:05] [PASSED] 0x9AC9 (TIGERLAKE)
[07:15:05] [PASSED] 0x9AD9 (TIGERLAKE)
[07:15:05] [PASSED] 0x9AF8 (TIGERLAKE)
[07:15:05] [PASSED] 0x4C80 (ROCKETLAKE)
[07:15:05] [PASSED] 0x4C8A (ROCKETLAKE)
[07:15:05] [PASSED] 0x4C8B (ROCKETLAKE)
[07:15:05] [PASSED] 0x4C8C (ROCKETLAKE)
[07:15:05] [PASSED] 0x4C90 (ROCKETLAKE)
[07:15:05] [PASSED] 0x4C9A (ROCKETLAKE)
[07:15:05] [PASSED] 0x4680 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4682 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4688 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x468A (ALDERLAKE_S)
[07:15:05] [PASSED] 0x468B (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4690 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4692 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4693 (ALDERLAKE_S)
[07:15:05] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46AA (ALDERLAKE_P)
[07:15:05] [PASSED] 0x462A (ALDERLAKE_P)
[07:15:05] [PASSED] 0x4626 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x4628 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:15:05] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:15:05] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:15:05] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:15:05] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:15:05] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:15:05] [PASSED] 0xA721 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA720 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:15:05] [PASSED] 0xA780 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA781 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA782 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA783 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA788 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA789 (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA78A (ALDERLAKE_S)
[07:15:05] [PASSED] 0xA78B (ALDERLAKE_S)
[07:15:05] [PASSED] 0x4905 (DG1)
[07:15:05] [PASSED] 0x4906 (DG1)
[07:15:05] [PASSED] 0x4907 (DG1)
[07:15:05] [PASSED] 0x4908 (DG1)
[07:15:05] [PASSED] 0x4909 (DG1)
[07:15:05] [PASSED] 0x56C0 (DG2)
[07:15:05] [PASSED] 0x56C2 (DG2)
[07:15:05] [PASSED] 0x56C1 (DG2)
[07:15:05] [PASSED] 0x7D51 (METEORLAKE)
[07:15:05] [PASSED] 0x7DD1 (METEORLAKE)
[07:15:05] [PASSED] 0x7D41 (METEORLAKE)
[07:15:05] [PASSED] 0x7D67 (METEORLAKE)
[07:15:05] [PASSED] 0xB640 (METEORLAKE)
[07:15:05] [PASSED] 0x56A0 (DG2)
[07:15:05] [PASSED] 0x56A1 (DG2)
[07:15:05] [PASSED] 0x56A2 (DG2)
[07:15:05] [PASSED] 0x56BE (DG2)
[07:15:05] [PASSED] 0x56BF (DG2)
[07:15:05] [PASSED] 0x5690 (DG2)
[07:15:05] [PASSED] 0x5691 (DG2)
[07:15:05] [PASSED] 0x5692 (DG2)
[07:15:05] [PASSED] 0x56A5 (DG2)
[07:15:05] [PASSED] 0x56A6 (DG2)
[07:15:05] [PASSED] 0x56B0 (DG2)
[07:15:05] [PASSED] 0x56B1 (DG2)
[07:15:05] [PASSED] 0x56BA (DG2)
[07:15:05] [PASSED] 0x56BB (DG2)
[07:15:05] [PASSED] 0x56BC (DG2)
[07:15:05] [PASSED] 0x56BD (DG2)
[07:15:05] [PASSED] 0x5693 (DG2)
[07:15:05] [PASSED] 0x5694 (DG2)
[07:15:05] [PASSED] 0x5695 (DG2)
[07:15:05] [PASSED] 0x56A3 (DG2)
[07:15:05] [PASSED] 0x56A4 (DG2)
[07:15:05] [PASSED] 0x56B2 (DG2)
[07:15:05] [PASSED] 0x56B3 (DG2)
[07:15:05] [PASSED] 0x5696 (DG2)
[07:15:05] [PASSED] 0x5697 (DG2)
[07:15:05] [PASSED] 0xB69 (PVC)
[07:15:05] [PASSED] 0xB6E (PVC)
[07:15:05] [PASSED] 0xBD4 (PVC)
[07:15:05] [PASSED] 0xBD5 (PVC)
[07:15:05] [PASSED] 0xBD6 (PVC)
[07:15:05] [PASSED] 0xBD7 (PVC)
[07:15:05] [PASSED] 0xBD8 (PVC)
[07:15:05] [PASSED] 0xBD9 (PVC)
[07:15:05] [PASSED] 0xBDA (PVC)
[07:15:05] [PASSED] 0xBDB (PVC)
[07:15:05] [PASSED] 0xBE0 (PVC)
[07:15:05] [PASSED] 0xBE1 (PVC)
[07:15:05] [PASSED] 0xBE5 (PVC)
[07:15:05] [PASSED] 0x7D40 (METEORLAKE)
[07:15:05] [PASSED] 0x7D45 (METEORLAKE)
[07:15:05] [PASSED] 0x7D55 (METEORLAKE)
[07:15:05] [PASSED] 0x7D60 (METEORLAKE)
[07:15:05] [PASSED] 0x7DD5 (METEORLAKE)
[07:15:05] [PASSED] 0x6420 (LUNARLAKE)
[07:15:05] [PASSED] 0x64A0 (LUNARLAKE)
[07:15:05] [PASSED] 0x64B0 (LUNARLAKE)
[07:15:05] [PASSED] 0xE202 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE209 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE20B (BATTLEMAGE)
[07:15:05] [PASSED] 0xE20C (BATTLEMAGE)
[07:15:05] [PASSED] 0xE20D (BATTLEMAGE)
[07:15:05] [PASSED] 0xE210 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE211 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE212 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE216 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE220 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE221 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE222 (BATTLEMAGE)
[07:15:05] [PASSED] 0xE223 (BATTLEMAGE)
[07:15:05] [PASSED] 0xB080 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB081 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB082 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB083 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB084 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB085 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB086 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB087 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB08F (PANTHERLAKE)
[07:15:05] [PASSED] 0xB090 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:15:05] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:15:05] [PASSED] 0xFD80 (PANTHERLAKE)
[07:15:05] [PASSED] 0xFD81 (PANTHERLAKE)
[07:15:05] ============= [PASSED] check_platform_gt_count =============
[07:15:05] ===================== [PASSED] xe_pci ======================
[07:15:05] =================== xe_rtp (2 subtests) ====================
[07:15:05] =============== xe_rtp_process_to_sr_tests  ================
[07:15:05] [PASSED] coalesce-same-reg
[07:15:05] [PASSED] no-match-no-add
[07:15:05] [PASSED] match-or
[07:15:05] [PASSED] match-or-xfail
[07:15:05] [PASSED] no-match-no-add-multiple-rules
[07:15:05] [PASSED] two-regs-two-entries
[07:15:05] [PASSED] clr-one-set-other
[07:15:05] [PASSED] set-field
[07:15:05] [PASSED] conflict-duplicate
[07:15:05] [PASSED] conflict-not-disjoint
[07:15:05] [PASSED] conflict-reg-type
[07:15:05] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:15:05] ================== xe_rtp_process_tests  ===================
[07:15:05] [PASSED] active1
[07:15:05] [PASSED] active2
[07:15:05] [PASSED] active-inactive
[07:15:05] [PASSED] inactive-active
[07:15:05] [PASSED] inactive-1st_or_active-inactive
[07:15:05] [PASSED] inactive-2nd_or_active-inactive
[07:15:05] [PASSED] inactive-last_or_active-inactive
[07:15:05] [PASSED] inactive-no_or_active-inactive
[07:15:05] ============== [PASSED] xe_rtp_process_tests ===============
[07:15:05] ===================== [PASSED] xe_rtp ======================
[07:15:05] ==================== xe_wa (1 subtest) =====================
[07:15:05] ======================== xe_wa_gt  =========================
[07:15:05] [PASSED] TIGERLAKE (B0)
[07:15:05] [PASSED] DG1 (A0)
[07:15:05] [PASSED] DG1 (B0)
[07:15:05] [PASSED] ALDERLAKE_S (A0)
[07:15:05] [PASSED] ALDERLAKE_S (B0)
[07:15:05] [PASSED] ALDERLAKE_S (C0)
[07:15:05] [PASSED] ALDERLAKE_S (D0)
[07:15:05] [PASSED] ALDERLAKE_P (A0)
[07:15:05] [PASSED] ALDERLAKE_P (B0)
[07:15:05] [PASSED] ALDERLAKE_P (C0)
[07:15:05] [PASSED] ALDERLAKE_S_RPLS (D0)
[07:15:05] [PASSED] ALDERLAKE_P_RPLU (E0)
[07:15:05] [PASSED] DG2_G10 (C0)
[07:15:05] [PASSED] DG2_G11 (B1)
[07:15:05] [PASSED] DG2_G12 (A1)
[07:15:05] [PASSED] METEORLAKE (g:A0, m:A0)
[07:15:05] [PASSED] METEORLAKE (g:A0, m:A0)
[07:15:05] [PASSED] METEORLAKE (g:A0, m:A0)
[07:15:05] [PASSED] LUNARLAKE (g:A0, m:A0)
[07:15:05] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[07:15:05] [PASSED] BATTLEMAGE (g:A0, m:A1)
[07:15:05] ==================== [PASSED] xe_wa_gt =====================
[07:15:05] ====================== [PASSED] xe_wa ======================
[07:15:05] ============================================================
[07:15:05] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[07:15:05] Elapsed time: 38.246s total, 4.307s configuring, 33.571s building, 0.332s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:15:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:15:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:15:33] Starting KUnit Kernel (1/1)...
[07:15:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:15:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:15:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:15:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:15:33] =========== drm_validate_clone_mode (2 subtests) ===========
[07:15:33] ============== drm_test_check_in_clone_mode  ===============
[07:15:33] [PASSED] in_clone_mode
[07:15:33] [PASSED] not_in_clone_mode
[07:15:33] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:15:33] =============== drm_test_check_valid_clones  ===============
[07:15:33] [PASSED] not_in_clone_mode
[07:15:33] [PASSED] valid_clone
[07:15:33] [PASSED] invalid_clone
[07:15:33] =========== [PASSED] drm_test_check_valid_clones ===========
[07:15:33] ============= [PASSED] drm_validate_clone_mode =============
[07:15:33] ============= drm_validate_modeset (1 subtest) =============
[07:15:33] [PASSED] drm_test_check_connector_changed_modeset
[07:15:33] ============== [PASSED] drm_validate_modeset ===============
[07:15:33] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:15:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:15:33] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:15:33] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:15:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:15:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:15:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:15:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:15:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:15:33] ============== drm_bridge_alloc (2 subtests) ===============
[07:15:33] [PASSED] drm_test_drm_bridge_alloc_basic
[07:15:33] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:15:33] ================ [PASSED] drm_bridge_alloc =================
[07:15:33] ================== drm_buddy (7 subtests) ==================
[07:15:33] [PASSED] drm_test_buddy_alloc_limit
[07:15:33] [PASSED] drm_test_buddy_alloc_optimistic
[07:15:33] [PASSED] drm_test_buddy_alloc_pessimistic
[07:15:33] [PASSED] drm_test_buddy_alloc_pathological
[07:15:33] [PASSED] drm_test_buddy_alloc_contiguous
[07:15:33] [PASSED] drm_test_buddy_alloc_clear
[07:15:33] [PASSED] drm_test_buddy_alloc_range_bias
[07:15:33] ==================== [PASSED] drm_buddy ====================
[07:15:33] ============= drm_cmdline_parser (40 subtests) =============
[07:15:33] [PASSED] drm_test_cmdline_force_d_only
[07:15:33] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:15:33] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:15:33] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:15:33] [PASSED] drm_test_cmdline_force_e_only
[07:15:33] [PASSED] drm_test_cmdline_res
[07:15:33] [PASSED] drm_test_cmdline_res_vesa
[07:15:33] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:15:33] [PASSED] drm_test_cmdline_res_rblank
[07:15:33] [PASSED] drm_test_cmdline_res_bpp
[07:15:33] [PASSED] drm_test_cmdline_res_refresh
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:15:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:15:33] [PASSED] drm_test_cmdline_res_margins_force_on
[07:15:33] [PASSED] drm_test_cmdline_res_vesa_margins
[07:15:33] [PASSED] drm_test_cmdline_name
[07:15:33] [PASSED] drm_test_cmdline_name_bpp
[07:15:33] [PASSED] drm_test_cmdline_name_option
[07:15:33] [PASSED] drm_test_cmdline_name_bpp_option
[07:15:33] [PASSED] drm_test_cmdline_rotate_0
[07:15:33] [PASSED] drm_test_cmdline_rotate_90
[07:15:33] [PASSED] drm_test_cmdline_rotate_180
[07:15:33] [PASSED] drm_test_cmdline_rotate_270
[07:15:33] [PASSED] drm_test_cmdline_hmirror
[07:15:33] [PASSED] drm_test_cmdline_vmirror
[07:15:33] [PASSED] drm_test_cmdline_margin_options
[07:15:33] [PASSED] drm_test_cmdline_multiple_options
[07:15:33] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:15:33] [PASSED] drm_test_cmdline_extra_and_option
[07:15:33] [PASSED] drm_test_cmdline_freestanding_options
[07:15:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:15:33] [PASSED] drm_test_cmdline_panel_orientation
[07:15:33] ================ drm_test_cmdline_invalid  =================
[07:15:33] [PASSED] margin_only
[07:15:33] [PASSED] interlace_only
[07:15:33] [PASSED] res_missing_x
[07:15:33] [PASSED] res_missing_y
[07:15:33] [PASSED] res_bad_y
[07:15:33] [PASSED] res_missing_y_bpp
[07:15:33] [PASSED] res_bad_bpp
[07:15:33] [PASSED] res_bad_refresh
[07:15:33] [PASSED] res_bpp_refresh_force_on_off
[07:15:33] [PASSED] res_invalid_mode
[07:15:33] [PASSED] res_bpp_wrong_place_mode
[07:15:33] [PASSED] name_bpp_refresh
[07:15:33] [PASSED] name_refresh
[07:15:33] [PASSED] name_refresh_wrong_mode
[07:15:33] [PASSED] name_refresh_invalid_mode
[07:15:33] [PASSED] rotate_multiple
[07:15:33] [PASSED] rotate_invalid_val
[07:15:33] [PASSED] rotate_truncated
[07:15:33] [PASSED] invalid_option
[07:15:33] [PASSED] invalid_tv_option
[07:15:33] [PASSED] truncated_tv_option
[07:15:33] ============ [PASSED] drm_test_cmdline_invalid =============
[07:15:33] =============== drm_test_cmdline_tv_options  ===============
[07:15:33] [PASSED] NTSC
[07:15:33] [PASSED] NTSC_443
[07:15:33] [PASSED] NTSC_J
[07:15:33] [PASSED] PAL
[07:15:33] [PASSED] PAL_M
[07:15:33] [PASSED] PAL_N
[07:15:33] [PASSED] SECAM
[07:15:33] [PASSED] MONO_525
[07:15:33] [PASSED] MONO_625
[07:15:33] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:15:33] =============== [PASSED] drm_cmdline_parser ================
[07:15:33] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:15:33] [PASSED] drm_test_connector_hdmi_init_valid
[07:15:33] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:15:33] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:15:33] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:15:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:15:33] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:15:33] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:15:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:15:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[07:15:33] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:15:33] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:15:33] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:15:33] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:15:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:15:33] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:15:33] [PASSED] drm_test_connector_hdmi_init_null_product
[07:15:33] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:15:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:15:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:15:33] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:15:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:15:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:15:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:15:33] ========= drm_test_connector_hdmi_init_type_valid  =========
[07:15:33] [PASSED] HDMI-A
[07:15:33] [PASSED] HDMI-B
[07:15:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:15:33] ======== drm_test_connector_hdmi_init_type_invalid  ========
[07:15:33] [PASSED] Unknown
[07:15:33] [PASSED] VGA
[07:15:33] [PASSED] DVI-I
[07:15:33] [PASSED] DVI-D
[07:15:33] [PASSED] DVI-A
[07:15:33] [PASSED] Composite
[07:15:33] [PASSED] SVIDEO
[07:15:33] [PASSED] LVDS
[07:15:33] [PASSED] Component
[07:15:33] [PASSED] DIN
[07:15:33] [PASSED] DP
[07:15:33] [PASSED] TV
[07:15:33] [PASSED] eDP
[07:15:33] [PASSED] Virtual
[07:15:33] [PASSED] DSI
[07:15:33] [PASSED] DPI
[07:15:33] [PASSED] Writeback
[07:15:33] [PASSED] SPI
[07:15:33] [PASSED] USB
[07:15:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:15:33] ============ [PASSED] drmm_connector_hdmi_init =============
[07:15:33] ============= drmm_connector_init (3 subtests) =============
[07:15:33] [PASSED] drm_test_drmm_connector_init
[07:15:33] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:15:33] ========= drm_test_drmm_connector_init_type_valid  =========
[07:15:33] [PASSED] Unknown
[07:15:33] [PASSED] VGA
[07:15:33] [PASSED] DVI-I
[07:15:33] [PASSED] DVI-D
[07:15:33] [PASSED] DVI-A
[07:15:33] [PASSED] Composite
[07:15:33] [PASSED] SVIDEO
[07:15:33] [PASSED] LVDS
[07:15:33] [PASSED] Component
[07:15:33] [PASSED] DIN
[07:15:33] [PASSED] DP
[07:15:33] [PASSED] HDMI-A
[07:15:33] [PASSED] HDMI-B
[07:15:33] [PASSED] TV
[07:15:33] [PASSED] eDP
[07:15:33] [PASSED] Virtual
[07:15:33] [PASSED] DSI
[07:15:33] [PASSED] DPI
[07:15:33] [PASSED] Writeback
[07:15:33] [PASSED] SPI
[07:15:33] [PASSED] USB
[07:15:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:15:33] =============== [PASSED] drmm_connector_init ===============
[07:15:33] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_init
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:15:33] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[07:15:33] [PASSED] Unknown
[07:15:33] [PASSED] VGA
[07:15:33] [PASSED] DVI-I
[07:15:33] [PASSED] DVI-D
[07:15:33] [PASSED] DVI-A
[07:15:33] [PASSED] Composite
[07:15:33] [PASSED] SVIDEO
[07:15:33] [PASSED] LVDS
[07:15:33] [PASSED] Component
[07:15:33] [PASSED] DIN
[07:15:33] [PASSED] DP
[07:15:33] [PASSED] HDMI-A
[07:15:33] [PASSED] HDMI-B
[07:15:33] [PASSED] TV
[07:15:33] [PASSED] eDP
[07:15:33] [PASSED] Virtual
[07:15:33] [PASSED] DSI
[07:15:33] [PASSED] DPI
[07:15:33] [PASSED] Writeback
[07:15:33] [PASSED] SPI
[07:15:33] [PASSED] USB
[07:15:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:15:33] ======== drm_test_drm_connector_dynamic_init_name  =========
[07:15:33] [PASSED] Unknown
[07:15:33] [PASSED] VGA
[07:15:33] [PASSED] DVI-I
[07:15:33] [PASSED] DVI-D
[07:15:33] [PASSED] DVI-A
[07:15:33] [PASSED] Composite
[07:15:33] [PASSED] SVIDEO
[07:15:33] [PASSED] LVDS
[07:15:33] [PASSED] Component
[07:15:33] [PASSED] DIN
[07:15:33] [PASSED] DP
[07:15:33] [PASSED] HDMI-A
[07:15:33] [PASSED] HDMI-B
[07:15:33] [PASSED] TV
[07:15:33] [PASSED] eDP
[07:15:33] [PASSED] Virtual
[07:15:33] [PASSED] DSI
[07:15:33] [PASSED] DPI
[07:15:33] [PASSED] Writeback
[07:15:33] [PASSED] SPI
[07:15:33] [PASSED] USB
[07:15:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:15:33] =========== [PASSED] drm_connector_dynamic_init ============
[07:15:33] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:15:33] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:15:33] ======= drm_connector_dynamic_register (7 subtests) ========
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:15:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:15:33] ========= [PASSED] drm_connector_dynamic_register ==========
[07:15:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:15:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:15:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:15:33] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:15:33] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:15:33] ========== drm_test_get_tv_mode_from_name_valid  ===========
[07:15:33] [PASSED] NTSC
[07:15:33] [PASSED] NTSC-443
[07:15:33] [PASSED] NTSC-J
[07:15:33] [PASSED] PAL
[07:15:33] [PASSED] PAL-M
[07:15:33] [PASSED] PAL-N
[07:15:33] [PASSED] SECAM
[07:15:33] [PASSED] Mono
[07:15:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:15:33] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:15:33] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:15:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:15:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:15:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[07:15:33] [PASSED] VIC 96
[07:15:33] [PASSED] VIC 97
[07:15:33] [PASSED] VIC 101
[07:15:33] [PASSED] VIC 102
[07:15:33] [PASSED] VIC 106
[07:15:33] [PASSED] VIC 107
[07:15:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:15:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:15:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:15:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:15:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:15:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:15:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:15:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:15:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[07:15:33] [PASSED] Automatic
[07:15:33] [PASSED] Full
[07:15:33] [PASSED] Limited 16:235
[07:15:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:15:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:15:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:15:33] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:15:33] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[07:15:33] [PASSED] RGB
[07:15:33] [PASSED] YUV 4:2:0
[07:15:33] [PASSED] YUV 4:2:2
[07:15:33] [PASSED] YUV 4:4:4
[07:15:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:15:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:15:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:15:33] ============= drm_damage_helper (21 subtests) ==============
[07:15:33] [PASSED] drm_test_damage_iter_no_damage
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:15:33] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:15:33] [PASSED] drm_test_damage_iter_simple_damage
[07:15:33] [PASSED] drm_test_damage_iter_single_damage
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:15:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:15:33] [PASSED] drm_test_damage_iter_damage
[07:15:33] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:15:33] [PASSED] drm_test_damage_iter_damage_one_outside
[07:15:33] [PASSED] drm_test_damage_iter_damage_src_moved
[07:15:33] [PASSED] drm_test_damage_iter_damage_not_visible
[07:15:33] ================ [PASSED] drm_damage_helper ================
[07:15:33] ============== drm_dp_mst_helper (3 subtests) ==============
[07:15:33] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[07:15:33] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:15:33] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:15:33] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:15:33] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:15:33] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:15:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:15:33] ============== drm_test_dp_mst_calc_pbn_div  ===============
[07:15:33] [PASSED] Link rate 2000000 lane count 4
[07:15:33] [PASSED] Link rate 2000000 lane count 2
[07:15:33] [PASSED] Link rate 2000000 lane count 1
[07:15:33] [PASSED] Link rate 1350000 lane count 4
[07:15:33] [PASSED] Link rate 1350000 lane count 2
[07:15:33] [PASSED] Link rate 1350000 lane count 1
[07:15:33] [PASSED] Link rate 1000000 lane count 4
[07:15:33] [PASSED] Link rate 1000000 lane count 2
[07:15:33] [PASSED] Link rate 1000000 lane count 1
[07:15:33] [PASSED] Link rate 810000 lane count 4
[07:15:33] [PASSED] Link rate 810000 lane count 2
[07:15:33] [PASSED] Link rate 810000 lane count 1
[07:15:33] [PASSED] Link rate 540000 lane count 4
[07:15:33] [PASSED] Link rate 540000 lane count 2
[07:15:33] [PASSED] Link rate 540000 lane count 1
[07:15:33] [PASSED] Link rate 270000 lane count 4
[07:15:33] [PASSED] Link rate 270000 lane count 2
[07:15:33] [PASSED] Link rate 270000 lane count 1
[07:15:33] [PASSED] Link rate 162000 lane count 4
[07:15:33] [PASSED] Link rate 162000 lane count 2
[07:15:33] [PASSED] Link rate 162000 lane count 1
[07:15:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:15:33] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[07:15:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:15:33] [PASSED] DP_POWER_UP_PHY with port number
[07:15:33] [PASSED] DP_POWER_DOWN_PHY with port number
[07:15:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:15:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:15:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:15:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:15:33] [PASSED] DP_QUERY_PAYLOAD with port number
[07:15:33] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:15:33] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:15:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:15:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:15:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:15:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:15:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:15:33] [PASSED] DP_REMOTE_I2C_READ with port number
[07:15:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:15:33] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:15:33] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:15:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:15:33] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:15:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:15:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:15:33] ================ [PASSED] drm_dp_mst_helper ================
[07:15:33] ================== drm_exec (7 subtests) ===================
[07:15:33] [PASSED] sanitycheck
[07:15:33] [PASSED] test_lock
[07:15:33] [PASSED] test_lock_unlock
[07:15:33] [PASSED] test_duplicates
[07:15:33] [PASSED] test_prepare
[07:15:33] [PASSED] test_prepare_array
[07:15:33] [PASSED] test_multiple_loops
[07:15:33] ==================== [PASSED] drm_exec =====================
[07:15:33] =========== drm_format_helper_test (17 subtests) ===========
[07:15:33] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:15:33] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:15:33] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:15:33] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:15:33] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:15:33] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:15:33] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:15:33] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:15:33] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:15:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:15:33] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:15:33] ============== drm_test_fb_xrgb8888_to_mono  ===============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:15:33] ==================== drm_test_fb_swab  =====================
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ================ [PASSED] drm_test_fb_swab =================
[07:15:33] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:15:33] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[07:15:33] [PASSED] single_pixel_source_buffer
[07:15:33] [PASSED] single_pixel_clip_rectangle
[07:15:33] [PASSED] well_known_colors
[07:15:33] [PASSED] destination_pitch
[07:15:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:15:33] ================= drm_test_fb_clip_offset  =================
[07:15:33] [PASSED] pass through
[07:15:33] [PASSED] horizontal offset
[07:15:33] [PASSED] vertical offset
[07:15:33] [PASSED] horizontal and vertical offset
[07:15:33] [PASSED] horizontal offset (custom pitch)
[07:15:33] [PASSED] vertical offset (custom pitch)
[07:15:33] [PASSED] horizontal and vertical offset (custom pitch)
[07:15:33] ============= [PASSED] drm_test_fb_clip_offset =============
[07:15:33] =================== drm_test_fb_memcpy  ====================
[07:15:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:15:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:15:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:15:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:15:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:15:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:15:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:15:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:15:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:15:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:15:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:15:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:15:33] =============== [PASSED] drm_test_fb_memcpy ================
[07:15:33] ============= [PASSED] drm_format_helper_test ==============
[07:15:33] ================= drm_format (18 subtests) =================
[07:15:33] [PASSED] drm_test_format_block_width_invalid
[07:15:33] [PASSED] drm_test_format_block_width_one_plane
[07:15:33] [PASSED] drm_test_format_block_width_two_plane
[07:15:33] [PASSED] drm_test_format_block_width_three_plane
[07:15:33] [PASSED] drm_test_format_block_width_tiled
[07:15:33] [PASSED] drm_test_format_block_height_invalid
[07:15:33] [PASSED] drm_test_format_block_height_one_plane
[07:15:33] [PASSED] drm_test_format_block_height_two_plane
[07:15:33] [PASSED] drm_test_format_block_height_three_plane
[07:15:33] [PASSED] drm_test_format_block_height_tiled
[07:15:33] [PASSED] drm_test_format_min_pitch_invalid
[07:15:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:15:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:15:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:15:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:15:33] [PASSED] drm_test_format_min_pitch_two_plane
[07:15:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:15:33] [PASSED] drm_test_format_min_pitch_tiled
[07:15:33] =================== [PASSED] drm_format ====================
[07:15:33] ============== drm_framebuffer (10 subtests) ===============
[07:15:33] ========== drm_test_framebuffer_check_src_coords  ==========
[07:15:33] [PASSED] Success: source fits into fb
[07:15:33] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:15:33] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:15:33] [PASSED] Fail: overflowing fb with source width
[07:15:33] [PASSED] Fail: overflowing fb with source height
[07:15:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:15:33] [PASSED] drm_test_framebuffer_cleanup
[07:15:33] =============== drm_test_framebuffer_create  ===============
[07:15:33] [PASSED] ABGR8888 normal sizes
[07:15:33] [PASSED] ABGR8888 max sizes
[07:15:33] [PASSED] ABGR8888 pitch greater than min required
[07:15:33] [PASSED] ABGR8888 pitch less than min required
[07:15:33] [PASSED] ABGR8888 Invalid width
[07:15:33] [PASSED] ABGR8888 Invalid buffer handle
[07:15:33] [PASSED] No pixel format
[07:15:33] [PASSED] ABGR8888 Width 0
[07:15:33] [PASSED] ABGR8888 Height 0
[07:15:33] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:15:33] [PASSED] ABGR8888 Large buffer offset
[07:15:33] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:15:33] [PASSED] ABGR8888 Invalid flag
[07:15:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:15:33] [PASSED] ABGR8888 Valid buffer modifier
[07:15:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:15:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] NV12 Normal sizes
[07:15:33] [PASSED] NV12 Max sizes
[07:15:33] [PASSED] NV12 Invalid pitch
[07:15:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:15:33] [PASSED] NV12 different  modifier per-plane
[07:15:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:15:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] NV12 Modifier for inexistent plane
[07:15:33] [PASSED] NV12 Handle for inexistent plane
[07:15:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:15:33] [PASSED] YVU420 Normal sizes
[07:15:33] [PASSED] YVU420 Max sizes
[07:15:33] [PASSED] YVU420 Invalid pitch
[07:15:33] [PASSED] YVU420 Different pitches
[07:15:33] [PASSED] YVU420 Different buffer offsets/pitches
[07:15:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:15:33] [PASSED] YVU420 Valid modifier
[07:15:33] [PASSED] YVU420 Different modifiers per plane
[07:15:33] [PASSED] YVU420 Modifier for inexistent plane
[07:15:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:15:33] [PASSED] X0L2 Normal sizes
[07:15:33] [PASSED] X0L2 Max sizes
[07:15:33] [PASSED] X0L2 Invalid pitch
[07:15:33] [PASSED] X0L2 Pitch greater than minimum required
[07:15:33] [PASSED] X0L2 Handle for inexistent plane
[07:15:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:15:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:15:33] [PASSED] X0L2 Valid modifier
[07:15:33] [PASSED] X0L2 Modifier for inexistent plane
[07:15:33] =========== [PASSED] drm_test_framebuffer_create ===========
[07:15:33] [PASSED] drm_test_framebuffer_free
[07:15:33] [PASSED] drm_test_framebuffer_init
[07:15:33] [PASSED] drm_test_framebuffer_init_bad_format
[07:15:33] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:15:33] [PASSED] drm_test_framebuffer_lookup
[07:15:33] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:15:33] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:15:33] ================= [PASSED] drm_framebuffer =================
[07:15:33] ================ drm_gem_shmem (8 subtests) ================
[07:15:33] [PASSED] drm_gem_shmem_test_obj_create
[07:15:33] [PASSED] drm_gem_shmem_test_obj_create_private
[07:15:33] [PASSED] drm_gem_shmem_test_pin_pages
[07:15:33] [PASSED] drm_gem_shmem_test_vmap
[07:15:33] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:15:33] [PASSED] drm_gem_shmem_test_get_sg_table
[07:15:33] [PASSED] drm_gem_shmem_test_madvise
[07:15:33] [PASSED] drm_gem_shmem_test_purge
[07:15:33] ================== [PASSED] drm_gem_shmem ==================
[07:15:33] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:15:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[07:15:33] [PASSED] Automatic
[07:15:33] [PASSED] Full
[07:15:33] [PASSED] Limited 16:235
[07:15:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:15:33] [PASSED] drm_test_check_disable_connector
[07:15:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:15:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:15:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:15:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:15:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:15:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:15:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:15:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:15:33] [PASSED] drm_test_check_output_bpc_dvi
[07:15:33] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:15:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:15:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:15:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:15:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:15:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:15:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:15:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:15:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:15:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:15:33] [PASSED] drm_test_check_broadcast_rgb_value
[07:15:33] [PASSED] drm_test_check_bpc_8_value
[07:15:33] [PASSED] drm_test_check_bpc_10_value
[07:15:33] [PASSED] drm_test_check_bpc_12_value
[07:15:33] [PASSED] drm_test_check_format_value
[07:15:33] [PASSED] drm_test_check_tmds_char_value
[07:15:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:15:33] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:15:33] [PASSED] drm_test_check_mode_valid
[07:15:33] [PASSED] drm_test_check_mode_valid_reject
[07:15:33] [PASSED] drm_test_check_mode_valid_reject_rate
[07:15:33] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:15:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:15:33] ================= drm_managed (2 subtests) =================
[07:15:33] [PASSED] drm_test_managed_release_action
[07:15:33] [PASSED] drm_test_managed_run_action
[07:15:33] =================== [PASSED] drm_managed ===================
[07:15:33] =================== drm_mm (6 subtests) ====================
[07:15:33] [PASSED] drm_test_mm_init
[07:15:33] [PASSED] drm_test_mm_debug
[07:15:33] [PASSED] drm_test_mm_align32
[07:15:33] [PASSED] drm_test_mm_align64
[07:15:33] [PASSED] drm_test_mm_lowest
[07:15:33] [PASSED] drm_test_mm_highest
[07:15:33] ===================== [PASSED] drm_mm ======================
[07:15:33] ============= drm_modes_analog_tv (5 subtests) =============
[07:15:33] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:15:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:15:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:15:33] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:15:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:15:33] =============== [PASSED] drm_modes_analog_tv ===============
[07:15:33] ============== drm_plane_helper (2 subtests) ===============
[07:15:33] =============== drm_test_check_plane_state  ================
[07:15:33] [PASSED] clipping_simple
[07:15:33] [PASSED] clipping_rotate_reflect
[07:15:33] [PASSED] positioning_simple
[07:15:33] [PASSED] upscaling
[07:15:33] [PASSED] downscaling
[07:15:33] [PASSED] rounding1
[07:15:33] [PASSED] rounding2
[07:15:33] [PASSED] rounding3
[07:15:33] [PASSED] rounding4
[07:15:33] =========== [PASSED] drm_test_check_plane_state ============
[07:15:33] =========== drm_test_check_invalid_plane_state  ============
[07:15:33] [PASSED] positioning_invalid
[07:15:33] [PASSED] upscaling_invalid
[07:15:33] [PASSED] downscaling_invalid
[07:15:33] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:15:33] ================ [PASSED] drm_plane_helper =================
[07:15:33] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:15:33] ====== drm_test_connector_helper_tv_get_modes_check  =======
[07:15:33] [PASSED] None
[07:15:33] [PASSED] PAL
[07:15:33] [PASSED] NTSC
[07:15:33] [PASSED] Both, NTSC Default
[07:15:33] [PASSED] Both, PAL Default
[07:15:33] [PASSED] Both, NTSC Default, with PAL on command-line
[07:15:33] [PASSED] Both, PAL Default, with NTSC on command-line
[07:15:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:15:33] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:15:33] ================== drm_rect (9 subtests) ===================
[07:15:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:15:33] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:15:33] [PASSED] drm_test_rect_clip_scaled_clipped
[07:15:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:15:33] ================= drm_test_rect_intersect  =================
[07:15:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:15:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:15:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:15:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:15:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:15:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:15:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:15:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:15:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:15:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:15:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:15:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:15:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:15:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:15:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:15:33] ============= [PASSED] drm_test_rect_intersect =============
[07:15:33] ================ drm_test_rect_calc_hscale  ================
[07:15:33] [PASSED] normal use
[07:15:33] [PASSED] out of max range
[07:15:33] [PASSED] out of min range
[07:15:33] [PASSED] zero dst
[07:15:33] [PASSED] negative src
[07:15:33] [PASSED] negative dst
[07:15:33] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:15:33] ================ drm_test_rect_calc_vscale  ================
[07:15:33] [PASSED] normal use
[07:15:33] [PASSED] out of max range
[07:15:33] [PASSED] out of min range
[07:15:33] [PASSED] zero dst
[07:15:33] [PASSED] negative src
[07:15:33] [PASSED] negative dst
[07:15:33] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:15:33] ================== drm_test_rect_rotate  ===================
[07:15:33] [PASSED] reflect-x
[07:15:33] [PASSED] reflect-y
[07:15:33] [PASSED] rotate-0
[07:15:33] [PASSED] rotate-90
[07:15:33] [PASSED] rotate-180
[07:15:33] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[07:15:33] ============== [PASSED] drm_test_rect_rotate ===============
[07:15:33] ================ drm_test_rect_rotate_inv  =================
[07:15:33] [PASSED] reflect-x
[07:15:33] [PASSED] reflect-y
[07:15:33] [PASSED] rotate-0
[07:15:33] [PASSED] rotate-90
[07:15:33] [PASSED] rotate-180
[07:15:33] [PASSED] rotate-270
[07:15:33] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:15:33] ==================== [PASSED] drm_rect =====================
[07:15:33] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:15:33] ============ drm_test_sysfb_build_fourcc_list  =============
[07:15:33] [PASSED] no native formats
[07:15:33] [PASSED] XRGB8888 as native format
[07:15:33] [PASSED] remove duplicates
[07:15:33] [PASSED] convert alpha formats
[07:15:33] [PASSED] random formats
[07:15:33] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:15:33] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:15:33] ============================================================
[07:15:33] Testing complete. Ran 616 tests: passed: 616
[07:15:33] Elapsed time: 28.036s total, 1.612s configuring, 26.255s building, 0.136s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:15:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:15:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:15:42] Starting KUnit Kernel (1/1)...
[07:15:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:15:42] ================= ttm_device (5 subtests) ==================
[07:15:42] [PASSED] ttm_device_init_basic
[07:15:42] [PASSED] ttm_device_init_multiple
[07:15:42] [PASSED] ttm_device_fini_basic
[07:15:42] [PASSED] ttm_device_init_no_vma_man
[07:15:42] ================== ttm_device_init_pools  ==================
[07:15:42] [PASSED] No DMA allocations, no DMA32 required
[07:15:42] [PASSED] DMA allocations, DMA32 required
[07:15:42] [PASSED] No DMA allocations, DMA32 required
[07:15:42] [PASSED] DMA allocations, no DMA32 required
[07:15:42] ============== [PASSED] ttm_device_init_pools ==============
[07:15:42] =================== [PASSED] ttm_device ====================
[07:15:42] ================== ttm_pool (8 subtests) ===================
[07:15:42] ================== ttm_pool_alloc_basic  ===================
[07:15:42] [PASSED] One page
[07:15:42] [PASSED] More than one page
[07:15:42] [PASSED] Above the allocation limit
[07:15:42] [PASSED] One page, with coherent DMA mappings enabled
[07:15:42] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:15:42] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:15:42] ============== ttm_pool_alloc_basic_dma_addr  ==============
[07:15:42] [PASSED] One page
[07:15:42] [PASSED] More than one page
[07:15:42] [PASSED] Above the allocation limit
[07:15:42] [PASSED] One page, with coherent DMA mappings enabled
[07:15:42] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:15:42] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:15:42] [PASSED] ttm_pool_alloc_order_caching_match
[07:15:42] [PASSED] ttm_pool_alloc_caching_mismatch
[07:15:42] [PASSED] ttm_pool_alloc_order_mismatch
[07:15:42] [PASSED] ttm_pool_free_dma_alloc
[07:15:42] [PASSED] ttm_pool_free_no_dma_alloc
[07:15:42] [PASSED] ttm_pool_fini_basic
[07:15:42] ==================== [PASSED] ttm_pool =====================
[07:15:42] ================ ttm_resource (8 subtests) =================
[07:15:42] ================= ttm_resource_init_basic  =================
[07:15:42] [PASSED] Init resource in TTM_PL_SYSTEM
[07:15:42] [PASSED] Init resource in TTM_PL_VRAM
[07:15:42] [PASSED] Init resource in a private placement
[07:15:42] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:15:42] ============= [PASSED] ttm_resource_init_basic =============
[07:15:42] [PASSED] ttm_resource_init_pinned
[07:15:42] [PASSED] ttm_resource_fini_basic
[07:15:42] [PASSED] ttm_resource_manager_init_basic
[07:15:42] [PASSED] ttm_resource_manager_usage_basic
[07:15:42] [PASSED] ttm_resource_manager_set_used_basic
[07:15:42] [PASSED] ttm_sys_man_alloc_basic
[07:15:42] [PASSED] ttm_sys_man_free_basic
[07:15:42] ================== [PASSED] ttm_resource ===================
[07:15:42] =================== ttm_tt (15 subtests) ===================
[07:15:42] ==================== ttm_tt_init_basic  ====================
[07:15:42] [PASSED] Page-aligned size
[07:15:42] [PASSED] Extra pages requested
[07:15:42] ================ [PASSED] ttm_tt_init_basic ================
[07:15:42] [PASSED] ttm_tt_init_misaligned
[07:15:42] [PASSED] ttm_tt_fini_basic
[07:15:42] [PASSED] ttm_tt_fini_sg
[07:15:42] [PASSED] ttm_tt_fini_shmem
[07:15:42] [PASSED] ttm_tt_create_basic
[07:15:42] [PASSED] ttm_tt_create_invalid_bo_type
[07:15:42] [PASSED] ttm_tt_create_ttm_exists
[07:15:42] [PASSED] ttm_tt_create_failed
[07:15:42] [PASSED] ttm_tt_destroy_basic
[07:15:42] [PASSED] ttm_tt_populate_null_ttm
[07:15:42] [PASSED] ttm_tt_populate_populated_ttm
[07:15:42] [PASSED] ttm_tt_unpopulate_basic
[07:15:42] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:15:42] [PASSED] ttm_tt_swapin_basic
[07:15:42] ===================== [PASSED] ttm_tt ======================
[07:15:42] =================== ttm_bo (14 subtests) ===================
[07:15:42] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[07:15:42] [PASSED] Cannot be interrupted and sleeps
[07:15:42] [PASSED] Cannot be interrupted, locks straight away
[07:15:42] [PASSED] Can be interrupted, sleeps
[07:15:42] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:15:42] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:15:42] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:15:42] [PASSED] ttm_bo_reserve_double_resv
[07:15:42] [PASSED] ttm_bo_reserve_interrupted
[07:15:42] [PASSED] ttm_bo_reserve_deadlock
[07:15:42] [PASSED] ttm_bo_unreserve_basic
[07:15:42] [PASSED] ttm_bo_unreserve_pinned
[07:15:42] [PASSED] ttm_bo_unreserve_bulk
[07:15:42] [PASSED] ttm_bo_put_basic
[07:15:42] [PASSED] ttm_bo_put_shared_resv
[07:15:42] [PASSED] ttm_bo_pin_basic
[07:15:42] [PASSED] ttm_bo_pin_unpin_resource
[07:15:42] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:15:42] ===================== [PASSED] ttm_bo ======================
[07:15:42] ============== ttm_bo_validate (21 subtests) ===============
[07:15:42] ============== ttm_bo_init_reserved_sys_man  ===============
[07:15:42] [PASSED] Buffer object for userspace
[07:15:42] [PASSED] Kernel buffer object
[07:15:42] [PASSED] Shared buffer object
[07:15:42] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:15:42] ============== ttm_bo_init_reserved_mock_man  ==============
[07:15:42] [PASSED] Buffer object for userspace
[07:15:42] [PASSED] Kernel buffer object
[07:15:42] [PASSED] Shared buffer object
[07:15:42] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:15:42] [PASSED] ttm_bo_init_reserved_resv
[07:15:42] ================== ttm_bo_validate_basic  ==================
[07:15:42] [PASSED] Buffer object for userspace
[07:15:42] [PASSED] Kernel buffer object
[07:15:42] [PASSED] Shared buffer object
[07:15:42] ============== [PASSED] ttm_bo_validate_basic ==============
[07:15:42] [PASSED] ttm_bo_validate_invalid_placement
[07:15:42] ============= ttm_bo_validate_same_placement  ==============
[07:15:42] [PASSED] System manager
[07:15:42] [PASSED] VRAM manager
[07:15:42] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:15:42] [PASSED] ttm_bo_validate_failed_alloc
[07:15:42] [PASSED] ttm_bo_validate_pinned
[07:15:42] [PASSED] ttm_bo_validate_busy_placement
[07:15:42] ================ ttm_bo_validate_multihop  =================
[07:15:42] [PASSED] Buffer object for userspace
[07:15:42] [PASSED] Kernel buffer object
[07:15:42] [PASSED] Shared buffer object
[07:15:42] ============ [PASSED] ttm_bo_validate_multihop =============
[07:15:42] ========== ttm_bo_validate_no_placement_signaled  ==========
[07:15:42] [PASSED] Buffer object in system domain, no page vector
[07:15:42] [PASSED] Buffer object in system domain with an existing page vector
[07:15:42] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:15:42] ======== ttm_bo_validate_no_placement_not_signaled  ========
[07:15:42] [PASSED] Buffer object for userspace
[07:15:42] [PASSED] Kernel buffer object
[07:15:42] [PASSED] Shared buffer object
[07:15:42] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:15:42] [PASSED] ttm_bo_validate_move_fence_signaled
[07:15:42] ========= ttm_bo_validate_move_fence_not_signaled  =========
[07:15:42] [PASSED] Waits for GPU
[07:15:42] [PASSED] Tries to lock straight away
[07:15:42] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:15:42] [PASSED] ttm_bo_validate_happy_evict
[07:15:42] [PASSED] ttm_bo_validate_all_pinned_evict
[07:15:42] [PASSED] ttm_bo_validate_allowed_only_evict
[07:15:42] [PASSED] ttm_bo_validate_deleted_evict
[07:15:42] [PASSED] ttm_bo_validate_busy_domain_evict
[07:15:42] [PASSED] ttm_bo_validate_evict_gutting
[07:15:42] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:15:42] ================= [PASSED] ttm_bo_validate =================
[07:15:42] ============================================================
[07:15:42] Testing complete. Ran 101 tests: passed: 101
[07:15:42] Elapsed time: 9.586s total, 1.611s configuring, 7.758s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 976 bytes --]

== Series Details ==

Series: drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM
URL   : https://patchwork.freedesktop.org/series/151739/
State : success

== Summary ==

CI Bug Log - changes from xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331_BAT -> xe-pw-151739v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 7)
------------------------------

  Missing    (1): bat-adlp-vm 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331 -> xe-pw-151739v1

  IGT_8462: f33a311145a889757f45313d2ff4bf58f7ef01d6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331: e7058b7a607f5fdfd7bc4586644756d7ef002331
  xe-pw-151739v1: 151739v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/index.html

[-- Attachment #2: Type: text/html, Size: 1524 bytes --]

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Gustavo Sousa]

Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
>We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
>since we started configuring LFPS sending. According to Bspec Configuring
>LFPS sending is needed only when using AUXLess ALPM. This patch avoids
>these failures by configuring LFPS sending only when using AUXLess ALPM.

Hm... But then with this patch we are missing writing zero to that bit
when necessary, no?

Could the timeouts be happening because intel_cx0_rmw() is getting
called without calling
intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end()?

>
>Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
>Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index ed8e640b96b0..9cfc3187aeab 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
>                                  const struct intel_crtc_state *crtc_state)
> {
>         struct intel_display *display = to_intel_display(encoder);
>-        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
>-        bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>-                                                  crtc_state);
>+        u8 owned_lane_mask;
>         int i;
> 
>-        if (DISPLAY_VER(display) < 20)
>+        if (DISPLAY_VER(display) < 20 ||
>+            !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
>                 return;
> 
>+        owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

This optimization could be on it's own patch.

--
Gustavo Sousa

>         for (i = 0; i < 4; i++) {
>                 int tx = i % 2 + 1;
>                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>@@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> 
>                 intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
>                               CONTROL0_MAC_TRANSMIT_LFPS,
>-                              enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
>-                              MB_WRITE_COMMITTED);
>+                              CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
>         }
> }
> 
>-- 
>2.43.0
>

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Hogander, Jouni]

On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
> Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
> > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3
> > retries"
> > since we started configuring LFPS sending. According to Bspec
> > Configuring
> > LFPS sending is needed only when using AUXLess ALPM. This patch
> > avoids
> > these failures by configuring LFPS sending only when using AUXLess
> > ALPM.
> 
> Hm... But then with this patch we are missing writing zero to that
> bit
> when necessary, no?

That shouldn't be necessary as 0 is the reset value.

> 
> Could the timeouts be happening because intel_cx0_rmw() is getting
> called without calling
> intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end()?

I wasn't aware about these. I will try them.

BR,

Jouni Högander

> 
> > 
> > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure
> > LFPS sending")
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
> > 1 file changed, 5 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index ed8e640b96b0..9cfc3187aeab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >                                  const struct intel_crtc_state
> > *crtc_state)
> > {
> >         struct intel_display *display = to_intel_display(encoder);
> > -        u8 owned_lane_mask =
> > intel_cx0_get_owned_lane_mask(encoder);
> > -        bool enable =
> > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > -                                                  crtc_state);
> > +        u8 owned_lane_mask;
> >         int i;
> > 
> > -        if (DISPLAY_VER(display) < 20)
> > +        if (DISPLAY_VER(display) < 20 ||
> > +            !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > crtc_state))
> >                 return;
> > 
> > +        owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> 
> This optimization could be on it's own patch.
> 
> --
> Gustavo Sousa
> 
> >         for (i = 0; i < 4; i++) {
> >                 int tx = i % 2 + 1;
> >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > INTEL_CX0_LANE1;
> > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> > 
> >                 intel_cx0_rmw(encoder, lane_mask,
> > PHY_CMN1_CONTROL(tx, 0),
> >                               CONTROL0_MAC_TRANSMIT_LFPS,
> > -                              enable ? CONTROL0_MAC_TRANSMIT_LFPS
> > : 0,
> > -                              MB_WRITE_COMMITTED);
> > +                              CONTROL0_MAC_TRANSMIT_LFPS,
> > MB_WRITE_COMMITTED);
> >         }
> > }
> > 
> > -- 
> > 2.43.0
> > 

✗ Xe.CI.Full: failure for drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38523 bytes --]

== Series Details ==

Series: drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM
URL   : https://patchwork.freedesktop.org/series/151739/
State : failure

== Summary ==

CI Bug Log - changes from xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331_FULL -> xe-pw-151739v1_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-151739v1_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-151739v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-151739v1_FULL:

### IGT changes ###

#### Warnings ####

  * igt@xe_pm@d3cold-basic-exec:
    - shard-adlp:         [SKIP][1] ([Intel XE#2284] / [Intel XE#366]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_pm@d3cold-basic-exec.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-1/igt@xe_pm@d3cold-basic-exec.html

  
Known issues
------------

  Here are the changes found in xe-pw-151739v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#1124])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][5] -> [SKIP][6] ([Intel XE#2314] / [Intel XE#2894])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#787]) +125 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-433/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2907])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#455] / [Intel XE#787]) +19 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][13] -> [INCOMPLETE][14] ([Intel XE#3862]) +1 other test incomplete
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][19] -> [INCOMPLETE][20] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2325])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2252]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-multiple:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#373]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_chamelium_frames@dp-crc-multiple.html

  * igt@kms_content_protection@atomic@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][24] ([Intel XE#1178])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-464/igt@kms_content_protection@atomic@pipe-a-dp-4.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][25] ([Intel XE#1178]) +1 other test fail
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][26] ([Intel XE#1188])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-433/igt@kms_content_protection@uevent@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2321])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#308])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2291]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#4331])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#455])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-adlp:         [PASS][33] -> [SKIP][34] ([Intel XE#4947])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@kms_fbcon_fbt@fbc.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-8/igt@kms_fbcon_fbt@fbc.html
    - shard-dg2-set2:     [PASS][35] -> [SKIP][36] ([Intel XE#2351] / [Intel XE#4208])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@kms_fbcon_fbt@fbc.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#776])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2375])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-dg2-set2:     [PASS][39] -> [SKIP][40] ([Intel XE#4208] / [i915#2575]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@basic-plain-flip@b-hdmi-a1:
    - shard-adlp:         [PASS][41] -> [DMESG-WARN][42] ([Intel XE#4543])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-6/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-3/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [PASS][43] -> [INCOMPLETE][44] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-5/igt@kms_flip@flip-vs-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-4/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [PASS][45] -> [INCOMPLETE][46] ([Intel XE#2049] / [Intel XE#2597]) +2 other tests incomplete
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend@d-dp2:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][47] ([Intel XE#2049] / [Intel XE#2597])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-432/igt@kms_flip@flip-vs-suspend@d-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2293] / [Intel XE#2380])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2293])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#651]) +4 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2311]) +6 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#5390]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2313]) +6 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#653]) +6 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-bmg:          [PASS][55] -> [SKIP][56] ([Intel XE#1503])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_hdr@static-toggle-dpms.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_lease@lease-unleased-connector:
    - shard-adlp:         [PASS][57] -> [SKIP][58] ([Intel XE#4950])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@kms_lease@lease-unleased-connector.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-8/igt@kms_lease@lease-unleased-connector.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#4359])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#1129])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#3309])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-adlp:         [PASS][62] -> [FAIL][63] ([Intel XE#718])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#1489]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#1489]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-primary-page-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@kms_psr@fbc-pr-primary-page-flip.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2330])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#2413])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_vrr@max-min:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1499]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_vrr@max-min.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_eudebug_online@interrupt-other:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#4837]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_eudebug_online@interrupt-other.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#4837]) +2 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2322]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-dg2-set2:     [PASS][75] -> [SKIP][76] ([Intel XE#1392]) +6 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_fault_mode@once-userptr-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#288]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_exec_fault_mode@once-userptr-imm.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [PASS][78] -> [DMESG-WARN][79] ([Intel XE#3876])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-1/igt@xe_exec_reset@parallel-gt-reset.html
    - shard-bmg:          NOTRUN -> [DMESG-WARN][80] ([Intel XE#3876])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_reset@virtual-close-fd-no-exec:
    - shard-adlp:         [PASS][81] -> [SKIP][82] ([Intel XE#4945]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@xe_exec_reset@virtual-close-fd-no-exec.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-8/igt@xe_exec_reset@virtual-close-fd-no-exec.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][83] ([Intel XE#4208]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_exec_reset@virtual-close-fd-no-exec.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#4943]) +4 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-remap-ro-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#4915]) +33 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-remap-ro-eocheck.html

  * igt@xe_exec_threads@threads-mixed-userptr-invalidate-race:
    - shard-adlp:         [PASS][86] -> [DMESG-FAIL][87] ([Intel XE#3876]) +1 other test dmesg-fail
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_exec_threads@threads-mixed-userptr-invalidate-race.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-1/igt@xe_exec_threads@threads-mixed-userptr-invalidate-race.html

  * igt@xe_oa@invalid-create-userspace-config:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#2541] / [Intel XE#3573])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_oa@invalid-create-userspace-config.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#2284])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-adlp:         [PASS][90] -> [DMESG-WARN][91] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-1/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#4733])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#4273])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][94] ([Intel XE#301]) -> [PASS][95] +1 other test pass
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [DMESG-WARN][96] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][98] ([Intel XE#4543]) -> [PASS][99] +1 other test pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][100] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][101] +4 other tests pass
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind:
    - shard-dg2-set2:     [SKIP][102] ([Intel XE#1392]) -> [PASS][103] +6 other tests pass
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-433/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][104] ([Intel XE#5018]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][106] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][107] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-adlp:         [SKIP][108] ([Intel XE#310]) -> [SKIP][109] ([Intel XE#4950])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-8/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][110] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][111] ([Intel XE#301])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][112] ([Intel XE#2311]) -> [SKIP][113] ([Intel XE#2312]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][114] ([Intel XE#5390]) -> [SKIP][115] ([Intel XE#2312]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][116] ([Intel XE#2312]) -> [SKIP][117] ([Intel XE#2311])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][118] ([Intel XE#2313]) -> [SKIP][119] ([Intel XE#2312]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][120] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][121] ([Intel XE#3544])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][122] ([Intel XE#1729]) -> [SKIP][123] ([Intel XE#2426])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_exec_capture@reset:
    - shard-dg2-set2:     [INCOMPLETE][124] ([Intel XE#4842]) -> [SKIP][125] ([Intel XE#4208])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@xe_exec_capture@reset.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_exec_capture@reset.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset:
    - shard-dg2-set2:     [SKIP][126] ([Intel XE#4915]) -> [SKIP][127] ([Intel XE#4208]) +3 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-dg2-435/igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset.html

  * igt@xe_exec_system_allocator@many-stride-mmap-free:
    - shard-adlp:         [SKIP][128] ([Intel XE#4915]) -> [SKIP][129] ([Intel XE#4945]) +4 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@xe_exec_system_allocator@many-stride-mmap-free.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/shard-adlp-8/igt@xe_exec_system_allocator@many-stride-mmap-free.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
  [Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
  [Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * Linux: xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331 -> xe-pw-151739v1

  IGT_8462: f33a311145a889757f45313d2ff4bf58f7ef01d6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331: e7058b7a607f5fdfd7bc4586644756d7ef002331
  xe-pw-151739v1: 151739v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151739v1/index.html

[-- Attachment #2: Type: text/html, Size: 45443 bytes --]

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Hogander, Jouni]

On Fri, 2025-07-18 at 09:05 +0300, Hogander, Jouni wrote:
> On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
> > Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
> > > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3
> > > retries"
> > > since we started configuring LFPS sending. According to Bspec
> > > Configuring
> > > LFPS sending is needed only when using AUXLess ALPM. This patch
> > > avoids
> > > these failures by configuring LFPS sending only when using
> > > AUXLess
> > > ALPM.
> > 
> > Hm... But then with this patch we are missing writing zero to that
> > bit
> > when necessary, no?
> 
> That shouldn't be necessary as 0 is the reset value.
> 
> > 
> > Could the timeouts be happening because intel_cx0_rmw() is getting
> > called without calling
> > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end()?
> 
> I wasn't aware about these. I will try them.

I tested this and it doesn't help:

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ed8e640b96b0..e6ff7f07b2e3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct
intel_encoder *encoder,
                                 const struct intel_crtc_state
*crtc_state)
 {
        struct intel_display *display = to_intel_display(encoder);
+       intel_wakeref_t wakeref;
        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
        bool enable =
intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
                                                  crtc_state);
@@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct
intel_encoder *encoder,
        if (DISPLAY_VER(display) < 20)
                return;
 
+       wakeref = intel_cx0_phy_transaction_begin(encoder);
+
        for (i = 0; i < 4; i++) {
                int tx = i % 2 + 1;
                u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
INTEL_CX0_LANE1;
@@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct
intel_encoder *encoder,
                              enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
                              MB_WRITE_COMMITTED);
        }
+
+       intel_cx0_phy_transaction_end(encoder, wakeref);
 }

Do you think I should still add this change as well?

> 
> BR,
> 
> Jouni Högander
> 
> > 
> > > 
> > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure
> > > LFPS sending")
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
> > > 1 file changed, 5 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index ed8e640b96b0..9cfc3187aeab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct
> > > intel_encoder *encoder,
> > >                                  const struct intel_crtc_state
> > > *crtc_state)
> > > {
> > >         struct intel_display *display =
> > > to_intel_display(encoder);
> > > -        u8 owned_lane_mask =
> > > intel_cx0_get_owned_lane_mask(encoder);
> > > -        bool enable =
> > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > -                                                  crtc_state);
> > > +        u8 owned_lane_mask;
> > >         int i;
> > > 
> > > -        if (DISPLAY_VER(display) < 20)
> > > +        if (DISPLAY_VER(display) < 20 ||
> > > +           
> > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > crtc_state))
> > >                 return;
> > > 
> > > +        owned_lane_mask =
> > > intel_cx0_get_owned_lane_mask(encoder);
> > 
> > This optimization could be on it's own patch.

Ok, maybe I leave that out or add own patch.

BR,

Jouni Högander


> > 
> > --
> > Gustavo Sousa
> > 
> > >         for (i = 0; i < 4; i++) {
> > >                 int tx = i % 2 + 1;
> > >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > > INTEL_CX0_LANE1;
> > > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct
> > > intel_encoder *encoder,
> > > 
> > >                 intel_cx0_rmw(encoder, lane_mask,
> > > PHY_CMN1_CONTROL(tx, 0),
> > >                               CONTROL0_MAC_TRANSMIT_LFPS,
> > > -                              enable ?
> > > CONTROL0_MAC_TRANSMIT_LFPS
> > > : 0,
> > > -                              MB_WRITE_COMMITTED);
> > > +                              CONTROL0_MAC_TRANSMIT_LFPS,
> > > MB_WRITE_COMMITTED);
> > >         }
> > > }
> > > 
> > > -- 
> > > 2.43.0
> > > 
> 

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Gustavo Sousa]

Quoting Hogander, Jouni (2025-07-18 07:46:31-03:00)
>On Fri, 2025-07-18 at 09:05 +0300, Hogander, Jouni wrote:
>> On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
>> > Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
>> > > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3
>> > > retries"
>> > > since we started configuring LFPS sending. According to Bspec
>> > > Configuring
>> > > LFPS sending is needed only when using AUXLess ALPM. This patch
>> > > avoids
>> > > these failures by configuring LFPS sending only when using
>> > > AUXLess
>> > > ALPM.
>> > 
>> > Hm... But then with this patch we are missing writing zero to that
>> > bit
>> > when necessary, no?
>> 
>> That shouldn't be necessary as 0 is the reset value.
>> 
>> > 
>> > Could the timeouts be happening because intel_cx0_rmw() is getting
>> > called without calling
>> > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end()?
>> 
>> I wasn't aware about these. I will try them.
>
>I tested this and it doesn't help:

Okay. Well, I still find it weird that this would time out for one case
and not time out for another... Do we have confirmation that this is
working fine for the AUX-Less ALPM case?

I wonder if we should rather do this step together with
intel_c10_pll_program(). Note that, for C10, there is also a required
step to set PHY_C10_VDR_CONTROL1[2] before accessing the msgbus.

>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index ed8e640b96b0..e6ff7f07b2e3 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct
>intel_encoder *encoder,
>                                 const struct intel_crtc_state
>*crtc_state)
> {
>        struct intel_display *display = to_intel_display(encoder);
>+       intel_wakeref_t wakeref;
>        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
>        bool enable =
>intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>                                                  crtc_state);
>@@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct
>intel_encoder *encoder,
>        if (DISPLAY_VER(display) < 20)
>                return;
> 
>+       wakeref = intel_cx0_phy_transaction_begin(encoder);
>+
>        for (i = 0; i < 4; i++) {
>                int tx = i % 2 + 1;
>                u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
>INTEL_CX0_LANE1;
>@@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct
>intel_encoder *encoder,
>                              enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
>                              MB_WRITE_COMMITTED);
>        }
>+
>+       intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
>Do you think I should still add this change as well?

If we are still going with this function instead of doing it in
intel_c10_pll_program(), then yes.

--
Gustavo Sousa

>
>> 
>> BR,
>> 
>> Jouni Högander
>> 
>> > 
>> > > 
>> > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure
>> > > LFPS sending")
>> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> > > ---
>> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
>> > > 1 file changed, 5 insertions(+), 6 deletions(-)
>> > > 
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > index ed8e640b96b0..9cfc3187aeab 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > @@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct
>> > > intel_encoder *encoder,
>> > >                                  const struct intel_crtc_state
>> > > *crtc_state)
>> > > {
>> > >         struct intel_display *display =
>> > > to_intel_display(encoder);
>> > > -        u8 owned_lane_mask =
>> > > intel_cx0_get_owned_lane_mask(encoder);
>> > > -        bool enable =
>> > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>> > > -                                                  crtc_state);
>> > > +        u8 owned_lane_mask;
>> > >         int i;
>> > > 
>> > > -        if (DISPLAY_VER(display) < 20)
>> > > +        if (DISPLAY_VER(display) < 20 ||
>> > > +           
>> > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>> > > crtc_state))
>> > >                 return;
>> > > 
>> > > +        owned_lane_mask =
>> > > intel_cx0_get_owned_lane_mask(encoder);
>> > 
>> > This optimization could be on it's own patch.
>
>Ok, maybe I leave that out or add own patch.
>
>BR,
>
>Jouni Högander
>
>
>> > 
>> > --
>> > Gustavo Sousa
>> > 
>> > >         for (i = 0; i < 4; i++) {
>> > >                 int tx = i % 2 + 1;
>> > >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
>> > > INTEL_CX0_LANE1;
>> > > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct
>> > > intel_encoder *encoder,
>> > > 
>> > >                 intel_cx0_rmw(encoder, lane_mask,
>> > > PHY_CMN1_CONTROL(tx, 0),
>> > >                               CONTROL0_MAC_TRANSMIT_LFPS,
>> > > -                              enable ?
>> > > CONTROL0_MAC_TRANSMIT_LFPS
>> > > : 0,
>> > > -                              MB_WRITE_COMMITTED);
>> > > +                              CONTROL0_MAC_TRANSMIT_LFPS,
>> > > MB_WRITE_COMMITTED);
>> > >         }
>> > > }
>> > > 
>> > > -- 
>> > > 2.43.0
>> > > 
>> 
>

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Hogander, Jouni]

On Fri, 2025-07-18 at 09:58 -0300, Gustavo Sousa wrote:
> Quoting Hogander, Jouni (2025-07-18 07:46:31-03:00)
> > On Fri, 2025-07-18 at 09:05 +0300, Hogander, Jouni wrote:
> > > On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
> > > > Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
> > > > > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after
> > > > > 3
> > > > > retries"
> > > > > since we started configuring LFPS sending. According to Bspec
> > > > > Configuring
> > > > > LFPS sending is needed only when using AUXLess ALPM. This
> > > > > patch
> > > > > avoids
> > > > > these failures by configuring LFPS sending only when using
> > > > > AUXLess
> > > > > ALPM.
> > > > 
> > > > Hm... But then with this patch we are missing writing zero to
> > > > that
> > > > bit
> > > > when necessary, no?
> > > 
> > > That shouldn't be necessary as 0 is the reset value.
> > > 
> > > > 
> > > > Could the timeouts be happening because intel_cx0_rmw() is
> > > > getting
> > > > called without calling
> > > > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end
> > > > ()?
> > > 
> > > I wasn't aware about these. I will try them.
> > 
> > I tested this and it doesn't help:
> 
> Okay. Well, I still find it weird that this would time out for one
> case
> and not time out for another... Do we have confirmation that this is
> working fine for the AUX-Less ALPM case?

I can reproduce this issue only with setup having two 4k monitors in DP
ports and then one eDP panel. The issue is triggered on DP port. I.e.
something that doesn't have AUX-Less ALPM. As it's clearly unnecessary
to write this register on that failing port and not mentioned in HAS I
was thinking just removing the failing write would work in this case.

> 
> I wonder if we should rather do this step together with
> intel_c10_pll_program(). Note that, for C10, there is also a required
> step to set PHY_C10_VDR_CONTROL1[2] before accessing the msgbus.

Configuring this is a own step listed in HAS (6.k.ii). I can try if
this works. I have no idea if it's ok to move it.

> 
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index ed8e640b96b0..e6ff7f07b2e3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >                                 const struct intel_crtc_state
> > *crtc_state)
> > {
> >        struct intel_display *display = to_intel_display(encoder);
> > +       intel_wakeref_t wakeref;
> >        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> >        bool enable =
> > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> >                                                  crtc_state);
> > @@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >        if (DISPLAY_VER(display) < 20)
> >                return;
> > 
> > +       wakeref = intel_cx0_phy_transaction_begin(encoder);
> > +
> >        for (i = 0; i < 4; i++) {
> >                int tx = i % 2 + 1;
> >                u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > INTEL_CX0_LANE1;
> > @@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >                              enable ? CONTROL0_MAC_TRANSMIT_LFPS :
> > 0,
> >                              MB_WRITE_COMMITTED);
> >        }
> > +
> > +       intel_cx0_phy_transaction_end(encoder, wakeref);
> > }
> > 
> > Do you think I should still add this change as well?
> 
> If we are still going with this function instead of doing it in
> intel_c10_pll_program(), then yes.
> 
> --
> Gustavo Sousa
> 
> > 
> > > 
> > > BR,
> > > 
> > > Jouni Högander
> > > 
> > > > 
> > > > > 
> > > > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to
> > > > > configure
> > > > > LFPS sending")
> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
> > > > > 1 file changed, 5 insertions(+), 6 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > index ed8e640b96b0..9cfc3187aeab 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > @@ -3239,14 +3239,14 @@ void
> > > > > intel_lnl_mac_transmit_lfps(struct
> > > > > intel_encoder *encoder,
> > > > >                                  const struct
> > > > > intel_crtc_state
> > > > > *crtc_state)
> > > > > {
> > > > >         struct intel_display *display =
> > > > > to_intel_display(encoder);
> > > > > -        u8 owned_lane_mask =
> > > > > intel_cx0_get_owned_lane_mask(encoder);
> > > > > -        bool enable =
> > > > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > > > -                                                 
> > > > > crtc_state);
> > > > > +        u8 owned_lane_mask;
> > > > >         int i;
> > > > > 
> > > > > -        if (DISPLAY_VER(display) < 20)
> > > > > +        if (DISPLAY_VER(display) < 20 ||
> > > > > +           
> > > > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > > > crtc_state))
> > > > >                 return;
> > > > > 
> > > > > +        owned_lane_mask =
> > > > > intel_cx0_get_owned_lane_mask(encoder);
> > > > 
> > > > This optimization could be on it's own patch.
> > 
> > Ok, maybe I leave that out or add own patch.
> > 
> > BR,
> > 
> > Jouni Högander
> > 
> > 
> > > > 
> > > > --
> > > > Gustavo Sousa
> > > > 
> > > > >         for (i = 0; i < 4; i++) {
> > > > >                 int tx = i % 2 + 1;
> > > > >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > > > > INTEL_CX0_LANE1;
> > > > > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct
> > > > > intel_encoder *encoder,
> > > > > 
> > > > >                 intel_cx0_rmw(encoder, lane_mask,
> > > > > PHY_CMN1_CONTROL(tx, 0),
> > > > >                               CONTROL0_MAC_TRANSMIT_LFPS,
> > > > > -                              enable ?
> > > > > CONTROL0_MAC_TRANSMIT_LFPS
> > > > > : 0,
> > > > > -                              MB_WRITE_COMMITTED);
> > > > > +                              CONTROL0_MAC_TRANSMIT_LFPS,
> > > > > MB_WRITE_COMMITTED);
> > > > >         }
> > > > > }
> > > > > 
> > > > > -- 
> > > > > 2.43.0
> > > > > 
> > > 
> > 

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Gustavo Sousa]

Quoting Hogander, Jouni (2025-07-18 10:08:52-03:00)
>On Fri, 2025-07-18 at 09:58 -0300, Gustavo Sousa wrote:
>> Quoting Hogander, Jouni (2025-07-18 07:46:31-03:00)
>> > On Fri, 2025-07-18 at 09:05 +0300, Hogander, Jouni wrote:
>> > > On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
>> > > > Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
>> > > > > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after
>> > > > > 3
>> > > > > retries"
>> > > > > since we started configuring LFPS sending. According to Bspec
>> > > > > Configuring
>> > > > > LFPS sending is needed only when using AUXLess ALPM. This
>> > > > > patch
>> > > > > avoids
>> > > > > these failures by configuring LFPS sending only when using
>> > > > > AUXLess
>> > > > > ALPM.
>> > > > 
>> > > > Hm... But then with this patch we are missing writing zero to
>> > > > that
>> > > > bit
>> > > > when necessary, no?
>> > > 
>> > > That shouldn't be necessary as 0 is the reset value.
>> > > 
>> > > > 
>> > > > Could the timeouts be happening because intel_cx0_rmw() is
>> > > > getting
>> > > > called without calling
>> > > > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end
>> > > > ()?
>> > > 
>> > > I wasn't aware about these. I will try them.
>> > 
>> > I tested this and it doesn't help:
>> 
>> Okay. Well, I still find it weird that this would time out for one
>> case
>> and not time out for another... Do we have confirmation that this is
>> working fine for the AUX-Less ALPM case?
>
>I can reproduce this issue only with setup having two 4k monitors in DP
>ports and then one eDP panel. The issue is triggered on DP port. I.e.
>something that doesn't have AUX-Less ALPM. As it's clearly unnecessary
>to write this register on that failing port and not mentioned in HAS I
>was thinking just removing the failing write would work in this case.
>
>> 
>> I wonder if we should rather do this step together with
>> intel_c10_pll_program(). Note that, for C10, there is also a required
>> step to set PHY_C10_VDR_CONTROL1[2] before accessing the msgbus.
>
>Configuring this is a own step listed in HAS (6.k.ii). I can try if
>this works. I have no idea if it's ok to move it.

Hm... Well, not sure. Reading the spec on MacTransmitLFPS field, it
appears that this should be programmed after lane reset sequence is
done. By the time we call intel_c10_pll_program(), the lane reset step
is already done.

Another thing I think we should be doing, if we want to keep this as a
separate step and be aligned with Bspec, is to set
C10_VDR_CTRL_MSGBUS_ACCESS, just like it is done for other C10
progamming in the code. That is a requirement for programming C10 via
msg bus.

--
Gustavo Sousa

>
>> 
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > index ed8e640b96b0..e6ff7f07b2e3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > @@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct
>> > intel_encoder *encoder,
>> >                                 const struct intel_crtc_state
>> > *crtc_state)
>> > {
>> >        struct intel_display *display = to_intel_display(encoder);
>> > +       intel_wakeref_t wakeref;
>> >        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
>> >        bool enable =
>> > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>> >                                                  crtc_state);
>> > @@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct
>> > intel_encoder *encoder,
>> >        if (DISPLAY_VER(display) < 20)
>> >                return;
>> > 
>> > +       wakeref = intel_cx0_phy_transaction_begin(encoder);
>> > +
>> >        for (i = 0; i < 4; i++) {
>> >                int tx = i % 2 + 1;
>> >                u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
>> > INTEL_CX0_LANE1;
>> > @@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct
>> > intel_encoder *encoder,
>> >                              enable ? CONTROL0_MAC_TRANSMIT_LFPS :
>> > 0,
>> >                              MB_WRITE_COMMITTED);
>> >        }
>> > +
>> > +       intel_cx0_phy_transaction_end(encoder, wakeref);
>> > }
>> > 
>> > Do you think I should still add this change as well?
>> 
>> If we are still going with this function instead of doing it in
>> intel_c10_pll_program(), then yes.
>> 
>> --
>> Gustavo Sousa
>> 
>> > 
>> > > 
>> > > BR,
>> > > 
>> > > Jouni Högander
>> > > 
>> > > > 
>> > > > > 
>> > > > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to
>> > > > > configure
>> > > > > LFPS sending")
>> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> > > > > ---
>> > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------
>> > > > > 1 file changed, 5 insertions(+), 6 deletions(-)
>> > > > > 
>> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > > > index ed8e640b96b0..9cfc3187aeab 100644
>> > > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > > > > @@ -3239,14 +3239,14 @@ void
>> > > > > intel_lnl_mac_transmit_lfps(struct
>> > > > > intel_encoder *encoder,
>> > > > >                                  const struct
>> > > > > intel_crtc_state
>> > > > > *crtc_state)
>> > > > > {
>> > > > >         struct intel_display *display =
>> > > > > to_intel_display(encoder);
>> > > > > -        u8 owned_lane_mask =
>> > > > > intel_cx0_get_owned_lane_mask(encoder);
>> > > > > -        bool enable =
>> > > > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>> > > > > -                                                 
>> > > > > crtc_state);
>> > > > > +        u8 owned_lane_mask;
>> > > > >         int i;
>> > > > > 
>> > > > > -        if (DISPLAY_VER(display) < 20)
>> > > > > +        if (DISPLAY_VER(display) < 20 ||
>> > > > > +           
>> > > > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
>> > > > > crtc_state))
>> > > > >                 return;
>> > > > > 
>> > > > > +        owned_lane_mask =
>> > > > > intel_cx0_get_owned_lane_mask(encoder);
>> > > > 
>> > > > This optimization could be on it's own patch.
>> > 
>> > Ok, maybe I leave that out or add own patch.
>> > 
>> > BR,
>> > 
>> > Jouni Högander
>> > 
>> > 
>> > > > 
>> > > > --
>> > > > Gustavo Sousa
>> > > > 
>> > > > >         for (i = 0; i < 4; i++) {
>> > > > >                 int tx = i % 2 + 1;
>> > > > >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
>> > > > > INTEL_CX0_LANE1;
>> > > > > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct
>> > > > > intel_encoder *encoder,
>> > > > > 
>> > > > >                 intel_cx0_rmw(encoder, lane_mask,
>> > > > > PHY_CMN1_CONTROL(tx, 0),
>> > > > >                               CONTROL0_MAC_TRANSMIT_LFPS,
>> > > > > -                              enable ?
>> > > > > CONTROL0_MAC_TRANSMIT_LFPS
>> > > > > : 0,
>> > > > > -                              MB_WRITE_COMMITTED);
>> > > > > +                              CONTROL0_MAC_TRANSMIT_LFPS,
>> > > > > MB_WRITE_COMMITTED);
>> > > > >         }
>> > > > > }
>> > > > > 
>> > > > > -- 
>> > > > > 2.43.0
>> > > > > 
>> > > 
>> > 
>

Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

[Hogander, Jouni]

On Fri, 2025-07-18 at 10:45 -0300, Gustavo Sousa wrote:
> Quoting Hogander, Jouni (2025-07-18 10:08:52-03:00)
> > On Fri, 2025-07-18 at 09:58 -0300, Gustavo Sousa wrote:
> > > Quoting Hogander, Jouni (2025-07-18 07:46:31-03:00)
> > > > On Fri, 2025-07-18 at 09:05 +0300, Hogander, Jouni wrote:
> > > > > On Thu, 2025-07-17 at 10:31 -0300, Gustavo Sousa wrote:
> > > > > > Quoting Jouni Högander (2025-07-17 03:32:58-03:00)
> > > > > > > We are seeing "dmesg-warn/abort - *ERROR* PHY * failed
> > > > > > > after
> > > > > > > 3
> > > > > > > retries"
> > > > > > > since we started configuring LFPS sending. According to
> > > > > > > Bspec
> > > > > > > Configuring
> > > > > > > LFPS sending is needed only when using AUXLess ALPM. This
> > > > > > > patch
> > > > > > > avoids
> > > > > > > these failures by configuring LFPS sending only when
> > > > > > > using
> > > > > > > AUXLess
> > > > > > > ALPM.
> > > > > > 
> > > > > > Hm... But then with this patch we are missing writing zero
> > > > > > to
> > > > > > that
> > > > > > bit
> > > > > > when necessary, no?
> > > > > 
> > > > > That shouldn't be necessary as 0 is the reset value.
> > > > > 
> > > > > > 
> > > > > > Could the timeouts be happening because intel_cx0_rmw() is
> > > > > > getting
> > > > > > called without calling
> > > > > > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction
> > > > > > _end
> > > > > > ()?
> > > > > 
> > > > > I wasn't aware about these. I will try them.
> > > > 
> > > > I tested this and it doesn't help:
> > > 
> > > Okay. Well, I still find it weird that this would time out for
> > > one
> > > case
> > > and not time out for another... Do we have confirmation that this
> > > is
> > > working fine for the AUX-Less ALPM case?
> > 
> > I can reproduce this issue only with setup having two 4k monitors
> > in DP
> > ports and then one eDP panel. The issue is triggered on DP port.
> > I.e.
> > something that doesn't have AUX-Less ALPM. As it's clearly
> > unnecessary
> > to write this register on that failing port and not mentioned in
> > HAS I
> > was thinking just removing the failing write would work in this
> > case.
> > 
> > > 
> > > I wonder if we should rather do this step together with
> > > intel_c10_pll_program(). Note that, for C10, there is also a
> > > required
> > > step to set PHY_C10_VDR_CONTROL1[2] before accessing the msgbus.
> > 
> > Configuring this is a own step listed in HAS (6.k.ii). I can try if
> > this works. I have no idea if it's ok to move it.
> 
> Hm... Well, not sure. Reading the spec on MacTransmitLFPS field, it
> appears that this should be programmed after lane reset sequence is
> done. By the time we call intel_c10_pll_program(), the lane reset
> step
> is already done.
> 
> Another thing I think we should be doing, if we want to keep this as
> a
> separate step and be aligned with Bspec, is to set
> C10_VDR_CTRL_MSGBUS_ACCESS, just like it is done for other C10
> progamming in the code. That is a requirement for programming C10 via
> msg bus.

Tested this as well and still I'm seeing this:

[  118.454525] xe 0000:00:02.0: [drm] *ERROR* PHY I Read 0800 failed
after 3 retries.

I will add your suggestions as a separate patches to my set but I will
keep the patch avoiding lfps configuration when it's not needed.

BR,

Jouni Högander

> 
> --
> Gustavo Sousa
> 
> > 
> > > 
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > index ed8e640b96b0..e6ff7f07b2e3 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > @@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct
> > > > intel_encoder *encoder,
> > > >                                 const struct intel_crtc_state
> > > > *crtc_state)
> > > > {
> > > >        struct intel_display *display =
> > > > to_intel_display(encoder);
> > > > +       intel_wakeref_t wakeref;
> > > >        u8 owned_lane_mask =
> > > > intel_cx0_get_owned_lane_mask(encoder);
> > > >        bool enable =
> > > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > >                                                  crtc_state);
> > > > @@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct
> > > > intel_encoder *encoder,
> > > >        if (DISPLAY_VER(display) < 20)
> > > >                return;
> > > > 
> > > > +       wakeref = intel_cx0_phy_transaction_begin(encoder);
> > > > +
> > > >        for (i = 0; i < 4; i++) {
> > > >                int tx = i % 2 + 1;
> > > >                u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > > > INTEL_CX0_LANE1;
> > > > @@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct
> > > > intel_encoder *encoder,
> > > >                              enable ?
> > > > CONTROL0_MAC_TRANSMIT_LFPS :
> > > > 0,
> > > >                              MB_WRITE_COMMITTED);
> > > >        }
> > > > +
> > > > +       intel_cx0_phy_transaction_end(encoder, wakeref);
> > > > }
> > > > 
> > > > Do you think I should still add this change as well?
> > > 
> > > If we are still going with this function instead of doing it in
> > > intel_c10_pll_program(), then yes.
> > > 
> > > --
> > > Gustavo Sousa
> > > 
> > > > 
> > > > > 
> > > > > BR,
> > > > > 
> > > > > Jouni Högander
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to
> > > > > > > configure
> > > > > > > LFPS sending")
> > > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++--
> > > > > > > ----
> > > > > > > 1 file changed, 5 insertions(+), 6 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > > > index ed8e640b96b0..9cfc3187aeab 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > > > > > @@ -3239,14 +3239,14 @@ void
> > > > > > > intel_lnl_mac_transmit_lfps(struct
> > > > > > > intel_encoder *encoder,
> > > > > > >                                  const struct
> > > > > > > intel_crtc_state
> > > > > > > *crtc_state)
> > > > > > > {
> > > > > > >         struct intel_display *display =
> > > > > > > to_intel_display(encoder);
> > > > > > > -        u8 owned_lane_mask =
> > > > > > > intel_cx0_get_owned_lane_mask(encoder);
> > > > > > > -        bool enable =
> > > > > > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > > > > > -                                                 
> > > > > > > crtc_state);
> > > > > > > +        u8 owned_lane_mask;
> > > > > > >         int i;
> > > > > > > 
> > > > > > > -        if (DISPLAY_VER(display) < 20)
> > > > > > > +        if (DISPLAY_VER(display) < 20 ||
> > > > > > > +           
> > > > > > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > > > > > > crtc_state))
> > > > > > >                 return;
> > > > > > > 
> > > > > > > +        owned_lane_mask =
> > > > > > > intel_cx0_get_owned_lane_mask(encoder);
> > > > > > 
> > > > > > This optimization could be on it's own patch.
> > > > 
> > > > Ok, maybe I leave that out or add own patch.
> > > > 
> > > > BR,
> > > > 
> > > > Jouni Högander
> > > > 
> > > > 
> > > > > > 
> > > > > > --
> > > > > > Gustavo Sousa
> > > > > > 
> > > > > > >         for (i = 0; i < 4; i++) {
> > > > > > >                 int tx = i % 2 + 1;
> > > > > > >                 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > > > > > > INTEL_CX0_LANE1;
> > > > > > > @@ -3256,8 +3256,7 @@ void
> > > > > > > intel_lnl_mac_transmit_lfps(struct
> > > > > > > intel_encoder *encoder,
> > > > > > > 
> > > > > > >                 intel_cx0_rmw(encoder, lane_mask,
> > > > > > > PHY_CMN1_CONTROL(tx, 0),
> > > > > > >                               CONTROL0_MAC_TRANSMIT_LFPS,
> > > > > > > -                              enable ?
> > > > > > > CONTROL0_MAC_TRANSMIT_LFPS
> > > > > > > : 0,
> > > > > > > -                              MB_WRITE_COMMITTED);
> > > > > > > +                             
> > > > > > > CONTROL0_MAC_TRANSMIT_LFPS,
> > > > > > > MB_WRITE_COMMITTED);
> > > > > > >         }
> > > > > > > }
> > > > > > > 
> > > > > > > -- 
> > > > > > > 2.43.0
> > > > > > > 
> > > > > 
> > > > 
> >