Re: [PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform

[Gustavo Sousa <gustavo.sousa@intel.com>]

Quoting Lucas De Marchi (2025-10-16 23:26:30-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Provide the basic platform definitions and PCI IDs for NVL-S.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
>v2: Fix rebase on flags moving to the device descriptor (Gustavo)
>---
> drivers/gpu/drm/xe/xe_pci.c            | 12 ++++++++++++
> drivers/gpu/drm/xe/xe_platform_types.h |  1 +
> include/drm/intel/pciids.h             |  9 +++++++++
> 3 files changed, 22 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index fac46178cebba..0546442e2a631 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -377,6 +377,17 @@ static const struct xe_device_desc ptl_desc = {
>         .vm_max_level = 4,
> };
> 
>+static const struct xe_device_desc nvls_desc = {
>+        PLATFORM(NOVALAKE_S),
>+        .dma_mask_size = 46,
>+        .has_display = true,
>+        .has_flat_ccs = 1,
>+        .max_gt_per_tile = 2,
>+        .require_force_probe = true,
>+        .va_bits = 48,
>+        .vm_max_level = 4,
>+};
>+
> #undef PLATFORM
> __diag_pop();
> 
>@@ -405,6 +416,7 @@ static const struct pci_device_id pciidlist[] = {
>         INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>         INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>         INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>+        INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>         { }
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
>index 3e332214c7bb4..78286285c2495 100644
>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>@@ -24,6 +24,7 @@ enum xe_platform {
>         XE_LUNARLAKE,
>         XE_BATTLEMAGE,
>         XE_PANTHERLAKE,
>+        XE_NOVALAKE_S,
> };
> 
> enum xe_subplatform {
>diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>index 452c1de606ff2..13c592e1a28c7 100644
>--- a/include/drm/intel/pciids.h
>+++ b/include/drm/intel/pciids.h
>@@ -887,4 +887,13 @@
>         MACRO__(0xFD80, ## __VA_ARGS__), \
>         MACRO__(0xFD81, ## __VA_ARGS__)
> 
>+/* NVL-S */
>+#define INTEL_NVLS_IDS(MACRO__, ...) \
>+        MACRO__(0xD740, ## __VA_ARGS__), \
>+        MACRO__(0xD741, ## __VA_ARGS__), \
>+        MACRO__(0xD742, ## __VA_ARGS__), \
>+        MACRO__(0xD743, ## __VA_ARGS__), \
>+        MACRO__(0xD744, ## __VA_ARGS__), \
>+        MACRO__(0xD745, ## __VA_ARGS__)
>+
> #endif /* __PCIIDS_H__ */
>
>-- 
>2.51.0
>